TC1791 Data Sheet

32-Bit
Microcontroller
TC1791
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1 2014-05
Microcontrollers
Edition 2014-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
32-Bit
Microcontroller
TC1791
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1 2014-05
Microcontrollers
TC1791
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
2.1
System Overview of the TC1791 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
3
3.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
TC1791 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
4
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.6.1
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.4
5.5
5.5.1
5.5.2
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . 5-71
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75
Extended Range Operating Conditions . . . . . . . . . . . . . . . . . . . . . 5-81
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-99
Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . 5-104
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-110
Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . 5-113
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-116
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-118
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-120
ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . 5-123
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-124
DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-126
Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-127
Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 5-130
SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-132
ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-135
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140
Data Sheet
I-1
V 1.1, 2014-05
TC1791
5.5.3
6
Data Sheet
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
I-2
V 1.1, 2014-05
TC1791
Data Sheet
3
V 1.1, 2014-05
TC1791
Data Sheet
4
V 1.1, 2014-05
TC1791
Summary of Features
1
Summary of Features
The SAK-TC1791F-512F240EL / SAK-TC1791F-512F240EP
features:
•
•
•
•
•
•
•
•
has
the
following
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 240 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 4 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
Data Sheet
1
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
•
•
•
•
•
•
•
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
48 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
128 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1791ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
The SAK-TC1791F-512F200EL / SAK-TC1791F-512F200EP
features:
•
•
has
the
following
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 200 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
Data Sheet
2
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
•
•
•
•
•
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 4 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
44 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
Data Sheet
3
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
•
•
•
•
•
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
128 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1791ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
The SAK-TC1791F-384F200EL / SAK-TC1791F-384F200EP
features:
•
•
•
•
•
has
the
following
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 200 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 3 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Data Sheet
4
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
•
•
•
•
•
•
•
•
•
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
44 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
128 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1791ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Data Sheet
5
V 1.1, 2014-05
TC1791
Summary of Features
•
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
The SAK-TC1791S-512F240EP has the following features:
•
•
•
•
•
•
•
•
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 240 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 4 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
Data Sheet
6
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
•
•
•
•
•
•
•
•
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
48 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
128 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1791ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
Secure Hardware Extension (SHE)
– For further information please contact your Infineon representative
The SAK-TC1791S-384F200EP has the following features:
•
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 200 MHz operation at full temperature range
Data Sheet
7
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
•
•
•
•
•
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 3 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
44 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
Data Sheet
8
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
•
•
•
•
•
•
•
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
128 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1791ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
Secure Hardware Extension (SHE)
– For further information please contact your Infineon representative
The SAK-TC1791N-384F200EP has the following features:
•
•
•
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 200 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 3 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
Data Sheet
9
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
•
•
•
•
•
•
•
•
•
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
44 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
128 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1791ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Data Sheet
10
V 1.1, 2014-05
TC1791
Summary of Features
•
•
•
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
Data Sheet
11
V 1.1, 2014-05
TC1791
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery.
For the available ordering codes for the TC1791 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1
TC1791 Derivative Synopsis
Derivative
Ambient Temperature Range
SAK-TC1791F-512F240EL
TA = -40oC to +125oC
SAK-TC1791F-512F240EP
TA = -40oC to +125oC
SAK-TC1791F-512F200EL
TA = -40oC to +125oC
SAK-TC1791F-512F200EP
TA = -40oC to +125oC
SAK-TC1791F-384F200EL
TA = -40oC to +125oC
SAK-TC1791F-384F200EP
TA = -40oC to +125oC
SAK-TC1791S-512F240EP
TA = -40oC to +125oC
SAK-TC1791S-384F200EP
TA = -40oC to +125oC
SAK-TC1791N-384F200EP
TA = -40oC to +125oC
Data Sheet
12
V 1.1, 2014-05
TC1791
System Overview of the TC1791
2
System Overview of the TC1791
The TC1791 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
•
•
•
Reduced Instruction Set Computing (RISC) processor architecture
Digital Signal Processing (DSP) operations and addressing modes
On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1791 include:
•
•
•
•
•
•
•
•
•
Efficient memory organization: instruction and data scratch memories, caches
Serial communication interfaces – flexible synchronous and asynchronous modes
Peripheral Control Processor – standalone data operations and interrupt servicing
DMA Controller – DMA operations and interrupt servicing
General-purpose timers
High-performance on-chip buses
On-chip debugging and emulation facilities
Flexible interconnections to external components
Flexible power-management
The TC1791 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller and several on-chip peripherals. The TC1791 is designed to meet
the needs of the most demanding embedded control systems applications where the
competing issues of price/performance, real-time responsiveness, computational power,
data bandwidth, and power consumption are key design elements.
The TC1791 offers several versatile on-chip peripheral units such as serial controllers,
timer units, and Analog-to-Digital converters. Within the TC1791, all these peripheral
units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect
(FPI) Bus and the Cross Bar Interconnect (SRI). Several I/O lines on the TC1791 ports
are reserved for these peripheral units to communicate with the external world.
Data Sheet
13
V 1.1, 2014-05
TC1791
System Overview of the TC1791Block Diagram
2.1
Block Diagram
Figure 1 shows the block diagram of the SAK-TC1791F-512F240EL / SAK-TC1791F512F240EP / SAK-TC1791F-512F200EL / SAK-TC1791F-512F200EP.
FPU
PMI
DMI
LMU
TriCore
CPU
32 KB PSPR
16 KB ICACHE
128LDRAM
KB DSPR
16 KB DCACHE
DCACHE
128 KB
SRAM
M/S
S
M/S
EBU
Cross Bar Interconnect (SRI)
S
XBAR
S
S
PMU0
PMU1
M
M/S
2 MB PFlash
192 KB DFlash
16 KB BROM
KeyFlash
16 channels
(MemCheck)
(SFI)
2 MB PFlash
M/S
Interrupt
System
4
SSCG
M /S
PCP2
Core
4
Interrupts
ASC
SSC
E-Ray
2
SBCU
BMU
Ports
5V (3.3V supported as well)
Ext. ADC Supply
External
Request Unit
CCU6
(2xCCU6)
SENT
(8 channels )
FCE
2
GPT120
GPTA0
GPTA1
LTCA2
SDMA
8 channels
32 KB CMEM
(2 Channels)
MultiCAN
MLI
STM
SSC Guardian
(4 Nodes, 128 MO)
Interface/JTAG
2
M/S
16 KB PRAM
2
OCDS L 1 Debug
DMA
Bridge
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
PSPR:
Program Scratch-Pad RAM
DSPR:
Data Scratch-Padl Data RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
CMEM:
Code RAM in PCP
XBAR:
SRI Cross Bar (XBar_SRI)
S
:
On Chip Bus Slave Interface
M
:
On Chip Bus Master Interface
2
ADC0
ADC1
(5V max)
44
ADC2
SCU
MSC
FM-PLL
(LVDS)
PLL E-RAY
(3.3V max)
FADC
8
System Peripheral Bus (SPB)
3.3V
Ext. FADC Supply
TC1791
Figure 1
Data Sheet
Block Diagram
14
V 1.1, 2014-05
TC1791
System Overview of the TC1791Block Diagram
Figure 2 shows the block diagram of the SAK-TC1791F-384F200EL / SAK-TC1791F384F200EP.
FPU
PMI
DMI
LMU
TriCore
CPU
32 KB PSPR
16 KB ICACHE
128LDRAM
KB DSPR
16 KB DCACHE
DCACHE
128 KB
SRAM
M/S
S
M/S
EBU
Cross Bar Interconnect (SRI)
S
XBAR
S
S
PMU0
PMU1
M
M/S
2 MB PFlash
192 KB DFlash
16 KB BROM
KeyFlash
16 channels
(MemCheck)
(SFI)
1 MB PFlash
M/S
Interrupt
System
SSCG
PCP2
M /S
4
Core
4
Interrupts
ASC
SSC
2
SBCU
BMU
Ports
5V (3.3V supported as well)
Ext. ADC Supply
External
Request Unit
CCU6
(2xCCU6)
SENT
(8 channels )
FCE
2
GPT120
GPTA 0
GPTA1
SDMA
8 channels
32 KB CMEM
E-Ray
(2 Channels)
MultiCAN
MLI
STM
SSC Guardian
(4 Nodes, 128 MO)
Interface/JTAG
2
M/S
16 KB PRAM
2
OCDS L 1 Debug
DMA
Bridge
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
PSPR:
Program Scratch-Pad RAM
DSPR:
Data Scratch-Padl Data RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
CMEM:
Code RAM in PCP
XBAR:
SRI Cross Bar (XBar_SRI)
S
:
On Chip Bus Slave Interface
M
:
On Chip Bus Master Interface
2
ADC0
ADC1
(5V max)
44
ADC2
SCU
MSC
FM-PLL
(LVDS)
PLL E-RAY
(3.3V max)
FADC
8
System Peripheral Bus (SPB)
LTCA2
3.3V
Ext. FADC Supply
TC1791
Figure 2
Block Diagram
Figure 3 shows the block diagram of the SAK-TC1791S-512F240EP.
Data Sheet
15
V 1.1, 2014-05
TC1791
System Overview of the TC1791Block Diagram
FPU
PMI
DMI
LMU
TriCore
CPU
32 KB PSPR
16 KB ICACHE
128LDRAM
KB DSPR
16 KB DCACHE
DCACHE
128 KB
SRAM
M/S
S
M/S
EBU
Cross Bar Interconnect (SRI)
S
XBAR
S
S
PMU0
PMU1
M
M/S
2 MB PFlash
192 KB DFlash
16 KB BROM
KeyFlash
16 channels
(MemCheck)
(SFI)
2 MB PFlash
M/S
4
SSCG
M /S
PCP2
Core
4
Interrupts
ASC
SSC
SSC Guardian
(4 Nodes, 128 MO)
2
Interrupt
System
8 channels
STM
SHE
SBCU
BMU
Ports
5V (3.3V supported as well)
Ext. ADC Supply
External
Request Unit
CCU6
(2xCCU6)
SENT
(8 channels )
FCE
2
GPT120
GPTA0
GPTA1
MLI
SDMA
32 KB CMEM
E-Ray
(2 Channels)
MultiCAN
Interface/JTAG
2
M/S
16 KB PRAM
2
OCDS L 1 Debug
DMA
Bridge
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
PSPR:
Program Scratch-Pad RAM
DSPR:
Data Scratch-Padl Data RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
CMEM:
Code RAM in PCP
XBAR:
SRI Cross Bar (XBar_SRI)
S
:
On Chip Bus Slave Interface
M
:
On Chip Bus Master Interface
2
ADC0
ADC1
(5V max)
44
ADC2
SCU
MSC
FM-PLL
(LVDS)
PLL E-RAY
(3.3V max)
FADC
8
System Peripheral Bus (SPB)
LTCA2
3.3V
Ext. FADC Supply
TC1791
Figure 3
Block Diagram
Figure 4 shows the block diagram of the SAK-TC1791S-384F200EP.
Data Sheet
16
V 1.1, 2014-05
TC1791
System Overview of the TC1791Block Diagram
FPU
PMI
DMI
LMU
TriCore
CPU
32 KB PSPR
16 KB ICACHE
128LDRAM
KB DSPR
16 KB DCACHE
DCACHE
128 KB
SRAM
M/S
S
M/S
EBU
Cross Bar Interconnect (SRI)
S
XBAR
S
S
PMU0
PMU1
M
M/S
2 MB PFlash
192 KB DFlash
16 KB BROM
KeyFlash
16 channels
(MemCheck)
(SFI)
1 MB PFlash
M/S
4
SSCG
M /S
PCP2
Core
4
Interrupts
ASC
SSC
SSC Guardian
(4 Nodes, 128 MO)
2
Interrupt
System
8 channels
STM
SHE
SBCU
BMU
Ports
5V (3.3V supported as well)
Ext. ADC Supply
External
Request Unit
CCU6
(2xCCU6)
SENT
(8 channels )
FCE
2
GPT120
GPTA0
GPTA1
LTCA2
MLI
SDMA
32 KB CMEM
E-Ray
(2 Channels)
MultiCAN
Interface/JTAG
2
M/S
16 KB PRAM
2
OCDS L 1 Debug
DMA
Bridge
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
PSPR:
Program Scratch-Pad RAM
DSPR:
Data Scratch-Padl Data RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
CMEM:
Code RAM in PCP
XBAR:
SRI Cross Bar (XBar_SRI)
:
On Chip Bus Slave Interface
S
:
On Chip Bus Master Interface
M
2
ADC0
ADC1
(5V max)
44
ADC2
SCU
MSC
FM-PLL
(LVDS)
PLL E-RAY
(3.3V max)
FADC
8
System Peripheral Bus (SPB)
3.3V
Ext. FADC Supply
TC1791
Figure 4
Block Diagram
Figure 5 shows the block diagram of the SAK-TC1791N-384F200EP.
Data Sheet
17
V 1.1, 2014-05
TC1791
System Overview of the TC1791Block Diagram
FPU
PMI
DMI
LMU
TriCore
CPU
32 KB PSPR
16 KB ICACHE
128LDRAM
KB DSPR
16 KB DCACHE
DCACHE
128 KB
SRAM
M/S
S
M/S
EBU
Cross Bar Interconnect (SRI)
S
XBAR
S
S
PMU0
PMU1
M
M/S
2 MB PFlash
192 KB DFlash
16 KB BROM
KeyFlash
16 channels
(MemCheck)
(SFI)
1 MB PFlash
M/S
Interrupt
System
4
SSCG
M /S
PCP2
Core
4
Interrupts
ASC
SSC
Interface/JTAG
2
MLI
M/S
16 KB PRAM
2
OCDS L 1 Debug
DMA
Bridge
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
PSPR:
Program Scratch-Pad RAM
DSPR:
Data Scratch-Padl Data RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
CMEM:
Code RAM in PCP
XBAR:
SRI Cross Bar (XBar_SRI)
:
On Chip Bus Slave Interface
S
:
On Chip Bus Master Interface
M
SDMA
8 channels
STM
SSC Guardian
SBCU
BMU
Ports
5V (3.3V supported as well)
Ext. ADC Supply
32 KB CMEM
MultiCAN
(4 Nodes, 128 MO)
2
SENT
(8 channels )
External
Request Unit
CCU6
(2xCCU6)
FCE
2
GPT120
GPTA0
GPTA1
LTCA2
2
ADC0
ADC1
(5V max)
44
ADC2
SCU
MSC
FM-PLL
(LVDS)
PLL E-RAY
(3.3V max)
FADC
8
System Peripheral Bus (SPB)
3.3V
Ext. FADC Supply
TC1791
Figure 5
Data Sheet
Block Diagram
18
V 1.1, 2014-05
TC1791
Pinning
3
Pinning
Figure 6 is showing the TC1791 Logic Symbol.
General Control
Alternate Functions :
PORST
TESTMODE
14
ESR0
6
ESR1
10
TRST
4
TCK / DAP0
OCDS /
JTAG Control
13
TDI / BRKIN/
BRKOUT
16
TDO /BRKOUT/
DAP2 / BRKIN
12
TMS / DAP1
6
XTAL1
8
XTAL2
Oscillator
12
V D DOSC
VDD OSC3
6
VSSOSC
16
TC1791
VD D PF
VD DPF3
5
16
10
Digital Circuitry
Power Supply
VD DP
12
VDD
2
VD D FL3
VSS
VSSP
V
13
Port 2
GPTA / SSC0 / SSC1
Port 3
GPTA / CCU6 / GPT12
Port 4
Port 5
Port 6
Port 7
GPTA / SSC2 / CCU6 / GPT12
ASC0 / ASC1 / MSC0 / LVDS /
MLI0 / MLI1 / CCU6 / GPT12
ASC0 / ASC1 / SSC1 / CAN /
E-RAY / CCU6 / GPT12
ERU / ADC-Mux / SSC3
Port 9
MLI 1 / GPTA / SENT /
CCU6 / GPT12
MSC0 / MSC1 / GPTA /
SENT / CCU6 / GPT12
Port 10
SSC0
Port 13
GPTA
Port 14
GPTA / CCU6 / GPT12
Port 17
SENT
(Overlay with Analog Inputs )
Port 8
3
VSSAF
V SS MF
VFAGND
VFAR EF
VD DMF
VD DAF
3
V
N.C.
Port 1
1)
GPTA / HWCFG / E-RAY /
GPT12
GPTA / ERU / SSC1 / SSC3 /
CCU6 / GPT12
1) Only available for SAK-TC 1791S-512F240EP,
SAK-TC 1791F-512F240EP, SAK-TC 1791F512F240EL, SAK-TC 1791S-384F200EP, SAKTC 1791F-384F200EL, SAK-TC1791F-384F200EP,
and SAK-TC 1791F-384F200EL.
48
DD SB
(ED only, N.C. in PD)
FADC Analog
Power Supply
Port 0
AN[47:0]
ADC / FADC
Analog Inputs
VAR EFx
VAGND
VDD M
VSSM
ADC0 /ADC1 / ADC2
Analog Power Supply
2
TC 1791_LogSym_292
Figure 6
Data Sheet
TC1791 Logic Symbol
19
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
3.1
TC1791 Pin Configuration
This chapter shows the pin configuration of the TC1791 package PG-LFBGA- 292-6.
20
19
18
17
16
15
14
13
12
11
Y VSS P14.6 P14.8 VSSP P10.5 P10.0 P10.3 P4.7
P4.3 VSSP
W VDD
P4.2 VDDP
VSS P14.4 VDDP P10.4 P10.1 P4.10 P4.6
10
9
8
7
6
5
4
3
2
VSS
VA
VA AN39 AN37
AN30 AN26
AN34 AN1
MF
GND0 REF0 P17.11 P17.9
VFA
VA
VA AN38 AN36
AN29 AN25
AN33 AN2
GND
REF2 REF1 P17.10 P17.8
V P14.2 VDD
1
NC
AN3
AN4 AN44
U P14.0 P13.15
VSS P10.2 P4.14 P4.9
P4.5
P4.1
VDD VFA
AN43 AN41
AN28 AN24
AN47 AN32
MF REF
P17.15 P17.13
T P13.14 P13.13
VDD VSS P4.12 P4.8
P4.4
P4.0
VDD
AN42 AN40
AN31 AN27 AN35
AN7
P17.14 P17.12
AF
AN5 AN45
AN0
AN6 AN46
P13.10 VDD
AN8 AN9
P17.0 P17.1
VDDM VSSM
P P13.9 P13.8
P13.7 P13.6
AN10 AN11
P17.2 P17.3
AN12 AN13
P17.4 P17.5
N P13.5 P13.4
P13.3 P13.2
VDD
VDD
AN16 AN17
AN14 AN15
P17.6 P17.7
M VDDP VDDP
P13.1 P13.0
VSS
VSS
VSS
VSS
AN18 AN19
AN20 AN21
L VSSP VSSP
VDD VDD
PF3 FL3
VSS
VSS
VSS
VSS
NC
NC
AN22 AN23
K XTAL1 XTAL2
VDD VDD
PF OSC3
VSS
VSS
VSS
VSS
VDD
FL3
P7.5
VDDP VSSP
TDI
TMS
VSS
VSS
VSS
VSS
P7.4
P7.3
P7.2
H TCK TRST
TDO P9.14
VDD
VDD
P7.0
P1.1
P1.12 P1.0
G ESR1 ESR0
Test
P9.13
mode
P1.9
P8.6
P1.6
P1.7
F P9.10 PORST
P9.5
P8.5
P8.7
P8.4
P8.0
E P9.7
P9.8
P9.0 VSSP P5.5
D P9.2
P9.1
VSSP P5.7
C P9.3
P9.4
R P13.12 P13.11
J
VSS VDD
OSC OSC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD VSS
VSS
VSS
VSS
VDD
VDD
P9.6
P3.0
P3.4 P3.12 P0.1
P5.2 P5.12 P3.10 P0.0
P5.8
P0.2
P0.7
P7.1
P0.3
P0.5
P2.6
P8.1
VSSP P8.2
P8.3 P6.15
P0.4
P0.6 P2.10 P2.5
P2.4
P6.7 VSSP
P6.11 P6.14
P5.3 P5.13 P5.14 P0.10 P0.13 VDDP P0.9 P2.12 P2.7
A VSSP VDDP P5.4 P5.11 P5.10 P5.0
Data Sheet
VSS
P6.10 P6.13
B P5.6 VSSP VDDP P5.9
Figure 7
VDD VSS
P5.1 P5.15 P0.11 P0.12 VSSP P0.14 P2.14 P2.8
P2.3
P6.8
P6.4 VDDP VSSP P6.12
P2.2
P6.9
P6.6
P6.5 VDDP NC
TC1791 Pinning for PG-LFBGA-292 Package
20
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Table 2
Pin
Pin Definitions and Functions
Symbol
Ctrl.
Type Function
P0.0
I/O
HWCFG0
I
A1+/
PU
OUT56
O1
OUT56 Line of GPTA0
OUT56
O2
OUT56 Line of GPTA1
OUT80
O3
OUT80 Line of LTCA2
P0.1
I/O
HWCFG1
I
OUT57
O1
OUT57 Line of GPTA0
OUT57
O2
OUT57 Line of GPTA1
OUT81
O3
OUT81 Line of LTCA2
P0.2
I/O
HWCFG2
I
OUT58
O1
OUT58 Line of GPTA0
OUT58
O2
OUT58 Line of GPTA1
OUT82
O3
OUT82 Line of LTCA2
P0.3
I/O
HWCFG3
I
OUT59
O1
OUT59 Line of GPTA0
OUT59
O2
OUT59 Line of GPTA1
OUT83
O3
OUT83 Line of LTCA2
Port 0
D12
E11
D11
E10
Data Sheet
A1/
PU
A2/
PU
A1/
PU
Port 0 General Purpose I/O Line 0
Hardware Configuration Input 0
Port 0 General Purpose I/O Line 1
Hardware Configuration Input 1
Port 0 General Purpose I/O Line 2
Hardware Configuration Input 2
Port 0 General Purpose I/O Line 3
Hardware Configuration Input 3
21
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D10
P0.4
I/O
HWCFG4
I
A1/
PU
OUT60
O1
OUT60 Line of GPTA0
OUT60
O2
OUT60 Line of GPTA1
EVTO0
O3
MCDS Output Event 01)
P0.5
I/O
HWCFG5
I
OUT61
O1
OUT61 Line of GPTA0
OUT61
O2
OUT61 Line of GPTA1
EVTO1
O3
MCDS Output Event 11)
P0.6
I/O
HWCFG6
I
OUT62
O1
OUT62 Line of GPTA0
OUT62
O2
OUT62 Line of GPTA1
EVTO2
O3
MCDS Output Event 21)
P0.7
I/O
HWCFG7
I
OUT63
O1
OUT63 Line of GPTA0
OUT63
O2
OUT63 Line of GPTA1
EVTO3
O3
MCDS Output Event 31)
P0.9
I/O
RXDA0
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
E9
D9
E8
B9
Data Sheet
A1/
PU
A2/
PU
A1/
PU
A1/
PU
Port 0 General Purpose I/O Line 4
Hardware Configuration Input 4
Port 0 General Purpose I/O Line 5
Hardware Configuration Input 5
Port 0 General Purpose I/O Line 6
Hardware Configuration Input 6
Port 0 General Purpose I/O Line 7
Hardware Configuration Input 7
Port 0 General Purpose I/O Line 9
E-Ray Channel A Receive Data Input 0 2)
22
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B12
P0.10
I/O
TXENA
O1
A2/
PU
Reserved
O2
-
Reserved
O3
-
P0.11
I/O
T5INB
I
T5INA
I
GPT121
TXENB
O1
E-Ray Channel B transmit Data Output
enable 2)
Reserved
O2
-
Reserved
O3
-
P0.12
I/O
T5EUDA
I
T5EUDB
I
GPT121
TXDB
O1
E-Ray Channel B transmit Data Output 2)
Reserved
O2
-
Reserved
O3
-
P0.13
I/O
RXDB0
I
T5EUDB
I
GPT120
T5EUDA
I
GPT121
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
A12
A11
B11
Data Sheet
A2/
PU
A2/
PU
A1/
PU
Port 0 General Purpose I/O Line 10
E-Ray Channel A transmit Data Output
enable 2)
Port 0 General Purpose I/O Line 11
GPT120
Port 0 General Purpose I/O Line 12
GPT120
Port 0 General Purpose I/O Line 13
E-Ray Channel B Receive Data Input 0 2)
23
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A9
P0.14
I/O
T6INA
I
A2/
PU
T6INB
I
GPT121
TXDA
O1
E-Ray Channel A transmit Data Output 2)
Reserved
O2
-
Reserved
O3
-
P1.0
I/O
REQ0
I
EXTCLK1
O1
External Clock Output 1
Reserved
O2
-
Reserved
O3
-
P1.1
I/O
REQ1
I
CC60INA
I
CCU60
CC60INB
I
CCU61
CC60
O1
CCU60
Reserved
O2
-
Reserved
O3
-
P1.6
I/O
TVALID0A
O1
SLSO10
O2
SSC1 Slave Select Output Line 10
COUT60
O3
CCU60
Port 0 General Purpose I/O Line 14
GPT120
Port 1
H1
H4
G2
Data Sheet
A2/
PU
A1/
PU
A2/
PU
Port 1 General Purpose I/O Line 0
External trigger Input 0
Port 1 General Purpose I/O Line 1
External trigger Input 1
Port 1 General Purpose I/O Line 6
MLI0 transmit Channel valid Output A
24
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
G1
P1.7
I/O
CC61INB
I
A2/
PU
CC61INA
I
CCU61
TData0
O1
MLI0 transmit Channel Data Output
CC61
O2
CCU61
T3OUT
O3
GPT120
P1.9
I/O
RREADY0A
O1
SLSO11
O2
SSC1 Slave Select Output Line 11
OUT65
O3
OUT65 Line of GPTA0
P1.12
I/O
EXTCLK0
O1
OUT68
O2
OUT68 Line of GPTA0
OUT68
O3
OUT68 Line of GPTA1
P2.2
I/O
SLSO02
O1
SLSO12
O2
SSC1 Slave Select Output Line 12
SLSO02
AND
SLSO12
O3
SSC0 & SSC1 Slave Select Output Line 2
AND Slave Select Output Line 12
P2.3
I/O
SLSO03
O1
SLSO13
O2
SSC1 Slave Select Output Line 13
SLSO03
AND
SLSO13
O3
SSC0 & SSC1 Slave Select Output Line 3
AND Slave Select Output Line 13
G5
H2
A2/
PU
A2/
PU
Port 1 General Purpose I/O Line 7
CCU60
Port 1 General Purpose I/O Line 9
MLI0 Receive Channel ready Output A
Port 1 General Purpose I/O Line 12
External Clock Output 0
Port 2
A6
B6
Data Sheet
A1+/
PU
A1+/
PU
Port 2 General Purpose I/O Line 2
SSC0 Slave Select Output Line 2
Port 2 General Purpose I/O Line 3
SSC0 Slave Select Output Line 3
25
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D6
P2.4
I/O
SLSO04
O1
A1+/
PU
SLSO14
O2
SSC1 Slave Select Output Line 14
SLSO04
AND
SLSO14
O3
SSC0 & SSC1 Slave Select Output Line 4
AND Slave Select Output Line 14
P2.5
I/O
SLSO05
O1
SLSO15
O2
SSC1 Slave Select Output Line 15
SLSO05
AND
SLSO15
O3
SSC0 & SSC1 Slave Select Output Line 5
AND Slave Select Output Line 15
P2.6
I/O
SLSO06
O1
SLSO16
O2
SSC1 Slave Select Output Line 16
SLSO06
AND
SLSO16
O3
SSC0 & SSC1 Slave Select Output Line 6
AND Slave Select Output Line 16
P2.7
I/O
SLSO07
O1
SLSO17
O2
SSC1 Slave Select Output Line 17
SLSO07
AND
SLSO17
O3
SSC0 & SSC1 Slave Select Output Line
7AND Slave Select Output Line 17
D7
E7
B7
Data Sheet
A1+/
PU
A1+/
PU
A1+/
PU
Port 2 General Purpose I/O Line 4
SSC0 Slave Select Output Line 4
Port 2 General Purpose I/O Line 5
SSC0 Slave Select Output Line 5
Port 2 General Purpose I/O Line 6
SSC0 Slave Select Output Line 6
Port 2 General Purpose I/O Line 7
SSC0 Slave Select Output Line 7
26
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A7
P2.8
I/O
IN0
I
A1/
PU
IN0
I
IN0 Line of GPTA1
IN0
I
IN0 Line of LTCA2
CCPOS0A
I
CCU62
T12HRB
I
CCU63
T3INB
I
GPT120
T3INA
I
GPT121
OUT0
O1
OUT0 Line of GPTA0
OUT0
O2
OUT0 Line of GPTA1
OUT0
O3
OUT0 Line of LTCA2
P2.10
I/O
IN2
I
IN2
I
IN2 Line of GPTA1
IN2
I
IN2 Line of LTCA2
T12HRE
I
CCU60
CC61INC
I
CCU60
CTRAPA
I
CCU61
CTRAPB
I
CCU63
CC60INC
I
CCU61
OUT2
O1
OUT2 Line of GPTA0
OUT2
O2
OUT2 Line of GPTA1
OUT2
O3
OUT2 Line of LTCA2
D8
Data Sheet
A1/
PU
Port 2 General Purpose I/O Line 8
IN0 Line of GPTA0
Port 2 General Purpose I/O Line 10
IN2 Line of GPTA0
27
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B8
P2.12
I/O
IN4
I
A1/
PU
IN4
I
IN4 Line of GPTA1
IN4
I
IN4 Line of LTCA2
T12HRB
I
CCU62
CCPOS0A
I
CCU63
T2INB
I
GPT120
T2INA
I
GPT121
OUT4
O1
OUT4 Line of GPTA0
OUT4
O2
OUT4 Line of GPTA1
OUT4
O3
OUT4 Line of LTCA2
P2.14
I/O
IN6
I
IN6
I
IN6 Line of GPTA1
IN6
I
IN6 Line of LTCA2
CCPOS0A
I
CCU60
T12HRB
I
CCU61
T3INA
I
GPT120
T3INB
I
GPT121
OUT6
O1
OUT6 Line of GPTA0
OUT6
O2
OUT6 Line of GPTA1
OUT6
O3
OUT6 Line of LTCA2
A8
A1/
PU
Port 2 General Purpose I/O Line 12
IN4 Line of GPTA0
Port 2 General Purpose I/O Line 14
IN6 Line of GPTA0
Port 3
Data Sheet
28
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
E14
P3.0
I/O
IN8
I
A1/
PU
IN8
I
IN8 Line of GPTA1
IN8
I
IN8 Line of LTCA2
CTRAPA
I
CCU62
CTRAPB
I
CCU61
CC60INC
I
CCU62
T12HRE
I
CCU63
CC61INC
I
CCU63
T5INA
I
GPT120
T5INB
I
GPT121
OUT8
O1
OUT8 Line of GPTA0
OUT8
O2
OUT8 Line of GPTA1
OUT8
O3
OUT8 Line of LTCA2
P3.4
I/O
IN12
I
IN12
I
IN12 Line of GPTA1
IN12
I
IN12 Line of LTCA2
T12HRE
I
CCU62
CC61INC
I
CCU62
CTRAPA
I
CCU63
CTRAPB
I
CCU60
CC60INC
I
CCU63
OUT12
O1
OUT12 Line of GPTA0
OUT12
O2
OUT12 Line of GPTA1
OUT12
O3
OUT12 Line of LTCA2
E13
Data Sheet
A1/
PU
Port 3 General Purpose I/O Line 0
IN8 Line of GPTA0
Port 3 General Purpose I/O Line 4
IN12 Line of GPTA0
29
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D13
P3.10
I/O
IN18
I
A1+/
PU
IN18
I
IN18 Line of GPTA1
IN18
I
IN18 Line of LTCA2
CCPOS1A
I
CCU62
T13HRB
I
CCU63
T3EUDB
I
GPT120
T3EUDA
I
GPT121
OUT18
O1
OUT18 Line of GPTA0
OUT18
O2
OUT18 Line of GPTA1
OUT18
O3
OUT18 Line of LTCA2
P3.12
I/O
IN20
I
IN20
I
IN20 Line of GPTA1
IN20
I
IN20 Line of LTCA2
CCPOS2A
I
CCU62
T12HRC
I
CCU63
T13HRC
I
CCU63
T4INB
I
GPT120
T4INA
I
GPT121
OUT20
O1
OUT20 Line of GPTA0
OUT20
O2
OUT20 Line of GPTA1
OUT20
O3
OUT20 Line of LTCA2
E12
A1/
PU
Port 3 General Purpose I/O Line 10
IN18 Line of GPTA0
Port 3 General Purpose I/O Line 12
IN20 Line of GPTA0
Port 4
Data Sheet
30
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
T12
P4.0
I/O
IN24
I
A1+/
PU
IN24
I
IN24 Line of GPTA1
IN24
I
IN24 Line of LTCA2
MRST2A
I
SSC2 Master Receive Input A (Master Mode)
OUT24
O1
OUT24 Line of GPTA0
OUT24
O2
OUT24 Line of GPTA1
MRST2
O3
SSC2 Slave Transmit Output (Slave Mode)
P4.1
I/O
IN25
I
IN25
I
IN25 Line of GPTA1
IN25
I
IN25 Line of LTCA2
MTSR2A
I
SSC2 Slave Receive Input A (Slave Mode)
MRSTG2A
I
SSC Guardian 2 Master Receive Input A
(Master Mode)3)
OUT25
O1
OUT25 Line of GPTA0
OUT25
O2
OUT25 Line of GPTA1
MTSR2
O3
SSC2 Master Transmit Output (Master
Mode)
U12
Data Sheet
A1+/
PU
Port 4 General Purpose I/O Line 0
IN24 Line of GPTA0
Port 4 General Purpose I/O Line 1
IN25 Line of GPTA0
31
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
W12
P4.2
I/O
IN26
I
A1+/
PU
IN26
I
IN26 Line of GPTA1
IN26
I
IN26 Line of LTCA2
SCLK2
I
SSC2 Input
OUT26
O1
OUT26 Line of GPTA0
OUT26
O2
OUT26 Line of GPTA1
SCLK2
O3
SSC2 Output
P4.3
I/O
IN27
I
IN27
I
IN27 Line of GPTA1
IN27
I
IN27 Line of LTCA2
OUT27
O1
OUT27 Line of GPTA0
OUT27
O2
OUT27 Line of GPTA1
SLSO20
O3
SSC2 Output
P4.4
I/O
IN28
I
IN28
I
IN28 Line of GPTA1
IN28
I
IN28 Line of LTCA2
OUT28
O1
OUT28 Line of GPTA0
OUT28
O2
OUT28 Line of GPTA1
SLSO21
O3
SSC2 Output
Y12
T13
Data Sheet
A1+/
PU
A1+/
PU
Port 4 General Purpose I/O Line 2
IN26 Line of GPTA0
Port 4 General Purpose I/O Line 3
IN27 Line of GPTA0
Port 4 General Purpose I/O Line 4
IN28 Line of GPTA0
32
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
U13
P4.5
I/O
IN29
I
A1+/
PU
IN29
I
IN29 Line of GPTA1
IN29
I
IN29 Line of LTCA2
OUT29
O1
OUT29 Line of GPTA0
OUT29
O2
OUT29 Line of GPTA1
SLSO22
O3
SSC2 Output
P4.6
I/O
IN30
I
IN30
I
IN30 Line of GPTA1
IN30
I
IN30 Line of LTCA2
OUT30
O1
OUT30 Line of GPTA0
OUT30
O2
OUT30 Line of GPTA1
SLSO23
O3
SSC2 Output
P4.7
I/O
IN31
I
IN31
I
IN31 Line of GPTA1
IN31
I
IN31Line of LTCA2
T6INB
I
GPT120
T6INA
I
GPT121
OUT31
O1
OUT31 Line of GPTA0
OUT31
O2
OUT31 Line of GPTA1
SLSO24
O3
SSC2 Output
W13
Y13
Data Sheet
A1+/
PU
A1+/
PU
Port 4 General Purpose I/O Line 5
IN29 Line of GPTA0
Port 4 General Purpose I/O Line 6
IN30 Line of GPTA0
Port 4 General Purpose I/O Line 7
IN31 Line of GPTA0
33
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
T14
P4.8
I/O
IN32
I
A1/
PU
IN32
I
IN32 Line of GPTA1
CCPOS1A
I
CCU60
T13HRB
I
CCU61
T3EUDA
I
GPT120
T3EUDB
I
GPT121
OUT32
O1
OUT32 Line of GPTA0
OUT32
O2
OUT32 Line of GPTA1
OUT0
O3
OUT0 Line of LTCA2
P4.9
I/O
IN33
I
IN33
I
IN33 Line of GPTA1
CCPOS2A
I
CCU60
T12HRC
I
CCU61
T13HRC
I
CCU61
T4INA
I
GPT120
T4INB
I
GPT121
SLSI2
I
SSC2
OUT33
O1
OUT33 Line of GPTA0
OUT33
O2
OUT33 Line of GPTA1
OUT1
O3
OUT1 Line of LTCA2
AB19
Data Sheet
A1/
PU
Port 4 General Purpose I/O Line 8
IN32 Line of GPTA0
Port 4 General Purpose I/O Line 9
IN33 Line of GPTA0
34
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
W14
P4.10
I/O
IN34
I
A1/
PU
IN34
I
IN34 Line of GPTA1
T12HRB
I
CCU60
CCPOS0A
I
CCU61
T2INA
I
GPT120
T2INB
I
GPT121
OUT34
O1
OUT34 Line of GPTA0
OUT34
O2
OUT34 Line of GPTA1
OUT2
O3
OUT2 Line of LTCA2
P4.12
I/O
IN36
I
IN36
I
IN36 Line of GPTA1
T13HRB
I
CCU60
CCPOS1A
I
CCU61
T2EUDA
I
GPT120
T2EUDB
I
GPT121
OUT36
O1
OUT36 Line of GPTA0
OUT36
O2
OUT36 Line of GPTA1
OUT4
O3
OUT4 Line of LTCA2
T15
Data Sheet
A1/
PU
Port 4 General Purpose I/O Line 10
IN34 Line of GPTA0
Port 4 General Purpose I/O Line 12
IN36 Line of GPTA0
35
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
U15
P4.14
I/O
IN38
I
A1/
PU
IN38
I
IN38 Line of GPTA1
T12HRC
I
CCU60
T13HRC
I
CCU60
CCPOS2A
I
CCU61
T4EUDA
I
GPT120
T4EUDB
I
GPT121
OUT38
O1
OUT38 Line of GPTA0
OUT38
O2
OUT38 Line of GPTA1
OUT6
O3
OUT6 Line of LTCA2
P5.0
I/O
RXD0A
I
T6EUDA
I
GPT120
T6EUDB
I
GPT121
RXD0A
O1
ASC0 Receiver Input/Output A
OUT72
O2
OUT72 Line of GPTA0
OUT72
O3
OUT72 Line of GPTA1
P5.1
I/O
TXD0
O1
OUT73
O2
OUT73 Line of GPTA0
OUT73
O3
OUT73 Line of GPTA1
Port 4 General Purpose I/O Line 14
IN38 Line of GPTA0
Port 5
A15
A14
Data Sheet
A1+/
PU
A1+/
PU
Port 5 General Purpose I/O Line 0
ASC0 Receiver Input/Output A
Port 5 General Purpose I/O Line 1
ASC0 Transmitter Output A
36
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D15
P5.2
I/O
RXD1A
I
A2/
PU
RXD1A
O1
ASC1 Receiver Input/Output A
OUT74
O2
OUT74 Line of GPTA0
OUT74
O3
OUT74 Line of GPTA1
P5.3
I/O
TXD1
O1
OUT75
O2
OUT75 Line of GPTA0
OUT75
O3
OUT75 Line of GPTA1
P5.4
I/O
T13HRB
I
CCPOS1A
I
CCU63
T2EUDB
I
GPT120
T2EUDA
I
GPT121
EN00
O1
MSC0 Device Select Output 0
RREADY0B
O2
MLI0 Receive Channel ready Output B
OUT76
O3
OUT76 Line of GPTA0
B15
A18
Data Sheet
A1+/
PU
A2/
PU
Port 5 General Purpose I/O Line 2
ASC1 Receiver Input/Output A
Port 5 General Purpose I/O Line 3
ASC1 Transmitter Output A
Port 5 General Purpose I/O Line 4
CCU62
37
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
E15
P5.5
I/O
SDI0
I
A1+/
PU
T12HRC
I
CCU62
T13HRC
I
CCU62
CCPOS2A
I
CCU63
T4EUDB
I
GPT120
T4EUDA
I
GPT121
OUT77
O1
OUT77 Line of GPTA0
OUT77
O2
OUT77 Line of GPTA1
OUT101
O3
OUT101 Line of LTCA2
P5.6
I/O
CC60INA
I
CC60INB
I
CCU63
EN10
O1
MSC1 Device Select Output 0
TVALID0B
O2
MLI0 transmit Channel valid Output B
CC60
O3
CCU62
P5.7
I/O
SDI1
I
CC61INA
I
CCU62
CC61INB
I
CCU63
OUT79
O1
OUT79 Line of GPTA0
OUT79
O2
OUT79 Line of GPTA1
CC61
O3
CCU62
B20
D16
Data Sheet
A2/
PU
A1+/
PU
Port 5 General Purpose I/O Line 5
MSC0 Serial Data Input
Port 5 General Purpose I/O Line 6
CCU62
Port 5 General Purpose I/O Line 7
MSC1 Serial Data Input
38
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B16
P5.8
I/O
CC62INA
I
F/
PU
CC62INB
I
CCU63
SON0
O1
MSC0 Differential Driver Serial Data Output
Negative
OUT80
O2
OUT80 Line of GPTA0
CC62
O3
CCU62
P5.9
I/O
SOP0A
O1
OUT81
O2
OUT81 Line of GPTA0
COUT60
O3
CCU62
P5.10
I/O
FCLN0
O1
OUT82
O2
OUT82 Line of GPTA0
COUT61
O3
CCU62
P5.11
I/O
FCLP0A
O1
OUT83
O2
OUT83 Line of GPTA0
COUT62
O3
CCU62
P5.12
I/O
SON1
O1
OUT84
O2
OUT84 Line of GPTA0
OUT84
O3
OUT84 Line of GPTA1
B17
A16
A17
D14
Data Sheet
F/
PU
F/
PU
F/
PU
F/
PU
Port 5 General Purpose I/O Line 8
CCU62
Port 5 General Purpose I/O Line 9
MSC0 Differential Driver Serial Data Output
Positive A
Port 5 General Purpose I/O Line 10
MSC0 Differential Driver Clock Output
Negative
Port 5 General Purpose I/O Line 11
MSC0 Differential Driver Clock Output
Positive A
Port 5 General Purpose I/O Line 12
MSC1 Differential Driver Serial Data Output
Negative
39
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B14
P5.13
I/O
SOP1A
O1
F/
PU
OUT85
O2
OUT85 Line of GPTA0
OUT85
O3
OUT85 Line of GPTA1
P5.14
I/O
FCLN1
O1
OUT86
O2
OUT86 Line of GPTA0
OUT86
O3
OUT86 Line of GPTA1
P5.15
I/O
FCLNP1A
O1
OUT87
O2
OUT87 Line of GPTA0
OUT87
O3
OUT87 Line of GPTA1
P6.4
I/O
MTSR1
I
MRSTG1
I
SSC Guardian 1 Master Receive Input
(Master Mode)
MTSR1
O1
SSC1 Master Transmit Output (Master
Mode)3)
Reserved
O2
-
Reserved
O3
-
B13
A13
F/
PU
F/
PU
Port 5 General Purpose I/O Line 13
MSC1 Differential Driver Serial Data Output
Positive A
Port 5 General Purpose I/O Line 14
MSC1 Differential Driver Clock Output
Negative
Port 5 General Purpose I/O Line 15
MSC1 Differential Driver Clock Output
Positive A
Port 6
B4
Data Sheet
A1+/
PU
Port 6 General Purpose I/O Line 4
SSC1 Slave Receive Input (Slave Mode)
40
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A3
P6.5
I/O
MRST1
I
A1+/
PU
MRST1
O1
SSC1 Slave Transmit Output (Slave Mode)
Reserved
O2
-
Reserved
O3
-
P6.6
I/O
SCLK1
I
SCLK1
O1
SSC1 Clock Input/Output
Reserved
O2
-
Reserved
O3
-
P6.7
I/O
SLSI1
I
T6OFL
O1
GPT120
Reserved
O2
-
Reserved
O3
-
P6.8
I/O
RXDCAN0
I
RXD0B
I
ASC0 Receiver Input/Output B
CAPINB
I
GPT120
CAPINA
I
GPT121
Reserved
O1
-
RXD0B
O2
ASC0 Receiver Input/Output B
Reserved
O3
-
A4
D5
B5
Data Sheet
A1+/
PU
A1+/
PU
A2/
PU
Port 6 General Purpose I/O Line 5
SSC1 Master Receive Input (Master Mode)
Port 6 General Purpose I/O Line 6
SSC1 Clock Input/Output
Port 6 General Purpose I/O Line 7
SSC1 slave Select Input
Port 6 General Purpose I/O Line 8
CAN Node 0 Receiver Input 0
CAN Node 3 Receiver Input 1
41
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A5
P6.9
I/O
TXDCAN0
O1
A2/
PU
TXD0
O2
ASC0 Transmitter Output B
T60FL
O3
GPT120
P6.10
I/O
RXDCAN1
I
RXD1B
I
ASC1 Receiver Input/Output B
Reserved
O1
-
RXD1B
O2
ASC1 Receiver Input/Output B
TXENA
O3
E-Ray Channel A transmit Data Output
enable 2)
P6.11
I/O
TXDCAN1
O1
TXD1
O2
ASC1 Transmitter Output B
TXENB
O3
E-Ray Channel B transmit Data Output
enable 2)
P6.12
I/O
RXDCAN2
I
RXDA1
I
E-Ray Channel A Receive Data Input 1 2)
Reserved
O1
-
Reserved
O2
-
COUT61
O3
CCU60
C2
D2
B1
Data Sheet
A2/
PU
A2/
PU
A1/
PU
Port 6 General Purpose I/O Line 9
CAN Node 0 Transmitter Output
Port 6 General Purpose I/O Line 10
CAN Node 1 Receiver Input 0
CAN Node 0 Receiver Input 1
Port 6 General Purpose I/O Line 11
CAN Node 1 Transmitter Output
Port 6 General Purpose I/O Line 12
CAN Node 2 Receiver Input 0
CAN Node 1 Receiver Input 1
42
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C1
P6.13
I/O
TXDCAN2
O1
A2/
PU
TXDA
O2
E-Ray Channel A transmit Data Output 2)
COUT62
O3
CCU60
P6.14
I/O
RXDCAN3
I
RXDB1
I
E-Ray Channel B Receive Data Input 1 2)
Reserved
O1
-
Reserved
O2
-
COUT63
O3
CCU60
P6.15
I/O
CC60INB
I
CC60INA
I
CCU61
TXDCAN3
O1
CAN Node 3 Transmitter Output
TXDB
O2
E-Ray Channel B transmit Data Output 2)
CC60
O3
CCU61
P7.0
I/O
MRST3
I
REQ4
I
External trigger Input 4
AD2EMUX2
O1
ADC2 external multiplexer Control Output 2
MRST3
O2
SSC3 Slave Transmit Output (Master Mode)
Reserved
O3
-
D1
E1
A1/
PU
A2/
PU
Port 6 General Purpose I/O Line 13
CAN Node 2 Transmitter Output
Port 6 General Purpose I/O Line 14
CAN Node 3 Receiver Input 0
CAN Node 2 Receiver Input 1
Port 6 General Purpose I/O Line 15
CCU60
Port 7
H5
Data Sheet
A1+/
PU
Port 7 General Purpose I/O Line 0
SSC3 Master Receive Input (Slave Mode)
43
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
J1
P7.1
I/O
REQ5
I
A1+/
PU
MTSR3
I
SSC3 Slave Receive Input (Slave Mode)
MRSTG3B
I
SSC Guardian 3 Master Receive Input B
(Master Mode)
AD0EMUX2
O1
ADC0 external multiplexer Control Output 2
MTSR3
O2
SSC3 Master Transmit Output (Master
Mode)3)
Reserved
O3
-
P7.2
I/O
SCLK3
I
AD0EMUX0
O1
ADC0 external multiplexer Control Output 0
SCLK3
O2
SSC3 Output
Reserved
O3
-
P7.3
I/O
AD0EMUX1
O1
SLSO30
O2
SSC3 Output
Reserved
O3
-
P7.4
I/O
REQ6
I
AD2EMUX0
O1
ADC2 external multiplexer Control Output 0
SLSO31
O2
SSC3 Output
Reserved
O3
-
J2
J4
J5
Data Sheet
A1+/
PU
A1+/
PU
A1+/
PU
Port 7 General Purpose I/O Line 1
External trigger Input 5
Port 7 General Purpose I/O Line 2
SSC3 Input
Port 7 General Purpose I/O Line 3
ADC0 external multiplexer Control Output 1
Port 7 General Purpose I/O Line 4
External trigger Input 6
44
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
K4
P7.5
I/O
REQ7
I
A1+/
PU
AD2EMUX1
O1
ADC2 external multiplexer Control Output 1
SLSO32
O2
SSC3 Output
Reserved
O3
-
P8.0
I/O
IN40
I
IN40
I
IN40 Line of GPTA1
SENT0
I
SENT Digital Input
OUT40
O1
OUT40 Line of GPTA0
COUT62
O2
CCU61
TCLK1
O3
MLI1 transmit Channel Clock Output
P8.1
I/O
IN41
I
IN41
I
IN41 Line of GPTA1
TREADY1A
I
MLI1 transmit Channel ready Input A
SENT1
I
SENT Digital Input
CC61INA
I
CCU60
CC61INB
I
CCU61
OUT41
O1
OUT41 Line of GPTA0
CC61
O2
CCU60
SENT1
O3
SENT Digital Output
Port 7 General Purpose I/O Line 5
External trigger Input 7
Port 8
F1
E6
Data Sheet
A2/
PU
A1/
PU
Port 8 General Purpose I/O Line 0
IN40 Line of GPTA0
Port 8 General Purpose I/O Line 1
IN41 Line of GPTA0
45
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
E4
P8.2
I/O
IN42
I
A2/
PU
IN42
I
IN42 Line of GPTA1
SENT2
I
SENT Digital Input
CAPINA
I
GPT120
CAPINB
I
GPT121
COUT63
O1
CCU61
OUT42
O2
OUT42 Line of GPTA1
TVALID1A
O3
MLI1 transmit Channel valid Output A
P8.3
I/O
IN43
I
IN43
I
IN43 Line of GPTA1
SENT3
I
SENT Digital Input
CC62INA
I
CCU60
CC62INB
I
CCU61
OUT43
O1
OUT43 Line of GPTA0
CC62
O2
CCU60
TDATA1
O3
MLI1 transmit Channel Data Output A
E2
Data Sheet
A2/
PU
Port 8 General Purpose I/O Line 2
IN42 Line of GPTA0
Port 8 General Purpose I/O Line 3
IN43 Line of GPTA0
46
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
F2
P8.4
I/O
IN44
I
A1/
PU
IN44
I
IN44 Line of GPTA1
RCLK1A
I
MLI1 Receive Channel Clock Input A
SENT4
I
SENT Digital Input
CC62INB
I
CCU60
CC62INA
I
CCU61
OUT44
O1
OUT44 Line of GPTA0
CC62
O2
CCU61
T3OUT
O3
GPT121
P8.5
I/O
IN45
I
IN45
I
IN45 Line of GPTA1
SENT5
I
SENT Digital Input
CTRAPA
I
CCU60
CTRAPB
I
CCU62
CC60INC
I
CCU60
T12HRE
I
CCU61
CC61INC
I
CCU61
OUT45
O1
OUT45 Line of GPTA0
OUT45
O2
OUT45 Line of GPTA1
RREADY1A
O3
MLI1 Receive Channel ready Output A
F5
Data Sheet
A2/
PU
Port 8 General Purpose I/O Line 4
IN44 Line of GPTA0
Port 8 General Purpose I/O Line 5
IN45 Line of GPTA0
47
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
G4
P8.6
I/O
IN46
I
A1/
PU
IN46
I
IN46 Line of GPTA1
RVALID1A
I
MLI1 Receive Channel valid Input A
SENT6
I
SENT Digital Input
OUT46
O1
OUT46 Line of GPTA0
COUT60
O2
CCU61
T6OUT
O3
GPT120
P8.7
I/O
IN47
I
IN47
I
IN47 Line of GPTA1
RDATA1A
I
MLI1 Receive Channel Data Input A
SENT7
I
SENT Digital Input
OUT47
O1
OUT47 Line of GPTA0
COUT61
O2
CCU61
T6OUT
O3
GPT121
P9.0
I/O
IN48
I
IN48
I
IN48 Line of GPTA1
COUT63
O1
CCU62
OUT48
O2
OUT48 Line of GPTA1
EN12
O3
MSC1 Device Select Output 2
F4
A1/
PU
Port 8 General Purpose I/O Line 6
IN46 Line of GPTA0
Port 8 General Purpose I/O Line 7
IN47 Line of GPTA0
Port 9
E17
Data Sheet
A2/
PU
Port 9 General Purpose I/O Line 0
IN48 Line of GPTA0
48
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D19
P9.1
I/O
IN49
I
A2/
PU
IN49
I
IN49 Line of GPTA1
CC60INB
I
CCU62
CC60INA
I
CCU63
CC60
O1
CCU63
OUT49
O2
OUT49 Line of GPTA1
EN11
O3
MSC1 Device Select Output 1
P9.2
I/O
IN50
I
IN50
I
IN50 Line of GPTA1
CC61INB
I
CCU62
CC61INA
I
CCU63
CC61
O1
CCU63
OUT50
O2
OUT50 Line of GPTA1
SOP1B
O3
MSC1 serial Data Output
P9.3
I/O
IN51
I
IN51
I
IN51 Line of GPTA1
CC62INB
I
CCU62
CC62INA
I
CCU63
CC62
O1
CCU63
OUT51
O2
OUT51 Line of GPTA1
FCLP1B
O3
MSC1 Clock Output
D20
C20
Data Sheet
A2/
PU
A2/
PU
Port 9 General Purpose I/O Line 1
IN49 Line of GPTA0
Port 9 General Purpose I/O Line 2
IN50 Line of GPTA0
Port 9 General Purpose I/O Line 3
IN51 Line of GPTA0
49
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C19
P9.4
I/O
IN52
I
A2/
PU
IN52
I
IN52 Line of GPTA1
COUT60
O1
CCU63
OUT52
O2
OUT52 Line of GPTA1
EN03
O3
MSC0 Device Select Output 3
P9.5
I/O
IN53
I
IN53
I
IN53 Line of GPTA1
SENT1
I
SENT Digital Input
COUT61
O1
CCU63
OUT53
O2
OUT53 Line of GPTA1
EN02
O3
MSC0 Device Select Output 2
P9.6
I/O
IN54
I
IN54
I
IN54 Line of GPTA1
SENT3
I
SENT Digital Input
OUT54
O1
OUT54 Line of GPTA0
SENT3
O2
SENT Digital Output
EN01
O3
MSC0 Device Select Output 1
F17
F16
Data Sheet
A2/
PU
A2/
PU
Port 9 General Purpose I/O Line 4
IN52 Line of GPTA0
Port 9 General Purpose I/O Line 5
IN53 Line of GPTA0
Port 9 General Purpose I/O Line 6
IN54 Line of GPTA0
50
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
E20
P9.7
I/O
IN55
I
A2/
PU
IN55
I
IN55 Line of GPTA1
SENT4
I
SENT Digital Input
OUT55
O1
OUT55 Line of GPTA0
SENT4
O2
SENT Digital Output
SOP0B
O3
MSC0 serial Data Output
P9.8
I/O
SENT6
I
COUT62
O1
CCU63
SENT6
O2
SENT Digital Output
FCLP0B
O3
MSC0 Clock Output
P9.10
I/O
EMGSTOP
I
SENT7
I
SENT Digital Input
COUT63
O1
CCU63
SENT7
O2
SENT Digital Output
Reserved
O3
-
P9.13
I/O
BRKIN
I
ECTT1
I
TTCAN Input
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
BRKOUT
O
OCDS Break Output
E19
F20
G16
Data Sheet
A2/
PU
A1/
PU
A2/
PU
Port 9 General Purpose I/O Line 7
IN55 Line of GPTA0
Port 9 General Purpose I/O Line 8
SENT Digital Input
Port 9 General Purpose I/O Line 10
Emergency Stop
Port 9 General Purpose I/O Line 13
OCDS Break Input
51
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
H16
P9.14
I/O
BRKIN
I
A2/
PU
ECTT2
I
TTCAN Input
REQ15
I
External trigger Input 15
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
BRKOUT
O
OCDS Break Output
P10.0
I/O
MRST0
I
MRST0
O1
SSC0 Slave Transmit Output (Slave Mode)
Reserved
O2
-
Reserved
O3
-
P10.1
I/O
MTSR0
I
MRSTG0
I
SSC Guardian 0 Master Receive Input
(Master Mode)
MTSR0
O1
SSC0 Master Transmit Output (Master
Mode)
Reserved
O2
-
Reserved
O3
-
Port 9 General Purpose I/O Line 14
OCDS Break Input
Port 10
Y15
W15
Data Sheet
A2/
PU
A2/
PU
Port 10 General Purpose I/O Line 0
SSC0 Master Receive Input (Master Mode)
Port 10 General Purpose I/O Line 1
SSC0 Slave Receive Input (Slave Mode)
52
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
U16
P10.2
I/O
SLSI0
I
A1/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P10.3
I/O
SCLK0
I
SCLK0
O1
SSC0 Clock Input/Output
Reserved
O2
-
Reserved
O3
-
P10.4
I/O
SLSO0
O1
Reserved
O2
-
Reserved
O3
-
P10.5
I/O
SLSO1
O1
Reserved
O2
-
Reserved
O3
-
P13.0
I/O
OUT88
O1
OUT88
O2
OUT88 Line of GPTA1
OUT80
O3
OUT80 Line of LTCA2
Y14
W16
Y16
A2/
PU
A1+/
PU
A1+/
PU
Port 10 General Purpose I/O Line 2
SSC0 Slave Select Input
Port 10 General Purpose I/O Line 3
SSC0 Clock Input/Output
Port 10 General Purpose I/O Line 4
SSC0 Slave Select Output Line 0
Port 10 General Purpose I/O Line 5
SSC0 Slave Select Output Line 1
Port 13
M16
Data Sheet
A2/
PU
Port 13 General Purpose I/O Line 0
OUT88 Line of GPTA0
53
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
M17
P13.1
I/O
OUT89
O1
A2/
PU
OUT89
O2
OUT89 Line of GPTA1
OUT81
O3
OUT81 Line of LTCA2
P13.2
I/O
OUT90
O1
OUT90
O2
OUT90 Line of GPTA1
OUT82
O3
OUT82 Line of LTCA2
P13.3
I/O
OUT91
O1
OUT91
O2
OUT91 Line of GPTA1
OUT83
O3
OUT83 Line of LTCA2
P13.4
I/O
OUT92
O1
OUT92
O2
OUT92 Line of GPTA1
OUT84
O3
OUT84 Line of LTCA2
P13.5
I/O
OUT93
O1
OUT93
O2
OUT93 Line of GPTA1
OUT85
O3
OUT85 Line of LTCA2
P13.6
I/O
OUT94
O1
OUT94
O2
OUT94 Line of GPTA1
OUT86
O3
OUT86 Line of LTCA2
N16
N17
N19
N20
P16
Data Sheet
A2/
PU
A2/
PU
A2/
PU
A2/
PU
A2/
PU
Port 13 General Purpose I/O Line 1
OUT89 Line of GPTA0
Port 13 General Purpose I/O Line 2
OUT90 Line of GPTA0
Port 13 General Purpose I/O Line 3
OUT91 Line of GPTA0
Port 13 General Purpose I/O Line 4
OUT92 Line of GPTA0
Port 13 General Purpose I/O Line 5
OUT93 Line of GPTA0
Port 13 General Purpose I/O Line 6
OUT94 Line of GPTA0
54
V 1.1, 2014-05
TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
P17
P13.7
I/O
OUT95
O1
A2/
PU
OUT95
O2
OUT95 Line of GPTA1
OUT87
O3
OUT87 Line of LTCA2
P13.8
I/O
OUT96
O1
OUT96
O2
OUT96 Line of GPTA1
OUT88
O3
OUT88 Line of LTCA2
P13.9
I/O
OUT97
O1
OUT97
O2
OUT97 Line of GPTA1
OUT89
O3
OUT89 Line of LTCA2
P13.10
I/O
OUT98
O1
OUT98
O2
OUT98 Line of GPTA1
OUT90
O3
OUT90 Line of LTCA2
P13.11
I/O
OUT99
O1
OUT99
O2
OUT99 Line of GPTA1
OUT91
O3
OUT91 Line of LTCA2
P13.12
I/O
OUT100
O1
OUT100
O2
OUT100 Line of GPTA1
OUT92
O3
OUT92 Line of LTCA2
P19
P20
R17
R19
R20
Data Sheet
A2/
PU
A2/
PU
A2/
PU
A2/
PU
A2/
PU
Port 13 General Purpose I/O Line 7
OUT95 Line of GPTA0
Port 13 General Purpose I/O Line 8
OUT96 Line of GPTA0
Port 13 General Purpose I/O Line 9
OUT97 Line of GPTA0
Port 13 General Purpose I/O Line 10
OUT98 Line of GPTA0
Port 13 General Purpose I/O Line 11
OUT99 Line of GPTA0
Port 13 General Purpose I/O Line 12
OUT100 Line of GPTA0
55
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
T19
P13.13
I/O
OUT101
O1
A2/
PU
OUT101
O2
OUT101 Line of GPTA1
OUT93
O3
OUT93 Line of LTCA2
P13.14
I/O
OUT102
O1
OUT102
O2
OUT102 Line of GPTA1
OUT94
O3
OUT94 Line of LTCA2
P13.15
I/O
OUT103
O1
OUT103
O2
OUT103 Line of GPTA1
OUT95
O3
OUT95 Line of LTCA2
P14.0
I/O
CC60
O1
OUT96
O2
OUT96 Line of GPTA1
OUT96
O3
OUT96 Line of LTCA2
P14.2
I/O
CC62
O1
OUT98
O2
OUT98 Line of GPTA1
OUT98
O3
OUT98 Line of LTCA2
P14.4
I/O
COUT61
O1
OUT100
O2
OUT100 Line of GPTA1
OUT100
O3
OUT100 Line of LTCA2
T20
U19
A2/
PU
A2/
PU
Port 13 General Purpose I/O Line 13
OUT101 Line of GPTA0
Port 13 General Purpose I/O Line 14
OUT102 Line of GPTA0
Port 13 General Purpose I/O Line 15
OUT103 Line of GPTA0
Port 14
U20
V20
W18
Data Sheet
A2/
PU
A2/
PU
A2/
PU
Port 14 General Purpose I/O Line 0
CCU60
Port 14 General Purpose I/O Line 2
CCU60
Port 14 General Purpose I/O Line 4
CCU60
56
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
Y19
P14.6
I/O
COUT63
O1
A2/
PU
OUT102
O2
OUT102 Line of GPTA1
OUT102
O3
OUT102 Line of LTCA2
P14.8
I/O
CC61
O1
T3OUT
O2
GPT120
OUT104
O3
OUT104 Line of LTCA2
P17.0
I
SENT0
I
SENT Digital Input 0
AN8
I
Analog Input : ADC0.CH8 5)
P17.1
I
SENT1
I
SENT Digital Input 1
AN9
I
Analog Input : ADC0.CH9 5)
P17.2
I
SENT2
I
SENT Digital Input 2
AN10
I
Analog Input : ADC0.CH10 5)
P17.3
I
SENT3
I
SENT Digital Input 3
AN11
I
Analog Input : ADC0.CH11 5)
P17.4
I
SENT4
I
SENT Digital Input 4
AN12
I
Analog Input : ADC0.CH12 5)
Y18
A2/
PU
Port 14 General Purpose I/O Line 6
CCU60
Port 14 General Purpose I/O Line 8
CCU61
Port 17
R5
R4
P5
P4
P2
Data Sheet
D/S
D/S
D/S
D/S
D/S
Port 17 General Purpose I Line 04)
Port 17 General Purpose I Line 14)
Port 17 General Purpose I Line 24)
Port 17 General Purpose I Line 34)
Port 17 General Purpose I Line 44)
57
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
P1
P17.5
I
D/S
SENT5
I
SENT Digital Input 5
AN13
I
Analog Input : ADC0.CH13 5)
P17.6
I
SENT6
I
SENT Digital Input 6
AN14
I
Analog Input : ADC0.CH14 5)
P17.7
I
SENT7
I
SENT Digital Input 7
AN15
I
Analog Input : ADC0.CH15 5)
P17.8
I
SENT0
I
SENT Digital Input 0
AN36
I
Analog Input : ADC2.CH4 5)
P17.9
I
SENT1
I
SENT Digital Input 1
AN37
I
Analog Input : ADC2.CH5 5)
P17.10
I
SENT2
I
SENT Digital Input 2
AN38
I
Analog Input : ADC2.CH6 5)
P17.11
I
SENT3
I
SENT Digital Input 3
AN39
I
Analog Input : ADC2.CH7 5)
P17.12
I
SENT4
I
SENT Digital Input 4
AN40
I
Analog Input : ADC2.CH8 5)
N2
N1
W4
Y4
W5
Y5
T6
Data Sheet
D/S
D/S
D/S
D/S
D/S
D/S
D/S
Port 17 General Purpose I Line 54)
Port 17 General Purpose I Line 64)
Port 17 General Purpose I Line 74)
Port 17 General Purpose I Line 84)
Port 17 General Purpose I Line 94)
Port 17 General Purpose I Line 104)
Port 17 General Purpose I Line 114)
Port 17 General Purpose I Line 124)
58
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
U6
P17.13
I
D/S
SENT5
I
SENT Digital Input 5
AN41
I
Analog Input : ADC2.CH9 5)
P17.14
I
SENT6
I
SENT Digital Input 6
AN42
I
Analog Input : ADC2.CH10 5)
P17.15
I
SENT7
I
SENT Digital Input 7
AN43
I
Analog Input : ADC2.CH11 5)
T7
U7
D/S
D/S
Port 17 General Purpose I Line 134)
Port 17 General Purpose I Line 144)
Port 17 General Purpose I Line 154)
Analog Input Port
T4
AN0
I
D
Analog Input 0: ADC0.CH0 5)
Y2
AN1
I
D
Analog Input 1: ADC0.CH1 5)
W2
AN2
I
D
Analog Input 2: ADC0.CH2 5)
W1
AN3
I
D
Analog Input 3: ADC0.CH3 5)
V2
AN4
I
D
Analog Input 4: ADC0.CH4 5)
U2
AN5
I
D
Analog Input 5: ADC0.CH5 5)
T2
AN6
I
D
Analog Input 6: ADC0.CH6 5)
T5
AN7
I
D
Analog Input 7: ADC0.CH7 5)
R5
AN8
I
D/S
Analog Input 8: ADC0.CH8, SENT0 5)
R4
AN9
I
D/S
Analog Input 9: ADC0.CH9, SENT1 5)
P5
AN10
I
D/S
Analog Input 10: ADC0.CH10, SENT2 5)
P4
AN11
I
D/S
Analog Input 11: ADC0.CH11, SENT3 5)
P2
AN12
I
D/S
Analog Input 12: ADC0.CH12, SENT4 5)
P1
AN13
I
D/S
Analog Input 13: ADC0.CH13, SENT5 5)
N2
AN14
I
D/S
Analog Input 14: ADC0.CH14, SENT6 5)
N1
AN15
I
D/S
Analog Input 15: ADC0.CH15, SENT7 5)
Data Sheet
59
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
N5
AN16
I
D
Analog Input 16: ADC1.CH0 5)
N4
AN17
I
D
Analog Input 17: ADC1.CH1 5)
M5
AN18
I
D
Analog Input 18: ADC1.CH2 5)
M4
AN19
I
D
Analog Input 19: ADC1.CH3 5)
M2
AN20
I
D
Analog Input 20: ADC1.CH4 5)
M1
AN21
I
D
Analog Input 21: ADC1.CH5 5)
L2
AN22
I
D
Analog Input 22: ADC1.CH6 5)
L1
AN23
I
D
Analog Input 23: ADC1.CH7 5)
U8
AN24
I
D
Analog Input 24: ADC1.CH8,
FADC_FADIN0P 6)
W8
AN25
I
D
Analog Input 25: ADC1.CH9,
FADC_FADIN0N 6)
Y8
AN26
I
D
Analog Input 26: ADC1.CH10,
FADC_FADIN1P 6)
T9
AN27
I
D
Analog Input 27: ADC1.CH11,
FADC_FADIN1N 6)
U9
AN28
I
D
Analog Input 28: ADC1.CH12,
FADC_FADIN2P 6)
W9
AN29
I
D
Analog Input 29: ADC1.CH13,
FADC_FADIN2N 6)
Y9
AN30
I
D
Analog Input 30: ADC1.CH14,
FADC_FADIN3P 6)
T10
AN31
I
D
Analog Input 31: ADC1.CH15,
FADC_FADIN3N 6)
U4
AN32
I
D
Analog Input 32: ADC2.CH0 5)
W3
AN33
I
D
Analog Input 33: ADC2.CH1 5)
Y3
AN34
I
D
Analog Input 34: ADC2.CH2 5)
T8
AN35
I
D
Analog Input 35: ADC2.CH3 5)
Data Sheet
60
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
W4
AN36
I
D
Analog Input 36: ADC2.CH4, SENT0 5)
Y4
AN37
I
D
Analog Input 37: ADC2.CH5, SENT1 5)
W5
AN38
I
D
Analog Input 38: ADC2.CH6, SENT2 5)
Y5
AN39
I
D
Analog Input 39: ADC2.CH7, SENT3 5)
T6
AN40
I
D
Analog Input 40: ADC2.CH8, SENT4 5)
U6
AN41
I
D
Analog Input 41: ADC2.CH9, SENT5 5)
T7
AN42
I
D
Analog Input 42: ADC2.CH10, SENT6 5)
U7
AN43
I
D
Analog Input 43: ADC2.CH11, SENT7 5)
V1
AN44
I
D
Analog Input 44: ADC2.CH12 5)
U1
AN45
I
D
Analog Input 45: ADC2.CH13 5)
T1
AN46
I
D
Analog Input 46: ADC2.CH14 5)
U5
AN47
I
D
Analog Input 47: ADC2.CH15 5)
System I/O
F19
PORST
I
PD
Power-on Reset Input
G19
ESR0
I/O
A2
External System Request Reset Input 0
Default configuration during and after reset is
open-drain driver. The driver drives low during
power-on reset.
G20
ESR1
I/O
A2/
PD
External System Request Reset Input 1
H20
TCK
I
PD
JTAG Module Clock Input
DAP0
I
TDI
I
BRKIN
I
BRKOUT
O
TESTMODE
I
J17
G17
Data Sheet
Device Access Port Line 0
A2/
PU
JTAG Module Serial Data Input
OCDS Break Input (Alternate Output)
OCDS Break Output (Alternate Input)
PU
Test Mode Select Input
61
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
J16
TMS
I
JTAG Module State Machine Control Input
DAP1
I/O
A2/
PD
H19
TRST
I
PD
JTAG Module Reset/Enable Input
K20
XTAL1
I
Main Oscillator/PLL/Clock Generator Input
K19
XTAL2
O
Main Oscillator/PLL/Clock Generator Output
H17
TDO
O
BRKIN
I
BRKOUT
O
OCDS Break Output (Alternate Output)
DAP2
O
Device Access Port Line 2
A2/
PU
Device Access Port Line 1
JTAG Module Serial Data Output
OCDS Break Input (Alternate Input)
Power Supply
R2
VDDM
-
-
ADC Analog Part Power Supply (3.3V - 5V)
R1
VSSM
-
-
ADC Analog Part Ground
Y6
VAREF0
-
-
ADC0 Reference Voltage
W6
VAREF1
-
-
ADC1 Reference Voltage
W7
VAREF2
-
-
ADC2 Reference Voltage
Y7
VAGND0
-
-
ADC0 Reference Ground
VAGND1
-
-
ADC1 Reference Ground
VAGND2
-
-
ADC2 Reference Ground
U10
VFAREF
-
-
FADC Reference Voltage
W10
VFAGND
-
-
FADC Reference Ground
U11
VDDMF
-
-
FADC Analog Part Power Supply (3.3V)
T11
VDDAF
-
-
FADC Analog Part Logic Power Supply
(1.3V)
Y10
VSSMF
-
-
FADC Analog Part Ground
VSSAF
-
-
FADC Analog Part Logic Ground
Data Sheet
62
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
K5,
L16
VDDFL3
-
-
Flash Power Supply (3.3V)
J20
VSSOSC
-
-
Oscillator Ground (Main & E-Ray)
VSSOSC3
-
-
Oscillator Ground (Main & E-Ray)
J19
VDDOSC
-
-
Main Oscillator Power Supply (1.3V)
K16
VDDOSC3
-
-
Main Oscillator Power Supply (3.3V)
K17
VDDPF
-
-
E-Ray PLL Power Supply (1.3V)
L17
VDDPF3
-
-
E-Ray PLL Power Supply (3.3V)
G8,
G13,
H7,
H14,
N7,
N14,
P8,
P13,
R16,
T17,
V19,
W20
VDD
-
-
Digital Core Power Supply (1.3V)
A2,
A19,
B3,
B10,
B18,
K2,
M19,
M20,
W11,
W17
VDDP
-
-
Port Power Supply (3.3V)
L4, L5
VDDSB
-
-
Emulation Stand-by SRAM Power Supply
(1.3V) (Emulation device only)
Note: This pin is N.C. in a productive device.
Data Sheet
63
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
P9,
P10,
P11,
P12,
N9,
N10,
N11,
N12
VSS
-
-
Digital Ground (center balls)
M7,
M8,
M10,
M11,
M13,
M14,
J7, J8,
J10,
J11,
J13,
J14
VSS
-
-
Digital Ground (center balls cont’d)
L7, L8, VSS
L9,
L10,
L11,
L12,
L13,
L14
-
-
Digital Ground (center balls cont’d)
K7,
K8,
K9,
K10,
K11,
K12,
K13,
K14
-
-
Digital Ground (center balls cont’d)
VSS
Data Sheet
64
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TC1791
PinningTC1791 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
G9,
G10,
G11,
G12,
H9,
H10,
H11,
H12
VSS
-
-
Digital Ground (center balls cont’d)
T16,
U17,
W19
VSS
-
-
Digital Ground (outer balls)
L19,
L20,
Y17,
Y20
VSS
-
-
Digital Ground (outer balls)
A10,
A20,
B2,
B19,
D4,
D17,
E5,
E16,
K1,
Y11
VSS
-
-
Digital Ground (outer balls)
-
-
Not connected. These pins are reserved for
future extension and shall not be connected
externally.
A1, Y1 N.C.
1) Only applicable in TC1791ED. Reserved in TC1791PD.
2) Only available for SAK-TC1791S-512F240EP, SAK-TC1791F-512F240EP, SAK-TC1791F-512F240EL, SAKTC1791S-384F200EP, SAK-TC1791F-384F200EP, and SAK-TC1791F-384F200EL.
3) The MTSR output of SSCx is overlayed with the MRSTG input of the related SSCGx
4) Analog Input overlayed with a SENT Digitial Input. The related port logic is used configure the input as either
analog input (default after reset) or digital input. The related port logic supports only the port input features as
the connected pads are input pads only.
5) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table.
6) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table.
Data Sheet
65
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TC1791
PinningTC1791 Pin Configuration
Legend for Table 2
Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X00B
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)
Column “Type”:
A1 = Pad class A1 (LVTTL)
A1+ = Pad class A1+ (LVTTL)
A2 = Pad class A2 (LVTTL)
F = Pad class F (LVDS/CMOS)
D = Pad class D (ADC)
S = Pad class S(SENT)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
Data Sheet
66
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TC1791
Identification Registers
4
Identification Registers
The Identification Registers uniquely identify the whole device.
Table 3
SAK-TC1791F-512F240EL Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
0700 9502H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 4
SAK-TC1791F-512F240EP Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
8700 9502H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 5
SAK-TC1791F-512F200EL Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
1700 9502H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 6
SAK-TC1791F-512F200EP Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
9700 9502H
F000 0640H
AB
Data Sheet
67
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TC1791
Identification Registers
Table 6
SAK-TC1791F-512F200EP Identification Registers (cont’d)
Short Name
Value
Address
Stepping
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 7
SAK-TC1791F-384F200EL Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
1600 9502H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 8
SAK-TC1791F-384F200EP Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
9600 9502H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 9
SAK-TC1791S-512F240EP Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
8700 AA02H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Data Sheet
68
V 1.1, 2014-05
TC1791
Identification Registers
Table 10
SAK-TC1791S-384F200EP Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
9600 AA02H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 11
SAK-TC1791N-384F200EP Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
9600 B502H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Data Sheet
69
V 1.1, 2014-05
TC1791
Electrical ParametersGeneral Parameters
5
Electrical Parameters
This specification provides all electrical parameters of the TC1791.
5.1
General Parameters
5.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC1791
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
•
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1791 and must be regarded for a system design.
SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1791 designed in.
Data Sheet
70
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TC1791
Electrical ParametersGeneral Parameters
5.1.2
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.
Table 12
Pad Driver and Pad Classes Overview
Class Power Type
Supply
Sub Class
Speed Load
Grade 1)
Leakage
150oC 1)
Termination
1)
A
F
3.3 V
3.3 V
LVTTL
I/O,
LVTTL
outputs
A1
(e.g. GPIO)
6 MHz
100 pF 500 nA
A1+
(e.g. serial
I/Os)
25
MHz
50 pF
1 μA
Series
termination
recommended
A2
(e.g. serial
I/Os)
40
MHz
50 pF
3 μA
Series
termination
recommended
LVDS
–
50
MHz
–
–
Parallel
termination,
100 Ω ± 10% 2)
CMOS
–
6 MHz
50 pF
–
DE
5V
ADC
–
–
–
–
I
3.3 V
LVTTL
(input
only)
–
–
–
–
No
1) These values show typical application configurations for the pad. Complete and detailed pad parameters are
available in the individual pad parameter table on the following pages.
2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω ± 10%.
Data Sheet
71
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TC1791
Electrical ParametersGeneral Parameters
5.1.3
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 13
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Min. Typ. Max.
Storage temperature
TST
Voltage at 1.3 V power supply VDD
pins with respect to VSS
Voltage at 3.3 V power supply VDDP
pins with respect to VSS
SR
Voltage at 5 V power supply VDDM
pins with respect to VSS
Voltage on any Class A input VIN
Unit Note /
Test Con
dition
SR -65
–
150
°C
–
SR –
–
2.0
V
–
–
–
4.33
V
–
SR –
–
7.0
V
–
SR -0.7 –
VDDP + 0.5 V
or max. 4.33
Whatever
is lower
-0.6 –
7.0
V
–
Voltage on any shared Class VAINF
-0.6 –
D analog input pin with
VFAREF
respect to VSSAF, if the FADC
SR
is switched through to the pin.
7.0
V
–
Input current on any pin
during overload condition
pin and dedicated input pins
with respect to VSS
Voltage on any Class D
analog input pin with respect
to VAGND
VAIN
VAREFx
SR
IIN
-10
–
+10
mA
Absolute maximum sum of all IIN
input circuit currents for one
port group during overload
condition1)
-25
–
+25
mA
Absolute maximum sum of all ΣIIN
input circuit currents during
overload condition
-200 –
200
mA
1) The port groups are defined in Table 18.
Data Sheet
72
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TC1791
Electrical ParametersGeneral Parameters
5.1.4
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 14 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
•
•
full operation life-time (24000 h) is not exceeded
Operating Conditions are met for
– pad supply levels (VDDP or VDDM)
– temperature
If a pin current is out of the Operating Conditions but within the overload parameters,
then the parameters functionality of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Table 14
Overload Parameters
Parameter
Min. Typ. Max.
Unit Note /
Test Con
dition
Input current on any digital pin IIN
during overload condition
except LVDS pins
-5
mA
Input current on LVDS pins
IINLVDS
IING
-3
–
+3
mA
-20
–
+20
mA
IINANA
IINSA
-3
–
+3
mA
-45
–
+45
mA
ΣIINS
-100 –
100
mA
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
Input current on analog pins
Absolute sum of all analog
input currents for analog
inputs during overload
condition
Absolute sum of all input
circuit currents during
overload condition
Symbol
Values
–
+5
1) The port groups are defined in Table 18.
Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.
Data Sheet
73
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TC1791
Electrical ParametersGeneral Parameters
Table 15
PN-Junction Characterisitics for positive Overload
Pad Type
IIN = 3 mA
IIN = 5 mA
A1 / A1+ / F
UIN = VDDP + 0.6 V
UIN = VDDP + 0.5 V
UIN = VDDP + 0.7 V
UIN = VDDM + 0.6 V
UIN = VDDM + 0.6 V
UIN = VDDP + 0.7 V
UIN = VDDP + 0.6 V
A2
LVDS
D
S
Table 16
-
PN-Junction Characterisitics for negative Overload
Pad Type
IIN = -3 mA
IIN = -5 mA
A1 / A1+ / F
UIN = VSS - 0.6 V
UIN = VSS - 0.5 V
UIN = VSS - 0.7 V
UIN = VSSM - 0.6 V
UIN = VSSM - 0.6 V
UIN = VSS - 0.7 V
UIN = VSS - 0.6 V
A2
LVDS
D
S
-
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery without having
any negative reliability impact on the operational life-time.
Data Sheet
74
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TC1791
Electrical ParametersGeneral Parameters
5.1.5
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the TC1791. All parameters specified in the following tables
refer to these operating conditions, unless otherwise noticed.
Digital supply voltages applied to the TC1791 must be static regulated voltages which
allow a typical voltage swing of ± 5 %.
All parameters specified in the following tables (Table 19 and following) refer to these
operating conditions (Table 17), unless otherwise noticed in the Note / Test Condition
column.
The Extended Range Operating Conditions did not increase area of validity of the
parameters defined in table 11 and later.
Table 17
Parameter
Operating Conditions Parameters
Symbol
Overload coupling factor KOVAN
for analog inputs, negative CC
Values
Unit
Min.
Typ.
Max.
−
−
0.0001
Note /
Test Condition
IOV≤ 0 mA;
IOV≥ -2 mA;
analog
pad= 5.0 V
Overload coupling factor KOVAP
for analog inputs, positive CC
−
−
0.0000
1
IOV≤ 3 mA;
IOV≥ 0 mA;
analog
pad= 5.0 V
Data Sheet
75
V 1.1, 2014-05
TC1791
Electrical ParametersGeneral Parameters
Table 17
Operating Conditions Parameters (cont’d)
Parameter
Symbol
Values
Min.
CPU Frequency
Data Sheet
Unit
Note /
Test Condition
Typ.
Max.
fCPU SR −
−
240
MHz SAK-TC1791F512F 240EL;
SAK-TC1791F512F 240EP;
SAK-TC1791S512F 240EP
−
−
200
MHz SAK-TC1791F512F 200EL
SAK-TC1791F512F 200EP;
SAK-TC1791F384F 200EL;
SAK-TC1791F384F 200EP;
SAK-TC1791S384F 200EP;
SAK-TC1791F384N 200EL;
SAK-TC1791F384N 200EP
76
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Electrical ParametersGeneral Parameters
Table 17
Operating Conditions Parameters (cont’d)
Parameter
Symbol
Values
Min.
Modulated fCPU
Modulated fFPI
−
240
MHz SAK-TC1791F512F 240EL;
SAK-TC1791F512F 240EP;
SAK-TC1791S512F 240EP
−
−
200
MHz SAK-TC1791F512F 200EL
SAK-TC1791F512F 200EP;
SAK-TC1791F384F 200EL;
SAK-TC1791F384F 200EP;
SAK-TC1791S384F 200EP;
SAK-TC1791F384N 200EL;
SAK-TC1791F384N 200EP
fFPI SR −
fFPI_modul −
−
100
MHz
−
100MHz MA = modulatio
2*MA1)
n amplitude
−
150
−
MHz MA = modulatio
150n amplitude
2*MA1)
fCPU_mod −
ated
FSI frequency
Modulated fFSI
PCP Frequency
SR
SR
fPCP SR −
fPCP_mod −
ulated
Data Sheet
SR
fFSI SR −
fFSI_modul −
ated
Modulated fPCP
Note /
Test Condition
Max.
ulated
FPI bus frequency
Unit
Typ.
SR
77
MHz
−
200
−
200MHz MA = modulatio
2*MA1)
n amplitude
MHz
V 1.1, 2014-05
TC1791
Electrical ParametersGeneral Parameters
Table 17
Operating Conditions Parameters (cont’d)
Parameter
SRI Frequency
Data Sheet
Symbol
fSRI SR
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
240
MHz SAK-TC1791F512F 240EL;
SAK-TC1791F512F 240EP;
SAK-TC1791S512F 240EP
−
−
200
MHz SAK-TC1791F512F 200EL
SAK-TC1791F512F 200EP;
SAK-TC1791F384F 200EL;
SAK-TC1791F384F 200EP;
SAK-TC1791S384F 200EP;
SAK-TC1791F384N 200EL;
SAK-TC1791F384N 200EP
78
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Electrical ParametersGeneral Parameters
Table 17
Operating Conditions Parameters (cont’d)
Parameter
Symbol
Values
Min.
Unit
Note /
Test Condition
Typ.
Max.
−
240
MHz SAK-TC1791F512F 240EL;
SAK-TC1791F512F 240EP;
SAK-TC1791S512F 240EP
−
−
200
MHz SAK-TC1791F512F 200EL
SAK-TC1791F512F 200EP;
SAK-TC1791F384F 200EL;
SAK-TC1791F384F 200EP;
SAK-TC1791S384F 200EP;
SAK-TC1791F384N 200EL;
SAK-TC1791F384N 200EP
Inactive device pin current IID SR
-1
−
1
mA
Short circuit current of
digital outputs2)
ISC SR
-5
−
5
mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
CC
−
−
100
mA
Absolute sum of short
circuit currents per pin
group
ΣISC_PG
CC
−
−
20
mA
Ambient Temperature
TA SR
-40
TJ SR
-40
VDD SR 1.17
−
125
°C
−
150
Modulated fSRI
fSRI_modul −
ated
Junction temperature
Core Supply Voltage
Data Sheet
SR
1.3
79
1.43
All power
supply voltages
VDDx = 0
°C
3)
V
for duration
limitation see
Section 5.1.5.1
V 1.1, 2014-05
TC1791
Electrical ParametersGeneral Parameters
Table 17
Operating Conditions Parameters (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
3.635)
V
for duration
limitation see
Section 5.1.5.1
5
5.54)
V
1.17
1.3
1.433)
V
for duration
limitation see
Section 5.1.5.1
VDDOSC3 2.97
3.3
3.635)
V
for duration
limitation see
Section 5.1.5.1
VDDP SR 2.97
3.3
3.63 5) V
for duration
limitation see
Section 5.1.5.1
Min.
Typ.
Max.
Flash supply voltage 3.3V VDDFL3
SR
2.97
3.3
ADC analog supply
voltage
VDDM
3.135
Oscillator core supply
voltage
VDDOSC
SR
Oscillator 3.3V supply
voltage
SR
Digital supply voltage for
IO pads
SR
E-Ray PLL core voltage
supply
VDDPF
1.17
1.3
1.433)
V
SR
for duration
limitation see
Section 5.1.5.1
E-Ray PLL 3.3V supply
VDDPF3
2.97
3.3
3.635)
V
for duration
limitation see
Section 5.1.5.1
VDDPPA
0.65
−
−
V
VSS SR 0
Analog ground voltage for VSSM SR -0.1
VDDM
Analog core supply
VDDAF
1.17
−
−
V
0
0.1
V
1.3
1.433)
V
SR
VDDP voltage to ensure
defined pad states6)
CC
Digital ground voltage
SR
VDDMF
2.97
3.3
3.635)
V
Analog ground voltage for VSSAF
SR
-0.1
0
0.1
V
FADC / ADC analog
supply voltage
SR
VDDMF
1) MA equals the modulation amplitude in percentage times the configured PLL clock out frequency.
2) Applicable for digital outputs.
3) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
Data Sheet
80
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TC1791
Electrical ParametersGeneral Parameters
4) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
5) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
6) This parameter is valid under the assumption the PORST signal is constantly at low level during the powerup/power-down of VDDP.
5.1.5.1
Extended Range Operating Conditions
The following extended operating conditions are defined:
•
•
•
1.3V + 5% < VDD / VDDOSC / VDDPF / VDDAF < 1.3V + 7.5% (overvoltage condition):
– limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
1.3V + 7.5% < VDD / VDDOSC / VDDPF / VDDAF < 1.3V + 10% (overvoltage condition):
– limited to 1000 hours duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
3.3V + 5% < VDDP / VDDOSC3 / VDDPF3 / VDDFL3 / VDDMF < 3.3V + 10%
(overvoltage condition):
limited to 1000 hours duration cumulative in lifetime, due to the reliability reduction of
the chip caused by the overvoltage stress.
Table 18
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
1
P2.[4:2], P6.[6:9]
2
P6.[5:4], P6.[11:10]
3
P6.[15:12]
4
P8.[5:0]
5
P8.[7:6]
6
P1.7, P1.9
7
P1.6, P1.12
8
P1.[1:0], P7.[2:0]
9
P7.[5:3]
10
P4.[6:0]
11
P4.[10:7]
12
P4.12, P4.14
13
P10.[5:0]
14
P14.8
Data Sheet
81
V 1.1, 2014-05
TC1791
Electrical ParametersGeneral Parameters
Table 18
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
15
P14.4, P14.6
16
P13.15, P14.0, P14.2
17
P13.[14:11]
18
P13.[10:8]
19
P13.[7:4]
20
P13.[3:0]
21
P9.10, P9.14
22
P9.7, P9.13
23
P9.[4:2], P9.6
24
P9.1, P9.5, P9.8
25
P9.0
26
P5.[11:8]
27
P5.6, P5.[15:12]
28
P5.0, P5.[5:2], P5.7
29
P3.0, P3.4, P5.1
30
P3.10, P3.12
31
P0.[3:0]
32
P0.[11:4]
33
P0.[14:12]
34
P2:12, P2.14
35
P2.[10:5]
Data Sheet
82
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TC1791
Electrical ParametersDC Parameters
5.2
DC Parameters
5.2.1
Input/Output Pins
Table 19
Standard_Pads Parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
TA= 25 °C;
f= 1 MHz
Vi≥ 0.6 x VDDP V
Vi≥ 0.36 x
VDDP V
Vi≤ 0.6 x VDDP V
Vi≤ 0.36 x
VDDP V
Pin capacitance (digital
inputs/outputs)
CIO CC
−
−
10
pF
Pull-down current
|IPDL|
CC
−
−
150
μA
10
−
−
μA
|IPUH|
CC
10
−
−
μA
−
−
100
μA
Spike filter always blocked tSF1 CC
pulse duration
−
−
10
ns
only PORST pin
Spike filter pass-through
pulse duration
100
−
−
ns
only PORST pin
Unit
Note /
Test Condition
Pull-Up current
Table 20
tSF2 CC
Standard_Pads Class_A1
Parameter
Symbol
Min.
Typ.
Max.
Input Hysteresis for A1
pads 1)
HYSA1
0.1 x
−
−
V
CC
VDDP
IOZA1
-500
−
500
nA
VILA1 /
VIHA1
0.6
−
−
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
Input Leakage Current
Class A1
Ratio Vil/Vih, A1 pads
Values
CC
Vi≥ 0 V;
Vi≤ VDDP V
CC
On-Resistance of the
RDSONW
class A1 pad, weak driver CC
Data Sheet
83
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 20
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
On-Resistance of the
class A1 pad, medium
driver
CC
Fall time, pad type A1
tFA1 CC
RDSONM
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
−
−
150
ns
CL= 20 pF; pin
out
driver= weak
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
84
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 20
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A1
Typ.
Max.
tRA1 CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage class
A1 pads
VIHA1
SR
0.6 x
min(V V
DDP+
0.3,3.6
)
−
Input low voltage class A1 VILA1 SR -0.3
pads
Data Sheet
−
VDDP
0.36 x
V
VDDP
85
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TC1791
Electrical ParametersDC Parameters
Table 20
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
Values
Min.
Output voltage high class
A1 pads
VOHA1
CC
Typ.
Unit
Note /
Test Condition
V
IOH≥ -1.4 mA;
Max.
VDDP - −
−
−
−
0.4
2.4
pin out
driver= medium
V
IOH≥ -2 mA; pin
out
driver= medium
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
2.4
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
−
−
0.4
V
IOL≤ 2 mA; pin
0.4
Output voltage low class
A1 pads
VOLA1
CC
out
driver= medium
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 21
Standard_Pads Class_A1+
Parameter
Symbol
Input Hysteresis for A1+
pads 1)
HYSA1
+ CC
IOZA1+
VDDP
RDSONW
Input Leakage Current
Class A1+
On-Resistance of the
class A1+ pad, weak
driver
Data Sheet
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
0.1 x
−
−
V
-1000
−
1000
nA
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
CC
CC
86
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Electrical ParametersDC Parameters
Table 21
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
On-Resistance of the
class A1+ pad, strong
driver
RDSON1+ −
−
100
Ohm IOH> -2 mA;
P_MOS
−
−
80
Ohm IOL< 2 mA;
N_MOS
Fall time, pad type A1+
tFA1+ CC −
−
150
ns
−
−
On-Resistance of the
class A1+ pad, medium
driver
RDSONM
CC
CC
CL= 20 pF; pin
out
driver= weak
28
ns
CL= 50 pF;
edge= slow ;
pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
87
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 21
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A1+
Typ.
Max.
tRA1+ CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
28
ns
CL= 50 pF;
edge= slow ;
pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage, Class
A1+ pads
Input low voltage Class
A1+ pads
Ratio Vil/Vih, A1+ pads
VIHA1+
SR
VILA1+
0.6 x
−
VDDP
0.3,3.6
)
−
-0.3
SR
VILA1+ /
VIHA1+
min(V V
DDP+
0.36 x
V
VDDP
−
0.6
−
CC
Data Sheet
88
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TC1791
Electrical ParametersDC Parameters
Table 21
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Min.
Output voltage high class
A1+ pads
VOHA1+
CC
Typ.
Unit
Note /
Test Condition
V
IOH≥ -1.4 mA;
Max.
VDDP - −
−
VDDP - −
−
−
−
0.4
pin out
driver= medium
V
0.4
2.4
IOH≥ -1.4 mA;
pin out
driver= strong
V
IOH≥ -2 mA; pin
out
driver= medium
−
2.4
−
V
IOH≥ -2 mA; pin
out
driver= strong
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
2.4
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
−
−
0.4
V
IOL≤ 2 mA; pin
0.4
Output voltage low class
A1+ pads
VOLA1+
CC
out
driver= medium
−
−
0.4
V
IOL≤ 2 mA; pin
out
driver= strong
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Data Sheet
89
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 22
Standard_Pads Class_A2
Parameter
Input Hysteresis for A2
pads 1)
Input Leakage current
Class A2
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
HYSA2
0.1 x
−
−
V
CC
VDDP
IOZA2
-6000
−
6000
nA
-3000
−
3000
nA
0.6
−
−
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
−
−
28
Ohm IOH> -2 mA;
P_MOS
−
−
22
Ohm IOL< 2 mA;
N_MOS
CC
Vi< VDDP / 2 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
Vi> VDDP / 2 1 V; Vi< VDDP / 2
+1V
Ratio Vil/Vih, A2 pads
VILA2 /
VIHA2
CC
On-Resistance of the
RDSONW
class A2 pad, weak driver CC
On-Resistance of the
class A2 pad, medium
driver
RDSONM
CC
On-Resistance of the
RDSON2
class A2 pad, strong driver CC
Data Sheet
90
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 22
Standard_Pads Class_A2 (cont’d)
Parameter
Fall time, pad type A2
Symbol
tFA2 CC
Values
Min.
Typ.
Max.
−
−
150
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
−
−
7
ns
CL= 50 pF;
edge= medium
; pin out
driver= strong
−
−
10
ns
CL= 50 pF;
edge= mediumminus ; pin out
driver= strong
−
−
3.7
ns
CL= 50 pF;
edge= sharp ;
pin out
driver= strong
−
−
5
ns
CL= 50 pF;
edge= sharpminus ; pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
7.5
ns
CL= 100 pF;
edge= sharp ;
pin out
driver= strong
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
Data Sheet
91
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 22
Parameter
Standard_Pads Class_A2 (cont’d)
Symbol
Values
Min.
Typ.
Max.
−
−
550
Unit
Note /
Test Condition
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
92
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 22
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A2
Typ.
Max.
tRA2 CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
7.0
ns
CL= 50 pF;
edge= medium
; pin out
driver= strong
−
−
10
ns
CL= 50 pF;
edge= mediumminus ; pin out
driver= strong
−
−
3.7
ns
CL= 50 pF;
edge= sharp ;
pin out
driver= strong
−
−
5
ns
CL= 50 pF;
edge= sharpminus ; pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
7.5
ns
CL= 100 pF;
edge= sharp ;
pin out
driver= strong
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
Data Sheet
93
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 22
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Max.
−
−
550
Unit
Note /
Test Condition
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage, class
A2 pads
VIHA2
SR
0.6 x
VOHA2
CC
min(V V
DDP +
0.3,
3.6)
−
Input low voltage Class A2 VILA2 SR -0.3
pads
Output voltage high class
A2 pads
−
VDDP
0.36 x
V
VDDP
VDDP - −
−
VDDP - −
−
−
−
V
0.4
pin out
driver= medium
V
0.4
2.4
IOH≥ -1.4 mA;
IOH≥ -1.4 mA;
pin out
driver= strong
V
IOH≥ -2 mA; pin
out
driver= medium
−
2.4
−
V
IOH≥ -2 mA; pin
out
driver= strong
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
0.4
2.4
Data Sheet
94
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 22
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Output voltage low class
A2 pads
VOLA2
Values
Min.
Typ.
Max.
−
−
0.4
Unit
Note /
Test Condition
V
IOL≤ 2 mA; pin
CC
out
driver= medium
−
−
0.4
V
IOL≤ 2 mA; pin
out
driver= strong
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 23
Standard_Pads Class_F
Parameter
Input Hysteresis F1)
Input Leakage Current
Class F
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
HYSF
0.05 x
−
−
V
CC
VDDP
IOZF CC -6000
−
6000
nA
-3000
−
3000
nA
−
−
−
170
Ohm IOH> -2 mA;
P_MOS
−
−
145
Ohm IOL< 2 mA;
N_MOS
Vi< VDDP / 2 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
Vi> VDDP / 2 1 V; Vi< VDDP / 2
+1V
Ratio Vil/ Vih, F pads
On-Resistance of the
class F pad, medium
driver
VILF /
0.6
VIHF CC
RDSONM −
CC
Fall time, pad type F,
CMOS mode
tFF CC
−
−
60
ns
CL= 50 pF
Rise time, pad type F,
CMOS mode
tRF CC
−
−
60
ns
CL= 50 pF
Data Sheet
95
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 23
Standard_Pads Class_F (cont’d)
Parameter
Symbol
Values
Min.
Input high voltage, pad
class F, CMOS mode
VIHF SR 0.6 x
VDDP
Input low voltage, Class F VILF SR
pads, CMOS mode
Output high voltage, class VOHF
F pads, CMOS mode
CC
−
min(V V
DDP+
Note /
Test Condition
0.3,
3.6)
0.36 x
V
VDDP
VDDP-
−
−
V
IOH≥ -1.4 mA
−
−
V
−
0.4
V
IOH≥ -2 mA
IOL≤ 2 mA
0.4
2.4
Output low voltage, class
F pads, CMOS mode
Max.
−
-0.3
Unit
Typ.
VOLF CC −
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 24
Standard_Pads Class_I
Parameter
Symbol
Min.
Typ.
Max.
Input Hysteresis Class I1)
HYSI
0.1 x
−
−
V
CC
VDDP
IOZI CC -1000
VILI / VIHI 0.6
−
1000
nA
−
−
VIHI SR
−
min(V V
DDP+
Input Leakage Current
Ratio between low and
high input threshold
Input high voltage, class I
pins
Input low voltage, Class I
pads
Values
Unit
Note /
Test Condition
CC
0.6 x
VDDP
VILI SR
0.3,
3.6)
−
-0.3
0.36 x
V
VDDP
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Class S pad parameters are only valid for VDDM = 4.75 V to 5.25 V.
Data Sheet
96
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 25
Standard_Pads Class_S
Parameter
Symbol
Input Hysteresis for class
S pads1)
Input leakage current
Input voltage high
Input voltage low
VILS Delta
2)
HYSS
Values
Unit
Min.
Typ.
Max.
0.3
−
−
V
-300
−
300
nA
−
−
3.6
V
1.9
−
−
V
-50
−
50
mV
Note /
Test Condition
CC
IOZS CC
VIHS CC
VILS CC
VILSD
CC
Maximum input
low state
threshold
variation over
1ms
(VDDP = consta
nt)
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
2) VILSD is implemented to ensure J2716 specification. It can’t be guaranteed that it suppresses switching due to
external noise.
Table 26
LVDS_Pads Parameters
Parameter
Symbol
Min.
Typ.
Max.
Output impedance, pad
class F, LVDS mode
RO CC
40
−
140
Ohm
Fall time, pad type LVDS
tFL CC
−
−
2
ns
Data Sheet
Values
97
Unit
Note /
Test Condition
termination
100 Ω ± 1 %;
differential
capacitance = 1
0 pF; input
capacitance = 2
0 pF
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 26
LVDS_Pads Parameters (cont’d)
Parameter
Symbol
Unit
Note /
Test Condition
2
ns
termination
100 Ω ± 1 %;
differential
capacitance = 1
0 pF; input
capacitance = 2
0 pF
−
13
μs
termination
100 Ω ± 1 %
−
400
mV
termination
100 Ω ± 1 %
Typ.
Max.
−
−
tSET_LVD −
Rise time, pad type LVDS tRL CC
Pad set-up time
Values
Min.
S
CC
Output Differential Voltage VOD CC 150
Output voltage high, pad
class F, LVDS mode
VOH CC −
−
1525
mV
termination
100 Ω ± 1 %
Output voltage low, pad
class F, LVDS mode
VOL CC
−
−
mV
termination
100 Ω ± 1 %
Output Offset Voltage
VOS CC 1075
−
1325
mV
termination
100 Ω ± 1 %
Data Sheet
875
98
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
5.2.2
Analog to Digital Converters (ADCx)
ADC parameter are valid for VDD / DDAF = 1.235 V to 1.365 V; VDDM = 4.5 V to 5.5 V.
Table 27
ADC Parameters
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
CAINSW
Switched capacitance at
the analog voltage inputs1) CC
−
9
20
pF
Total capacitance of an
analog input
−
20
30
pF
Switched capacitance at
the positive reference
voltage input2)3)
CAREFSW −
15
30
pF
Total capacitance of the
voltage reference inputs2)
CAREFTO −
20
40
pF
Differential Non-Linearity
Error4)5)6)7)
Gain Error4)5)6)7)
CAINTOT
CC
CC
T CC
EADNL
-3
−
3
LSB
ADC
resolution= 12bit 8) 9)
EAGAIN
-3.5
−
3.5
LSB
ADC
resolution= 12bit 8) 9)
EAINL
-3
−
3
LSB
ADC
resolution= 12bit 8) 9)
EAOFF
-4
−
4
LSB
ADC
resolution= 12bit 8) 9)
CC
CC
Integral NonLinearity4)5)6)7)
Offset Error4)5)6)7)
CC
CC
Converter clock
Internal ADC clock
Charge consumption per
conversion
Note /
Test Condition
fADC SR 4
fADCI CC 1
−
100
MHz fADC= fFPI
−
18
MHz ADC0
1
−
18
MHz ADC1
1
−
2010)
MHz ADC2
100
pC
QCONV
11)
70
85
CC
charge needs to
be provided via
VAREF0
Data Sheet
99
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 27
ADC Parameters (cont’d)
Parameter
Symbol
Values
Min.
Input leakage at analog
inputs12)
IOZ1 CC -100
Typ.
Max.
−
500
Unit
Note /
Test Condition
nA
Vi≤ VDDM V;
Vi≥ 0.97 x
VDDM V;
overlayed= No
-100
−
600
nA
Vi≥ 0.97 x
VDDM V;
Vi≤ VDDM V;
overlayed= Yes
-500
−
100
nA
Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
-600
−
100
nA
Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
-100
−
200
nA
Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= No
overlayed= Yes
overlayed= No
-100
−
300
nA
Vi< 0.97 x
VDDM V;
Vi> 0.03 x
VDDM V;
overlayed= Yes
Input leakage current at
VAREF0 / VAREF2
IOZ2 CC -1
−
1
μA
Input leakage current at
-2
−
2
μA
IOZ3 CC -4
−
4
μA
RAIN CC −
900
1500
Ohm
VAREF1
Input leakage current at
VAGND0
ON resistance of the
transmission gates in the
analog voltage path
Data Sheet
100
VAREFx≥ 0 V;
VAREFx≤ VDDM V
VAREFx≥ 0 V;
VAREFx≤ VDDM V
VAGND0≥ 0 V;
VAGND0≤ VDDM V
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 27
ADC Parameters (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
ON resistance for the ADC RAIN7T
test (pull down for AIN7)
CC
180
550
900
Ohm
Resistance of the
reference voltage input
path
−
500
1000
Ohm
tS CC
2
tCAL CC −
−
257
TADCI
−
4352
cycle
s
TUE CC -4
−
414)
LSB
Sample time
Calibration time after bit
ADC_GLOBCFG.SUCAL
is set
Total Unadjusted
Error6)5)13)
RAREF
CC
Analog reference ground2) VAGNDx
SR
Analog input voltage
VSSM - −
0.05
VAIN SR VAGNDx −
VAGNDx −
Analog reference voltage2) VAREFx
SR
Analog reference voltage
range6)5)2)
Note /
Test Condition
+1
ADC
resolution= 12bit
VAREFx V
-1
VAREFx V
VDDM + V
0.0515)
16)
VAREFx - VDDM/2 −
VAGNDx
VDDM + V
0.05
SR
1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2.
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the reference voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additional decrease in
the ADC speed and accuracy.
6) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.
8) For 10-bit conversions the error value must be multiplied with a factor 0.25.
9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.
10) For fADCI between 18MHz and 20MHz the TUE and Gain Error can increase beyond the given limits. For
STC < 2 INL, DNL , and Offset errors can also increase.
Data Sheet
101
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
11) For a conversion time of 1 µs a rms value of 85µA result for IAREF0.
12) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation they do not define step function.
13) Measured without noise.
14) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB
15) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).
16) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),
then the accuracy of the ADC decrease by 4LSB12.
Table 28
Conversion Time (Operating Conditions apply)
Parameter
Symbol
Conversion
tC
time with
post-calibration
Values
Unit Note
CC 2 × TADC + (4 + STC + n) × TADCI μs
2 × TADC + (2 + STC + n) × TADCI
Conversion
time without
post-calibration
n = 8, 10, 12 for
n - bit conversion
TADC = 1 / fFPI
TADCI = 1 / fADCI
The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles.
REXT
VAIN =
Analog Input Circuitry
RAIN, On
ANx
CEXT
CAINTOT - CAINSW
VAGNDx
CAINSW
RAIN7T
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFTOT - CAREFSW
CAREFSW
VAGNDx
Analog_InpRefDiag
Figure 8
Data Sheet
ADCx Input Circuits
102
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Ioz1
Single ADC Input
500nA
200nA
100nA
-100nA
VIN[VDDM%]
3%
97% 100%
-500nA
Ioz1
Overlayed ADC/FADC Input
600nA
300nA
100nA
-100nA
VIN[VDDM%]
3%
97% 100%
-600nA
Figure 9
Data Sheet
ADCx Analog Inputs Leakage
103
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
5.2.3
Fast Analog to Digital Converter (FADC)
FADC parameter are vaild for VDD / DDAF = 1.235 V to 1.365 V; VDDMF = 2.97 V to 3.6 V.
Table 29
FADC Parameters
Parameter
Input current at VFAREF
Symbol
Values
Unit
Min.
Typ.
Max.
IFAREF
−
−
120
μA
IFOZ2
-500
−
500
nA
IFOZ3
-500
−
500
nA
EFDNL
-1
−
1
LSB
Note /
Test Condition
CC
Input leakage current at
VFAREF1)
CC
Input leakage current at
VFAGND
CC
DNL error
CC
VFAREF≤ VDDMF
V; VFAREF≥ 0 V
VIN mode=
differential;
Gain = 1 or 2
−
-2
2
LSB
VIN mode=
differential;
Gain = 4 or 82)
−
-1
1
LSB
VIN mode=
single ended;
Gain = 1 or 2
−
-2
2
LSB
VIN mode=
single ended;
Gain = 4 or 82)
GRADient error
EFGRAD -5
−
-5
−
5
%
CC
VIN mode=
differential ;
Gain≤ 4
5
%
VIN mode=
single ended ;
Gain≤ 4
−
-6
6
%
VIN mode=
differential ;
Gain= 8
−
-6
6
%
VIN mode=
single ended ;
Gain= 8
Data Sheet
104
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 29
FADC Parameters (cont’d)
Parameter
INL error
Symbol
EFINL
Values
Unit
Note /
Test Condition
4
LSB
VIN mode=
4
LSB
VIN mode=
Min.
Typ.
Max.
-4
−
-4
−
CC
differential
single ended
Offset error
EFOFF
−
-90
90
mV
CC
VIN mode=
differential ;
Calibration= No
−
-90
90
mV
VIN mode=
single ended ;
Calibration= No
−
-20
20
mV
VIN mode=
differential ;
Calibration= Ye
s 3)4)
−
-20
20
mV
VIN mode=
single ended ;
Calibration= Ye
s 3)4)
EFREF
-60
−
60
mV
Channel amplifier cutoff
frequency
fCOFF
2
−
−
MHz
Converter clock
fFADC
1
−
100
MHz fFADC= fFPI
tC CC
−
−
21
1/
Input resistance of the
analog voltage path (Rn,
Rp)
RFAIN
100
Settling time of a channel
amplifier after changing
ENN or ENP
tSET CC −
Analog input voltage
range
VAINF
Error of commen mode
voltage VFAREF/2
CC
CC
SR
Conversion time
Data Sheet
−
200
kOh
m
−
5
μs
VDDMF
V
CC
SR
For 10-bit
fFADC conversion
VFAGND −
105
V 1.1, 2014-05
TC1791
Electrical ParametersDC Parameters
Table 29
FADC Parameters (cont’d)
Parameter
Symbol
Values
Min.
Analog reference ground
VFAGND
VSSAF - −
VFAREF
2.97
SR
Analog reference voltage
Typ.
0.05
SR
−
Unit
Max.
VSSAF
V
3.635)
V
Note /
Test Condition
+ 0.05
6)
1) This value applies in power-down mode.
2) No missing codes.
3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed
minimium once per week.
4) The offser error voltage drifts over the whole temperature range maximum +-3LSB.
5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum
of the pulses does not exceed 1 h.
6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage
overshoots).
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized.
Data Sheet
106
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Electrical ParametersDC Parameters
FADC Analog Input Stage
FAINxN
-
=
VFAGND
RN
VFAREF /2
+
+
FAINxP
RP
-
FADC Reference Voltage
Input Circuitry
VFAREF
IFAREF
VFAREF
VFAGND
FADC_InpRefDiag
Figure 10
Data Sheet
FADC Input Circuits
107
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Electrical ParametersDC Parameters
5.2.4
Table 30
Oscillator Pins
OSC_XTAL Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
VIN<VDDOSC3 ;
VIN>0 V
Min.
Typ.
Max.
-25
−
25
μA
Input current at XTAL1
IIX1 CC
Input frequency
fOSC SR 4
−
40
MHz Direct Input
Mode selected
8
−
25
MHz External Crystal
Mode selected
−
−
10
ms
VDDOS
V
Oscillator start-up time1)
tOSCS
CC
Input high voltage at
XTAL12)
VIHX SR 0.7 x
VDDOS
Input low voltage at
XTAL1
VILX SR -0.5
Input Hysteresis for
XTAL1 pad 3)
HYSAX
−
+
0.5
C3
C3
−
0.3 x
V
VDDOS
C3
−
−
200
mV
CC
1) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of
0.3 * VDDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative
resistance as recommended and specified by crystral suppliers.
2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is
necessary.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Data Sheet
108
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TC1791
Electrical ParametersDC Parameters
5.2.5
Table 31
Temperature Sensor
DTS Parameters
Parameter
Symbol
Values
Min.
Measurement time
Temperature sensor
range
tM CC
TSR SR
Unit
Typ.
Max.
−
−
100
μs
-40
−
150
°C
Sensor Accuracy
(calibrated)
TTSA CC -6
−
6
°C
Start-up time after resets
inactive
tTSST SR −
−
20
μs
Note /
Test Condition
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
(1)
DTSSTAT RESULT – 596
Tj = ------------------------------------------------------------------2, 03
Data Sheet
109
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TC1791
Electrical ParametersDC Parameters
5.2.6
Power Supply Current
The total power supply current defined below consists of leakage and switching
component.
Application relevant values are typically lower than those given in the following
two tables and depend on the customer's system operating conditions (e.g.
thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
VDD / VDDOSC / VDDAF / VDDPF = 1.365 V, VDDP / VDDOSC / VDDMF / VDDFL3 / VDDPF = 3.47 V,
VDDM = 5.25 V fSRI / CPU=240 / 200 MHz, fPCP=120 / 200 MHz, fSRI=80 / 100 MHz,
TJ=150 oC
The realisic power pattern defines the following conditions:
•
•
•
•
•
•
•
TJ=150 oC
fSRI = fCPU = 240 / 200 MHz
fPCP = 120 / 200 MHz
fFPI = 80 / 100MHz
VDD = VDDOSC = VDDAF = VDDPF = 1.326 V
VDDP = VDDOSC3 = VDDFL3 VDDPF3 = VDDMF = 3.366 V
VDDM = 5.1 V
The max power pattern defines the following conditions:
•
•
•
•
•
•
•
TJ=150 oC
fSRI = fCPU = 240 / 200 MHz
fPCP = 120 / 200 MHz
fFPI = 80 / 100MHz
VDD = VDDOSC = VDDAF = VDDPF = 1.43 V
VDDP = VDDOSC3 = VDDFL3 VDDPF3 = VDDMF = 3.63 V
VDDM = 5.5 V
Data Sheet
110
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TC1791
Electrical ParametersDC Parameters
Table 32
Power Supply Parameters
Parameter
Unit
Note /
Test Condition
7893)
mA
power
pattern= max;
fCPU=240 MHz
−
591
mA
power
pattern= realisti
c;
fCPU=240 MHz
−
−
7354)
mA
power
pattern= max;
fCPU=200 MHz
−
−
555
mA
power
pattern= realisti
c;
fCPU=200 MHz
IDD current at PORST Low IDD_PORS −
T CC
−
−
298
mA
−
249
mA
TJ=150 oC
TJ=140 oC
Core active mode supply
current1)2)
Symbol
IDD CC
Values
Min.
Typ.
Max.
−
−
−
E-Ray PLL core supply
current
IDDPF
−
−
4
mA
Oscillator core supply
current
IDDOSC
−
−
3
mA
Analog core supply
current
IDDAF
−
−
26
mA
Sum of all 1.3 V supply
currents
IDDSUM
−
−
624
mA
power
pattern= realisti
c;
fCPU=240 MHz
−
−
588
mA
power
pattern= realisti
c;
fCPU=200 MHz
IDDPF3
−
−
4
mA
IDDOSC3
−
−
11
mA
E-Ray PLL 3.3V supply
CC
CC
CC
CC
CC
Oscillator power supply
current, 3.3V
Data Sheet
CC
111
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TC1791
Electrical ParametersDC Parameters
Table 32
Power Supply Parameters (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note /
Test Condition
FADC analog supply
current, 3.3V
IDDMF
−
−
15
mA
IDDP current at PORST
IDDP_POR −
−
7
mA
−
IDDP_
mA
including flash
read current
mA
including flash
programming
current 6)
mA
including flash
erase verify
current 6)
CC
Low
ST
CC
IDDP CC −
IDDP current no pad
activity, LVDS off 5)
PORST
+ 25
−
−
IDDP_
PORST
+ 55
−
−
IDDP_
PORST
7)
+ 40
5)
−
−
98
mA
flash read
current
−
−
29
mA
flash
programming
current 6)
−
−
98
mA
flash erase
current 6)
ILVDS
−
−
24
mA
in total for all
LVDS pairs
Sum of all 3.3 V supply
currents, no pad activity,
LVDS off
IDD3SUM
−
−
160 8)
mA
including flash
read current
ADC 5V power supply
current
IDDM CC −
−
6
mA
Flash memory current
IDDFL3
CC
Current Consumption of
LVDS Pad Pairs
Data Sheet
CC
CC
112
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TC1791
Electrical ParametersDC Parameters
Table 32
Power Supply Parameters (cont’d)
Parameter
Symbol
Maximum power
dissipation
PD CC
Values
Unit
Note /
Test Condition
1706
mW
power
pattern= max;
fCPU=240 MHz
−
1449
mW
power
pattern= realisti
c;
fCPU=240 MHz
−
−
1523
mW
power
pattern= max;
fCPU=200 MHz
−
−
1403
mW
power
pattern= realisti
c;
fCPU=200 MHz
Min.
Typ.
Max.
−
−
−
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer
application will most probably be lower than this value, but must be evaluated seperately.
2) This current includes the E-Ray module power consumption, including the PCP operation component.
3) The IDD decreases typically by 102 mA if the fCPU decreases by 50MHz, at constant TJ
4) The IDD decreases typically by 105 mA if the fCPU decreases by 50MHz, at constant TJ
5) For operations including the D-Flash the required currents are always lower than the currents for non D-Flash
operation.
6) Relevant for the power supply dimensioning, not for thermal considerations.
7) In case of erase of Program Flash PFx, internal flash array loading effects may generate transient current
spikes of up to 15 mA for maximum 5 ms per flash module.
8) For power supply dimensioning of VDDP 30 mA have to added for flash programming case.
Note: In general current consumption for operations with data flash are always lower
than the defined values for program flash read operation.
5.2.6.1
Calculating the 1.3 V Current Consumption
The current consumption of the 1.3 V rail compose out of two parts:
•
•
Static current consumption
Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic
current consumption depends of the configured clocking frequencies and the software
Data Sheet
113
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TC1791
Electrical ParametersDC Parameters
application executed. These two parts needs to be added in order to get the rail current
consumption.
(2)
I
0
mA
= 3, 75 --------- × e 0, 02041 × T J [ C ]
C
(3)
I
0
mA
= 18, 77 --------- × e 0, 01825 × T J [ C ]
C
Function 2 defines the typical static current consumption and Function 3 defines the
maximum static current consumption. Both functions are valid for VDD = 1.326 V.
For the dynamic current consumption using the real pattern and fSRI = 2 * fPCP = 3 * fFPI
the function 4 applies:
(4)
mA
I D m = 1, 22 ------------- × f CPU [ MHz ]
y
MHz
For the dynamic current consumption using the real pattern and fSRI = fPCP = 2 * fFPI the
function 5 applies:
(5)
mA
I D m = 1, 305 ------------- × f CPU [ MHz ]
y
MHz
and this finally results in
(6)
I DD = I 0 + I DYM
Data Sheet
114
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TC1791
Electrical ParametersAC Parameters
5.3
AC Parameters
All AC parameters are defined with maximum driver strength unless otherwise noted.
5.3.1
Testing Waveforms
VD D P
90%
90%
10%
10%
VSS
tR
tF
rise_fall
Figure 11
Rise/Fall Time Parameters
VD D P
VD D E / 2
Test Points
VD D E / 2
VSS
mct04881_a.vsd
Figure 12
Testing Waveform, Output Delay
VLoad+ 0.1 V
VLoad- 0.1 V
Timing
Reference
Points
VOH - 0.1 V
VOL - 0.1 V
MCT04880_new
Figure 13
Data Sheet
Testing Waveform, Output High Impedance
115
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TC1791
Electrical ParametersAC Parameters
5.3.2
Power Sequencing
V
5.25V
5V
4.75V
VAREF
3.47V
3.3V
3.0V
-12%
1.365V
1.3V
1.235V
0.5V
-12%
0.5V
0.5V
t
VDDP
PORST
power
down
Figure 14
power
fail
t
Power-Up 10.vsd
5 V / 3.3 V / 1.3 V Power-Up/Down Sequence
The following list of rules applies to the power-up/down sequence:
•
•
•
All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current component, all ground pins are internally directly
connected.
At any moment in time to avoid increased latch-up risk,
each power supply must be higher then any lower_power_supply - 0.5 V, or:
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see Figure 14.
– The latch-up risk is minimized if the I/O currents are limited to:
– 20 mA for one pin group
– AND 100 mA for the completed device I/Os
– AND additionally before power-up / after power-down:
1 mA for one pin in inactive mode (0 V on all power supplies)
During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than 100 mV.
On the other hand, all power supply pins with the same name (for example all VDDP),
Data Sheet
116
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TC1791
Electrical ParametersAC Parameters
1.
2.
3.
4.
5.
6.
are internally directly connected. It is recommended that the power pins of the same
voltage are driven by a single power supply.
The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF powersupplies and the oscillator have reached stable operation, within the normal
operating conditions.
At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V
power supply voltage falls 12% below the nominal level. If, under these conditions,
the PORST is activated during a Flash write, only the memory row that was the target
of the write at the moment of the power loss will contain unreliable content. In order
to ensure clean power-down behavior, the PORST signal should be activated as
close as possible to the normal operating voltage range.
In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rules number 2 and 4.
Although not necessary, it is additionally recommended that all power supplies are
powered-up/down together in a controlled way, as tight to each other as possible.
Additionally, regarding the ADC reference voltage VAREF:
– VAREF must power-up at the same time or later then VDDM, and
– VAREF must power-down either earlier or at latest to satisfy the condition
VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter
capacitance through the ESD diodes through the VDDM power supply. In case of
discharging the reference capacitance through the ESD diodes, the current must
be lower than 5 mA.
Data Sheet
117
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TC1791
Electrical ParametersAC Parameters
5.3.3
Table 33
Power, Pad and Reset Timing
Reset Timings Parameters
Parameter
Symbol
Values
Min.
Application Reset Boot
Time1)2)
tB CC
Power on Reset Boot
Time3)4)
tBP CC
Typ.
Unit
Note /
Test Condition
fCPU = 240 MHz
fCPU = 200 MHz
Max.
−
−
1015
μs
−
−
1140
μs
−
−
2.5
ms
−
−
ns
−
−
ns
HWCFG pins hold time
from ESR0 rising edge
tHDH SR 16 /
fFPI
HWCFG pins setup time to tHDS SR 0
ESR0 rising edge
Ports inactive after ESR0
reset active
tPI CC
−
−
8/fFPI
ns
Ports inactive after
PORST reset active5)
tPIP CC
−
−
150
ns
Minimum PORST active
time after power supplies
are stable at operating
levels
tPOA SR 10
−
−
ms
TESTMODE / TRST hold
time from PORST rising
edge
tPOH SR 100
−
−
ns
PORST rise time
tPOR SR −
tPOS SR 0
−
50
ms
−
−
ns
−
40 6)
μs
TESTMODE / TRST
setup time to PORST
rising edge
Application Reset inactive tPOR_APP −
after PORST deassertion SR
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
2) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the
first user instruction has entered the CPU pipeline and its processing starts.
4) The given time includes the internal reset extension time for the System and Application Reset which is visible
through ESR0.
Data Sheet
118
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TC1791
Electrical ParametersAC Parameters
5) This parameter includes the delay of the analog spike filter in the PORST pad.
6) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the
Application Reset is extended.
VDD P -12%
VD D PPA
V D DPPA
VDDP
VDD
VD D -12%
tPOA
tPOA
PORST
tPOH
TRST
TESTMODE
ESR0
tPOH
t hd
t hd
tHDH
tHDH
tHDH
HWCFG
t PIP
tPI
Pads
tPI
t PIP
tPI
tPI
t PIP
tPI
Pad-state undefined
Tri-state or pull device active
reset_beh2
As programmed
Figure 15
Data Sheet
Power, Pad and Reset Timing
119
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TC1791
Electrical ParametersAC Parameters
5.3.4
Table 34
Phase Locked Loop (PLL)
PLL_SysClk Parameters
Parameter
Symbol
Values
Min.
Accumulated Jitter
Modulation frequency
PLL base frequency
DP CC -7
fMOD SR 50
fPLLBASE 50
Unit
Typ.
Max.
−
7
Note /
Test Condition
ns
−
200
kHz
200
320
MHz
fREF CC 8
fVCO CC 400
−
16
MHz
−
720
MHz with inactive
modulation
400
−
600
MHz with active
modulation
−
2.5
ns
−
9.5
ns
CC
VCO input frequency
VCO frequency range
Modulation jitter
Total long term jitter
JMOD CC −
JTOT CC −
Sum of DP and
JMOD
Modulation Amplitude
PLL lock-in time
System frequency
deviation
MA SR
tL CC
fSYSD
−
0
2.5
%
% of fVCO
14
−
200
μs
N > 32
14
−
400
μs
N ≤ 32
−
−
0.01
%
with active
modulation
CC
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the SRIBus clock fSRI) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Data Sheet
120
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Electrical ParametersAC Parameters
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in
[ns] dependent on the K2 - factor, the SRI clock frequency fSRI in [MHz], and the number
m of consecutive fSRI clock periods.
for
( K2 ≤ 100 )
( m ≤ ( f SRI [ MHz ] ) ⁄ 2 )
and
( 1 – 0, 01 × K2 ) × ( m – 1 )
740
D m [ ns ] = ⎛⎝ ------------------------------------------ + 5⎞⎠ × ⎛⎝ ---------------------------------------------------------------- + 0, 01 × K2⎞⎠
0, 5 × f SRI [ MHz ] – 1
K2 × f SRI [ MHz ]
else
740
D m [ ns ] = ------------------------------------------ + 5
K2 × f SRI [ MHz ]
(7)
(8)
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
accumulated jitter remains at a constant value. Further, a lower SRI-Bus clock frequency
fSRI results in a higher absolute maximum jitter value.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
VDDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Oscillator Watchdog (OSC_WDT)
The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The
OSC_WDT checks for too low frequencies and for too high frequencies.
The frequency that is monitored is fOSCREF which is derived for fOSC.
(9)
f O S C R EF
fO S C
= ---------------------------------OSCVAL + 1
The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is
2.5 MHz.
Data Sheet
121
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Electrical ParametersAC Parameters
Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as
possible to 2.5 MHz.
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above
7.5 MHz. This leads to the following two conditions:
•
•
Too low: fOSC < 1.25 MHz × (SCU_OSCCON.OSCVAL+1)
Too high: fOSC > 7.5 MHz × (SCU_OSCCON.OSCVAL+1)
Note: The accuracy is 30% for these boundaries.
Frequency Modulation
Frequency modulation defines a slow and predictable variation of the clock speed. The
modulation configuration itself is controlled via register SCU_PLLCON2 where the two
bit fields define the modulation properties.
(10)
f OSC MODFREQ × 31, 32
f MOD = -------------- × ---------------------------------------------------P
MODAMP
(11)
MODAMP
MA = ----------------------------
N × 161
Data Sheet
122
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TC1791
Electrical ParametersAC Parameters
5.3.5
Table 35
ERAY Phase Locked Loop (ERAY_PLL)
PLL_ERAY Parameters
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
Accumulated jitter at
SYSCLK pin
DPP CC -0.8
−
0.8
ns
Accumulated_Jitter
DP CC -0.5
fPLLBASE_ 50
−
0.5
ns
250
360
MHz
fREF CC 20
−
40
MHz
fVCO_ERA 450
−
500
MHz
−
200
μs
PLL Base Frequency of
the ERAY PLL
VCO input frequency of
the ERAY PLL
ERAY
Note /
Test Condition
CC
VCO frequency range of
the ERAY PLL
Y
PLL lock-in time
tL CC
CC
5.6
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDPF3 and VSSPF, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
123
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TC1791
Electrical ParametersAC Parameters
5.3.6
JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 36
JTAG Interface Timing Parameters
(Operating Conditions apply)
Parameter
Min.
Typ.
Max.
Unit Note /
Test Condition
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
25
–
–
ns
–
10
–
–
ns
–
10
–
–
ns
–
–
–
4
ns
–
–
–
4
ns
–
6
–
–
ns
–
t7 SR
6
–
–
ns
–
TDO valid after TCK falling t8 CC
edge1) (propagation delay) t CC
8
–
–
13
ns
CL = 50 pF
3
–
–
ns
CL = 20 pF
TDO hold after TCK falling t18 CC
edge1)
2
–
–
ns
TDO high imped. to valid
from TCK falling edge1)2)
t9 CC
–
–
14
ns
CL = 50 pF
TDO valid to high imped.
from TCK falling edge1)
t10 CC
–
–
13.5
ns
CL = 50 pF
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
Symbol
Values
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
124
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Electrical ParametersAC Parameters
t1
0.9 VD D P
0.5 VD D P
t5
t2
0.1 VD D P
t4
t3
MC_ JTAG_ TCK
Figure 16
Test Clock Timing (TCK)
TCK
t6
t7
t6
t7
TMS
TDI
t9
t8
t1 0
TDO
t18
Figure 17
Data Sheet
MC_JTAG
JTAG Timing
125
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
5.3.7
DAP Interface Timing
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 37
DAP Parameters
Parameter
Symbol
1)
tTCK SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
DAP0 clock period
DAP0 high time
1)
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Values
Unit
Min.
Typ.
Max.
12.5
−
−
ns
4
−
−
ns
4
−
−
ns
−
−
2
ns
−
−
2
ns
6.0
−
−
ns
DAP1 hold after DAP0
rising edge
t17 SR
6.0
−
−
ns
DAP1 valid per DAP0
clock period2)
t19 CC
8
−
−
ns
10
−
−
ns
Note /
Test Condition
CL= 20 pF;
f= 80 MHz
CL= 50 pF;
f= 40 MHz
1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VD D P
0.5 VD D P
t1 5
t1 2
t14
0.1 VD D P
t1 3
MC_DAP0
Figure 18
Data Sheet
Test Clock Timing (DAP0)
126
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
DAP0
t1 6
t1 7
DAP1
MC_ DAP1_RX
Figure 19
DAP Timing Host to Device
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 20
5.3.8
Data Sheet
DAP Timing Device to Host
Micro Link Interface (MLI) Timing
127
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
MLI Transmitter Timing
t13
t14
t10
t12
TCLKx
t11
t15
t15
TDATAx
TVALIDx
t16
t17
TREADYx
MLI Receiver Timing
t23
t24
t20
RCLKx
t22
t21
t25
t26
RDATAx
RVALIDx
t27
t27
RREADYx
MLI_Tmg_2.vsd
Figure 21
MLI Interface Timing
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
The MLI parameters are vaild for CL = 50 pF and strong driver medium edge.
Data Sheet
128
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
Table 38
MLI Receiver
Parameter
Symbol
Values
Unit
Min.
Typ.
1 / fFPI
−
−
ns
−
0.5 x
−
ns
−
ns
−
4
ns
−
−
4
ns
4.2
−
−
ns
RDATA/RVALID hold time t26 SR
after RCLK falling edge
2.2
−
−
ns
RREADY output delay
time
0
−
16
ns
RCLK clock period
RCLK high time1)2)
t20 SR
t21 SR
Max.
Note /
Test Condition
t20
RCLK low time1)2)
t22 SR
−
0.5 x
t20
RCLK rise time3)
RCLK fall time
3)
RDATA/RVALID setup
time before RCLK falling
edge
t23 SR
t24 SR
t25 SR
t27 SR
−
1) The following formula is valid: t21 + t22 = t20.
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver
timing parameters.
3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
Table 39
MLI Transmitter
Parameter
TCLK clock period
Symbol
t10 CC
Values
Unit
Min.
Typ.
Max.
2x1/
−
−
ns
0.45 x
0.5 x
0.55 x
ns
t10
t10
t10
0.45 x
0.5 x
0.55 x
t10
t10
t10
Note /
Test Condition
fFPI
TCLK high time1)2)
TCLK low time1)2)
t11 CC
t12 CC
ns
TCLK rise time
t13 CC
−
−
0.3 x
ns
TCLK fall time
t14 CC
−
−
0.3 x
ns
Data Sheet
129
t103)
t103)
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
MLI Transmitter (cont’d)
Table 39
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
TDATA/TVALID output
delay time
t15 CC
-3
−
4.4
ns
TREADY setup time
before TCLK rising edge
t16 SR
18
−
−
ns
TREADY hold time after
TCLK rising edge
t17 SR
-2
−
−
ns
Note /
Test Condition
1) The following formula is valid: t11 + t12 = t10.
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
5.3.9
Micro Second Channel (MSC) Interface Timing
The MSC parameters are vaild for CL = 50 pF.
Table 40
MSC Parameters
Parameter
Symbol
FCLP clock period1)2)
t40 CC
SOP4)/ENx outputs delay
from FCLP4) rising edge
t45 CC
SDI bit time
t46 CC
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
2x
−
−
ns
-2
−
5
ns
ENx with strong
driver and
sharp (minus )
edge
-2
−
10
ns
ENx with strong
driver and
medium
(minus) edge
0
−
21
ns
ENx with strong
driver and soft
edge
8x
−
−
ns
TMSC3)
TMSC
Data Sheet
130
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
Table 40
MSC Parameters (cont’d)
Parameter
Symbol
t48 SR
t49 SR
SDI rise time
SDI fall time
Values
Unit
Min.
Typ.
Max.
−
−
200
ns
−
−
200
ns
Note /
Test Condition
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.
2) FCLP signal high and low can be minimum 1xTMSC
3) TMSC = TSYS = 1 / fSYS.
4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.
t40
0.9 VDDP
0.1 VDDP
FCLP
t45
t45
SOP
EN
t48
t49
0.9 VDDP
0.1 VDDP
SDI
t46
Figure 22
t46
MSC_Tmg_1.vsd
MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
131
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
5.3.10
SSC Master/Slave Mode Timing
The SSC parameters are vaild for CL = 50 pF and strong driver medium edge.
Table 41
SSC Parameters
Parameter
Symbol
1)2)3)
SCLK clock period
t50 CC
Values
Unit
Min.
Typ.
Max.
2x1/
−
−
ns
Note /
Test Condition
fFPI
MTSR/SLSOx delay form
SCLK rising edge
t51 CC
0
−
8
ns
MRST setup to SCLK
latching edge3)
t52 SR
16.5
−
−
ns
MRST hold from SCLK
latching edge3)
t53 SR
0
−
−
ns
SCLK input clock
period1)3)
t54 SR
4x1/
−
−
ns
SCLK input clock duty
cycle
t55_t54
45
−
55
%
MTSR setup to SCLK
latching edge3)4)
t56 SR
1 / fFPI
−
−
ns
MTSR hold from SCLK
latching edge
t57 SR
1 / fFPI
+5
−
−
ns
SLSI setup to first SCLK
latching edge
t58 SR
1 / fFPI
+5
−
−
ns
SLSI hold from last SCLK t59 SR
latching edge5)
7
−
−
ns
MRST delay from SCLK
shift edge
t60 CC
0
−
16.5
ns
SLSI to valid data on
MRST
t61 CC
−
−
16.5
ns
fFPI
SR
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xTSSC.
3) TSSCmin = TSYS = 1/fSYS.
4) Fractional divider switched off, SSC internal baud rate generation used.
Data Sheet
132
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair
of shifting / latching edges.
t50
SCLK1)2)
t51
t51
MTSR1)
t52
t53
Data
valid
1)
MRST
t51
2)
SLSOn
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 23
Data Sheet
SSC Master Mode Timing
133
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
t54
First latching
SCLK edge
First shift
SCLK edge
SCLK1)
t55
t56
Last latching
SCLK edge
t55
t56
t57
Data
valid
1)
MTSR
t57
Data
valid
t60
t60
1)
MRST
t61
SLSI
t59
t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
Figure 24
Data Sheet
SSC_TmgSM
SSC Slave Mode Timing
134
V 1.1, 2014-05
TC1791
Electrical ParametersAC Parameters
5.3.11
ERAY Interface Timing
The timings of this section are valid for the strong driver and either sharp edge or medium
edge settings of the output drivers with CL = 25 pF.
The ERAY interface is only available for the SAK-TC1791F-512F240EP / SAKTC1791F-512F240EL / SAK-TC1791S-512F240EP / SAK-TC1791F384F200EL / SAK-TC1791F-384F200EP / SAK-TC1791S-384F200EP.
Table 42
ERAY Parameters
Parameter
Symbol
Values
Time span from last BSS
to FES without the
influence of quartz
tolerancies (d10Bit_TX)1)
t60 CC
997.75 −
1002.2 ns
5
TxD data valid from
fsample flip flop txd_reg
TxDA, TxDB
(dTxAsym)2)3)
t61-t62
−
−
1.5
Time span between last
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)1)4)5)
t63 SR
966
−
1046.1 ns
RxD capture by fsample
(RxDA/RxDB sampling
flip-flop) (dRxAsym)6)
t64-t65
−
−
3.0
ns
Asymmetrical
delay of rising
and falling edge
(RxDA, RxDB)
TxD data delay from
sampling flip-flop
dTxdly
−
−
10.0
ns
Px_PDR.PDy =
000B
−
−
15.0
ns
Px_PDR.PDy =
001B
−
−
10.0
ns
Min.
RxD capture delay by
sampling flip-flop
Typ.
Unit
Max.
ns
CC
CC
CC
dRxdly
Note /
Test Condition
Asymmetrical
delay of rising
and falling edge
(TxDA, TxDB)
CC
1) This includes the PLL_ERAY accumulated jitter.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulated jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tFA2 - tRA2| ≤ 1 ns.
4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.
Data Sheet
135
V 1.1, 2014-05
TC1791
Electrical ParametersFlash Memory Parameters
5) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * VDDP to 80% * VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6ns ≤ tFA2 - tRA2 ≤ 1.3ns.
6) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * VDDP to 80% * VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6ns ≤ tFA2 - tRA2 ≤ 1.3ns.
Last CRC Byte
BSS
(Byte Start Sequence)
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
TXD
t60
tsample
TXD
0.9 VDD
0.1 VDD
t61
t62
Last CRC Byte
BSS
(Byte Start Sequence)
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
RXD
t63
tsample
RXD
0.7 VDD
0.3 VDD
t64
t65
ERAY_TIMING
Figure 25
5.4
ERAY Timing
Flash Memory Parameters
The data retention time of the TC1791’s Flash memory depends on the number of times
the Flash memory has been erased and programmed.
Data Sheet
136
V 1.1, 2014-05
TC1791
Electrical ParametersFlash Memory Parameters
Table 43
FLASH32 Parameters
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
Note /
Test Condition
Data Flash Erase Time
per Sector
tERD CC −
−
4.21)
s
Program Flash Erase
Time per 256 KByte
Sector
tERP CC −
−
5
s
Program time data flash
per page2)
tPRD CC −
−
5.3
ms
without
reprogramming
−
−
15.9
ms
with two
reprogramming
cycles
tPRP CC −
−
5.3
ms
without
reprogramming
−
−
10.6
ms
with one
reprogramming
cycle
−
cycle Min. data
s
retention time 5
years
Program time program
flash per page3)
Data Flash Endurance
Erase suspend delay
NE CC
60000 −
4)
tFL_ErSusp −
−
15
ms
tFL_Margin 10
−
−
μs
CC
Wait time after margin
change
Del
CC
Program Flash Retention
Time, Physical Sector5)6)
tRET CC 20
−
−
year
s
Max. 1000
erase/program
cycles
Program Flash Retention
Time, Logical Sector5)6)
tRETL CC 20
−
−
year
s
Max. 100
erase/program
cycles
UCB Retention Time5)6)
tRTU CC 20
−
−
year
s
Max. 4
erase/program
cycles per UCB
Wake-Up time
tWU CC
−
270
μs
Data Sheet
−
137
V 1.1, 2014-05
TC1791
Electrical ParametersFlash Memory Parameters
Table 43
FLASH32 Parameters (cont’d)
Parameter
Symbol
Values
Min.
DFlash wait state
configuration
WSDF
PFlash wait state
configuration
WSPF
CC
CC
Typ.
50 ns x −
fFSI
26 ns x −
fFSI
Unit
Max.
Note /
Test Condition
−
−
1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can
increase by up to 100%.
2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each
reprogramming takes additional 5 ms.
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.
5) Storage and inactive time included.
6) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperature
of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is
minimum 0.7 years.
Data Sheet
138
V 1.1, 2014-05
TC1791
Electrical ParametersPackage and Reliability
5.5
Package and Reliability
5.5.1
Package Parameters
Table 44
Thermal Characteristics of the Package
Device
Package
RΘJCT1)
RΘJCB1) RΘJA
Unit
TC1791
PG-LFBGA- 292-6
3,73
4,98
K/W
15,0
Note
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between
the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are
under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
RTJA can be obtained from the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).
Data Sheet
139
V 1.1, 2014-05
TC1791
Electrical ParametersPackage and Reliability
Package Outline
292 x
0 .5 ±0.05
A
0.15 M C A B
0.08 M C
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1 7 ±0.1
0.1 C
CODE
COPLANARITY
INDEX MARKING
(LASERED )
C
SEATING PLANE
292 x
0.15
Y W V U T R P N M L K J HG F E D C B A
19 x 0 .8 = 15.2
17 ±0. 1
B
1 .7 MAX
0.8
5.5.2
INDEX
MARKING
0.8
19 x 0.8 = 15 .2
0.33 MIN
STANDOFF
Figure 26
Package Outlines PG-LFBGA- 292-6
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products.
5.5.3
Table 45
Parameter
Quality Declarations
Quality Parameters
Symbol
Values
Unit
Note / Test Condition
Min. Typ. Max.
–
–
24000 hours –2)
ESD susceptibility VHBM
according to
Human Body
Model (HBM)
–
–
2000
V
Conforming to
JESD22-A114-B
ESD susceptibility VHBM1
of the LVDS pins
–
–
500
V
–
Operation
Lifetime1)
Data Sheet
tOP
140
V 1.1, 2014-05
TC1791
Electrical ParametersPackage and Reliability
Table 45
Quality Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min. Typ. Max.
ESD susceptibility VCDM
according to
Charged Device
Model (CDM)
–
–
500
V
Conforming to
JESD22-C101-C
Moisture
Sensitivity Level
–
–
3
–
Conforming to Jedec
J-STD-020C for 240°C
MSL
1) This lifetime refers only to the time when the device is powered on.
2)For worst-case temperature profile equivalent to:
1200 hours at Tj = 125...150oC
3600 hours at Tj = 110...125oC
7200 hours at Tj = 100...110oC
11000 hours at Tj = 25...100oC
1000 hours at Tj = -40...25oC
Data Sheet
141
V 1.1, 2014-05
TC1791
History
6
History
The following changes where done between Version 0.6 and 0.62 of this document:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
add footnote to port 4.1 alternate output 3 MTSR2
change function description for port 4.1 alternate output 3 MTSR2 from Slave to
Master Transmit
add footnote to port 6.4 alternate output 1 MTSR1
add footnote to port 7.1 alternate output 2 MTSR3
change for port 8.3 the symbol from OUT43 (GPTA1) to CC62 (CCU60)
change for port 17 the type from S to D / S
add clarification that table 11 defines the conditions for all other parameters
add conditions for MLI, MSC, SSC, parameters
add parameters dTxdly and dRxdly to ERAY parameters
correct footnotes for ERAY parameters
split flash parameters tPRD and tPRP in two conditions
add conditions to LVDS pad parameters
remove Pin Reliability in Overload section
add parameters IIN and Sum IIN to absolute ratings
add parameter HYSX to PSC_XTAL
added RDSON values for all driver settings (weak, medium, and strong)
removed footnote 2 of table 10
change load for timing of SSC, MSC, and MLI from CL = 25 pF to CL = 50 pF (typical)
add to parameters tRF and tFF condition CL = 50 pF
add new footnote 7) to ADC parameter table
add min and max value for QCONV and adapt typ value
add load conditions for tFF1 and tRF1
add conditions to PLL parameter tL
change DAP parameter t19 from SR to CC classification
remove footnote 2 for the FADC
adapt IDs for AB step
removed footnote 2 in table 11
change max value for ADC parameter tS from 255 to 257
switch input function ECTT1 and ECTT2
add input function REQ15 to P9.14
add alternate output O1 for OUT97 of GPTA0
changed the name for O3 from EVTO2 to EVTO1 for P0.5
changed the name for O3 from EVTO3 to EVTO2 for P0.6
changed the name for O3 from EVTO4 to EVTO3 for P0.7
add input function SLSI2 for SSC2 to P4.9
The following changes where done between Version 0.62 and 0.63 of this document:
Data Sheet
1
V 1.1, 2014-05
TC1791
History
•
•
•
•
•
•
•
•
•
•
•
•
•
•
switch input function ECTT1 and ECTT2
add input function REQ15 to P9.14
add alternate output O1 for OUT97 of GPTA0
changed the name for O3 from EVTO2 to EVTO1 for P0.5
changed the name for O3 from EVTO3 to EVTO2 for P0.6
changed the name for O3 from EVTO4 to EVTO3 for P0.7
add input function SLSI2 for SSC2 to P4.9
change for port 6.15 the symbol from CC61(CCU60) to CC60(CCU61)
change for port 8.2 the symbol from CC61(CCU60) to COUT63(CCU61)
add to all SSC signal the assosiated SSC module where is was missing in the pinning
add section Pin Reliability in Overload
incease values for absolute maximium parameters IIN and SumIIN
correct P14.8 O2 as this was incorrected label as O1
add to P4.9 output function OUT1 for LTCA2
The following changes where done between Version 0.63 and 0.7 of this document:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
update value of RTID registers in section Identification Registers for AB step
remove sentence ‘Exposure to conditions within the maximum ratings will not affect
device reliability. To replace this sentence section Pin Reliability in Overload was
added.
add footnote 1 to table 12 (Operating Conditions)
increase values for absolute maximum parameters IIN and SumIIN
remove capacitance conditions for LVDS pad parameters as loads are defined by
interface (MSC) timings
add parameter VILSD for class S pads
add VDDM supply limitation for class S parameters
add footnote 10 to table 23 (ADC parameters)
remove old footnote 2 from table 24 (FADC parameters)
remove term typical from load of Peripheral Timings
add definition of driver strength settings for ERAY Interface Timing
update formulas for frequency modulation
change SSC parameter from t59 CC to SR
change footnote 4 wording for ERAY timing back to TC1797 wording
increase flash parameters tPRD and tPRP values
increase flash parameter tERD
add section 5.2.6.1.
change in legende of table 2 definition of class S pad
correct section Extended Range Operating Conditions for the 3.3 V area
increase limit in Extended Range Operating Conditions from 1 hour to 1000 hours
specify wording for limitation of pad performance in section Extended Range
Operating Conditions
remove incorrect test conditions for RDSONx parameters
adjust typo in temperature profile
Data Sheet
2
V 1.1, 2014-05
TC1791
History
•
•
•
•
removed RDSON parameters for class F pads weak driver as only medium is
available
add parameter fSYSD for the SYSPLL
update all current values of table 28 (Power Supply Parameters)
rework the 3.3 V current part of the Power Supply Parameters for better description
and usage
– Parameters IDDP_FP, IDDFL3E and IDDFL3R are removed and replaced in the following
way
– IDDP_FP is replaced by IDDP with the condition including flash programming current
– IDDFL3E is replaced by IDDP with the condition including flash erase verify current
– IDDFL3R is replaced by IDDP with the condition including flash read current
– parameter IDDFL3R was renamed to IDDFL3
The rework of the 3.3 V current part of the Power Supply Parameters was done for
simplification and clarification. Former given values could still be used if liked, the new
definition results in the same resulting values or slightly better values. The flash module
is supplied via IDDFL3 and IDDP. For the different flash operating modes in worst case
different allocations for the two domains resulting.
The application typical case ‘flash read’ has max IDDP of 25 mA and max IDDFL3 of 98 mA
resulting is a sum of 123 mA.
The case ‘flash programming’ has max IDDP of 55 mA and max IDDFL3 of 29 mA resulting
is a sum of 84 mA.
The case ‘flash erase verify’ has max IDDP of 40 mA and max IDDFL3 of 98 mA resulting
is a sum of 138 mA.
So
for the old parameter IDDP with 35 mA, the new version reads as
IDDP = 25+IDDP_PORST = 32 mA for the same application relevant case.
The following changes where done between Version 0.7 and 1.0 of this document:
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add product options SAK-TC1791S-512F240EP, SAK-TC1791S-384F200EP, and
SAK-TC1791N-384F200EP
update block diagrams to cover new options
add note to TC1791 Logic Symbol figure and pin list for E-RAY pins availability
add identification registers for new options
adapt Absolute Maximum Rating
clarify pad supply levels in Pin Reliability in Overload section
correct errors for analog inputs in tables 12 and 13
add note at the end of Pin Reliability in Overload section
clarify wording for valid operating conditions
add negative limit for class S pad leakage
change description of parameter tCAL for the ADC
update footnote 10 for the ADC
split FADC DNL parameter into two conditions and change value for gain 4 and 8
add footnote 5 to IDDP
Data Sheet
3
V 1.1, 2014-05
TC1791
History
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improve parameters IDDFL3
add footnote for D-Flash currents in power section
rework first sentence for chapter 5.3
increase max values for parameter tB
reduce min value for tL for both PLLs
split fVCO for the system PLL into two conditions
change formula 10
add for MLI and SSC timing parameter: valid strong driver medium edge only
change MLI parameter t17 min value
update parameter description for SSC parameters t52, t53, t56, t57, t58, and t59
change SSC parameters from CC to SR Symbol for t56, t57, t58 and t59
add note to ERAY parameters for availability
add footnote to Flash parameter tERD
change for parameter NE note from Max. data retention to Min.
The following changes where done between Version 1.0 and 1.1 of this document:
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remove the following product options:
– SAK-TC1791N-384F200EL
change VILS from 2.1V to 1.9V in table 25
change t48 from 100ns to 200ns in table 40
change t49 from 100ns to 200ns in table 40
extend KOVAN conditon from IOV≤ 0 mA; IOV≥ -1 mA to IOV≤ 0 mA; IOV≥ -2 mA
change package version from PG-LFBGA-292-3 to PG-LFBGA-292-6
Data Sheet
4
V 1.1, 2014-05
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG