Composite Transistors XN01872 (XN1872) Silicon n-channel enhancement MOSFET Unit: mm 2.90+0.20 –0.05 1.9±0.1 (0.95) (0.95) 5 • Two elements incorporated into one package (Source-coupled FETs) • Reduction of the mounting area and assembly cost by one half 2 1 (0.65) 0.30+0.10 –0.05 ■ Basic Part Number 1.1+0.2 –0.1 Symbol Rating Unit Drain-source surrender voltage VDSS 50 V Gate-source voltage (Drain open) VGSO 8 V Drain curennt ID 100 mA Peak drain current IDP 200 mA Total power dissipation PT 300 mW Channel temperature Tch 150 °C Storage temperature Tstg −55 to +150 °C 0 to 0.1 ■ Absolute Maximum Ratings Ta = 25°C 1: Drain (FET1) 2: Drain (FET2) 3: Gate (FET2) EIAJ: SC-74A Symbol 4: Source 5: Gate (FET1) Mini5-G1 Package Marking Symbol: 5U Internal Connection ■ Electrical Characteristics Ta = 25°C ± 3°C Parameter 1.1+0.3 –0.1 10˚ • 2SK0621 (2SK621) × 2 Parameter 0.4±0.2 4 1.50+0.25 –0.05 3 2.8+0.2 –0.3 ■ Features 0.16+0.10 –0.06 5˚ For switching Conditions 3 4 5 FET2 FET1 2 1 Min Typ Max Unit VDSS ID = 100 µA, VGS = 0 Drain-source cutoff current IDSS VDS = 10 V, VGS = 0 10 µA Gate-source cutoff current IGSS VGS = 8 V, VDS = 0 40 80 µA 1.5 3.5 V 50 Ω Drain-source surrender voltage 50 Vth ID = 100 µA, VDS = VGS Drain-source ON resistance RDS(on) ID = 20 mA, VGS = 5 V Forward transfer admittance Yfs ID = 20 mA, VDS = 5 V, f = 1 kHz 20 VOH VDS = 5 V, VGS = 1 V, RL = 200 Ω 4.5 VOL VDS = 5 V, VGS = 5 V, RL = 200 Ω Gate threshold voltage Output voltage high-level Output voltage low-level Input resistance *1 R1+R2 V 30 mS V 100 1.0 V 200 kΩ Turn-on time *2 ton VDD = 5 V, VGS = 0 V to 5 V, RL = 200 Ω 1.0 µs Turn-off time *2 toff VDD = 5 V, VGS = 5 V to 0 V, RL = 200 Ω 1.0 µs Short-circuit forward transfer capacitance (Common-source) Ciss VDS = 5 V, VGS = 0, f = 1 MHz 15 pF 9 Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors. 2. *1: Resistance ratio R1 /R2 = 1/50 *2: Pulse measurement Note) The part number in the parenthesis shows conventional part number. Publication date: February 2004 SJJ00035BED 1 XN01872 PT Ta ID VDS 120 ID VGS 120 Ta = 25°C 200 VGS = 6.0 V 80 5.5 V 5.0 V 60 4.5 V 40 4.0 V 100 Drain current ID (mA) 300 VDS = 5 V 100 100 400 Drain current ID (mA) Total power dissipation PT (mW) 500 3.5 V 20 Ta = −25°C 80 25°C 60 75°C 40 20 3.0 V 0 40 80 120 0 160 0 0 Ambient temperature Ta (°C) 20 10 2 4 6 8 10 Short-circuit forward transfer capacitance (Common source) Ciss , Short-circuit output capacitance (Common source) Coss (pF) Forward transfer admittance Yfs (mS) 30 0 6 12 10 4 Coss 2 0 0.1 Input voltage VIN (V) 100 10 10 10 100 Output current IO (mA) SJJ00035BED 6 8 10 100 ID = 20 mA 100 80 60 Ta = 75°C 40 25°C −25°C 20 0 1 4 RDS(on) VGS 6 1 2 2 120 8 VO = 1 V Ta = 25°C 1 0 Gate-source voltage VGS (V) Ciss VIN IO 0.1 0.1 10 VGS = 0 f = 1 MHz Ta = 25°C Drain-source voltage VDS (V) Drain-source voltage VDS (V) 1 000 8 Ciss , Coss VDS VDS = 5 V Ta = 25°C 40 0 4 Drain-source voltage VDS (V) Yfs VDS 50 2 Drain-source ON resistance RDS(on) (Ω) 0 0 2 4 6 8 Gate-source voltage VGS (V) 10 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technical information described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. 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