74LVT244A-Q100; 74LVTH244A-Q100 3.3 V octal buffer/line driver; 3-state Rev. 1 — 22 April 2013 Product data sheet 1. General description The 74LVT244A-Q100; 74LVTH244A-Q100 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal buffer that is ideal for driving bus lines. The device features two output enables (1OE, 2OE), each controlling four of the 3-state outputs. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 3) Specified from 40 C to +85 C Octal bus interface 3-state buffers Output capability: +64 mA and 32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection JESD78 Class II exceeds 500 mA ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) NXP Semiconductors 74LVT244A-Q100; 74LVTH244A-Q100 3.3 V octal buffer/line driver; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVT244AD-Q100 Temperature range Name Description Version 40 C to +85 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 40 C to +85 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 40 C to +85 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm 74LVTH244AD-Q100 74LVT244APW-Q100 74LVTH244APW-Q100 74LVT244ABQ-Q100 74LVTH244ABQ-Q100 4. Functional diagram 2 4 1A0 1Y0 1A1 1Y1 1A2 1Y2 1A3 1Y3 18 16 1 6 8 1 11 13 15 17 19 12 1OE 2A0 2A1 2A2 2A3 2Y0 2Y1 2Y2 2Y3 EN 14 9 2 18 4 16 6 14 8 12 19 7 5 EN 11 9 13 7 15 5 17 3 3 mna826 2OE mna825 Fig 1. Logic symbol 74LVT_LVTH244A_Q100 Product data sheet Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 2 of 15 74LVT244A-Q100; 74LVTH244A-Q100 NXP Semiconductors 3.3 V octal buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 2( WHUPLQDO LQGH[DUHD /97$4 /97+$4 9&& /97$4 /97+$4 $ 2( < < $ $ 2( 9&& $ 2( < < < < $ $ $ $ < < < $ $ < < $ $ < < *1' $ $ < $ < *1' $ < *1' DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 3. Pin configuration for SO20 and TSSOP20 Fig 4. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE 1, 19 output enable input (active low) 1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input 2Y0, 2Y1, 2Y2, 2Y3 9, 7, 5, 3 data output GND 10 ground (0 V) 2A0, 2A1, 2A2, 2A3 11, 13, 15, 17 data input 1Y0, 1Y1, 1Y2, 1Y3, 18, 16, 14, 12 data output VCC 20 74LVT_LVTH244A_Q100 Product data sheet supply voltage All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 3 of 15 NXP Semiconductors 74LVT244A-Q100; 74LVTH244A-Q100 3.3 V octal buffer/line driver; 3-state 6. Functional description 6.1 Function table Table 3. Function table [1] Control Input Output nOE nAn nYn L H [1] L L H H X Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage [1] VO output voltage [1] IIK input clamping current IOK output clamping current IO output current Tstg storage temperature Tj junction temperature total power dissipation Ptot Conditions Min Max Unit 0.5 +4.6 V 0.5 +7.0 V 0.5 +7.0 V VI < 0 V - 50 mA VO < 0 V - 50 mA output in LOW-state - 128 mA output in HIGH-state - 64 mA 65 +150 C - 150 C 500 mW output in OFF-state or HIGH-state [2] Tamb = 40 to +85 C [3] [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] For SO20 package: above 70 C derate linearly with 8 mW/K. For TSSOP20 package: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 package: above 60 C derate linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Min Typ Max Unit VCC supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V IOH HIGH-level output current - - 32 mA 74LVT_LVTH244A_Q100 Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 4 of 15 NXP Semiconductors 74LVT244A-Q100; 74LVTH244A-Q100 3.3 V octal buffer/line driver; 3-state Table 5. Operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit IOL LOW-level output current none - - 32 mA current duty cycle 50 %; fi 1 kHz - - 64 mA in free-air 40 - +85 C - - 10 ns/V Tamb ambient temperature t/V input transition rise and fall rate outputs enabled 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Min Typ Max Unit VCC = 2.7 V; IIK = 18 mA 1.2 0.9 - V [1] VIK input clamping voltage VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V VOH HIGH-level output voltage - V - V VOL II LOW-level output voltage input leakage current VCC = 2.7 V to 3.6 V; IOH = 100 A VCC 0.2 VCC 0.1 VCC = 2.7 V to 3.6 V; IOH = 8 mA 2.4 2.5 VCC = 3.0 V; IOH = 32 mA 2.0 2.2 - V VCC = 2.7 V; IOL = 100 A - 0.1 0.2 V VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 64 mA - 0.4 0.55 V - 0.1 10 A - 0.1 1 A VCC = 3.6 V; VI = VCC - 0.1 1 A VCC = 3.6 V; VI = 0 V 5 1 A - 1 100 A 75 150 - A 150 75 A all input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND data pins IOFF power-off leakage current [2] VCC = 0 V; VI or VO = 0 V to 4.5 V [3] IBHL bus hold LOW current VCC = 3 V; VI = 0.8 V IBHH bus hold HIGH current VCC = 3 V; VI = 2.0 V IBHLO bus hold LOW overdrive current nAn input; VCC = 0 V to 3.6 V; VI = 3.6 V 500 - - A IBHHO bus hold HIGH overdrive current nAn input; VCC = 0 V to 3.6 V; VI = 3.6 V - - 500 A ILO output leakage current nYn output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V - 60 125 A IO(pu/pd) power-up/power-down output current VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care - 1 100 A 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 [4] © NXP B.V. 2013. All rights reserved. 5 of 15 NXP Semiconductors 74LVT244A-Q100; 74LVTH244A-Q100 3.3 V octal buffer/line driver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions IOZ VCC = 3.6 V; VI = VIH or VIL OFF-state output current supply current ICC Min Typ Max Unit VO = 3.0 V - 1 5 A VO = 0.5 V 5 1 A - 0.13 0.19 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A output HIGH output LOW outputs disabled - 3 12 mA [5] - 0.13 0.19 mA [6] - 0.1 0.2 mA ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input at VCC 0.6 V and other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF All typical values are at Tamb = 25 C. [1] [2] Unused pins at VCC or GND. [3] This is the bus hold overdrive current required to force the input to the opposite logic state. [4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. [5] ICC is measured with outputs pulled to VCC or GND. [6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Tamb = 40 C to +85 C tPLH tPHL tPZH tPZL Conditions Min Typ Max Unit VCC = 2.7 V - - 5.0 ns VCC = 3.0 V to 3.6 V 1 2.5 4.1 ns VCC = 2.7 V - - 5.1 ns VCC = 3.0 V to 3.6 V 1 2.6 4.1 ns [1] LOW to HIGH propagation delay HIGH to LOW propagation delay OFF-state to HIGH propagation delay nAn to nYn; see Figure 5 nAn to nYn; see Figure 5 see Figure 6 VCC = 2.7 V - - 6.3 ns VCC = 3.0 V to 3.6 V 1 3.2 5.2 ns - - 6.7 ns 1.1 3.1 5.2 ns - - 6.3 ns 1.9 3.3 5.6 ns OFF-state to LOW propagation delay see Figure 6 HIGH to OFF-state propagation delay see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHZ VCC = 2.7 V VCC = 3.0 V to 3.6 V 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 6 of 15 74LVT244A-Q100; 74LVTH244A-Q100 NXP Semiconductors 3.3 V octal buffer/line driver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Conditions tPLZ LOW to OFF-state propagation delay see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V [1] Min Typ Max Unit - - 5.6 ns 1.8 3.3 5.1 ns All typical values are at VCC = 3.3 V and Tamb = 25 C. 11. Waveforms VI nAn input VM VM GND tPLH tPHL VOH VM nYn output VM VOL mna171 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (nAn) to output (nYn) propagation delays VI nOE input VM GND tPZL tPLZ 3.0 V VM nYn output VX VOL t PZH t PHZ VOH nYn output VY VM 0V 001aae464 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. 3-state output enable and disable times Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 7 of 15 74LVT244A-Q100; 74LVTH244A-Q100 NXP Semiconductors 3.3 V octal buffer/line driver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VDD VI RL VO G DUT RT RL CL 001aai546 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 7. Table 9. Test circuit for measuring switching times Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V 10 MHz 500 ns 2.5 ns 50 pF 500 GND 6V open 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 8 of 15 74LVT244A-Q100; 74LVTH244A-Q100 NXP Semiconductors 3.3 V octal buffer/line driver; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT163-1 (SO20) 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 9 of 15 74LVT244A-Q100; 74LVTH244A-Q100 NXP Semiconductors 3.3 V octal buffer/line driver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Package outline SOT360-1 (TSSOP20) 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 10 of 15 74LVT244A-Q100; 74LVTH244A-Q100 NXP Semiconductors 3.3 V octal buffer/line driver; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 0.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT764-1 (DHVQFN20) 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 11 of 15 74LVT244A-Q100; 74LVTH244A-Q100 NXP Semiconductors 3.3 V octal buffer/line driver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS BIpolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MIL Military TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT_LVTH244A_Q100 v.1 20130422 Product data sheet - - 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 12 of 15 NXP Semiconductors 74LVT244A-Q100; 74LVTH244A-Q100 3.3 V octal buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVT_LVTH244A_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 13 of 15 NXP Semiconductors 74LVT244A-Q100; 74LVTH244A-Q100 3.3 V octal buffer/line driver; 3-state No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVT_LVTH244A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 April 2013 © NXP B.V. 2013. All rights reserved. 14 of 15 NXP Semiconductors 74LVT244A-Q100; 74LVTH244A-Q100 3.3 V octal buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 April 2013 Document identifier: 74LVT_LVTH244A_Q100