Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W7x8.46
7X8 ARRAY 46 BALLS WITH 0.40 PITCH WAFER LEVEL CHIP SCALE PACKAGE
Rev 0, 11/12
2.400
2.820±0.030
1.600
X
0.400
Y
H
PRELIMINARY
G
0.200
F
E
3.310±0.030
2.000
D
2.800
C
B
A
(4X)
0.10
1
TOP VIEW
2
3
4
5
6
7
BOTTOM VIEW
PIN 1
(A1 CORNER)
0.290
PACKAGE
OUTLINE
0.400
0.240
0.550 MAX
0.200±0.030
0.265±0.035 x 46
0.10
ZXY
0.05
Z
Z SEATING
0.05 Z PLANE
SIDE VIEW
NOTES:
3 NSMD
1.
All dimensions are in millimeters.
TYPICAL RECOMMENDED LAND PATTERN
2.
Dimension and tolerance conform to ASMEY14.5-1994,
and JESD 95-1 SPP-010.
3.
NSMD refers to non-solder mask defined pad design per
Intersil Technical Brief http://www.intersil.com/data/tb/tb451.pdf
1