Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W5x8.40A
40 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP 0.4mm PITCH)
Rev 0, 2/15
X
2.06 ± 0.030
1.600
Y
H
40x 0.265 ±0.035
G
F
2.800
E
3.26 ± 0.030
D
C
B
(4X)
0.230
A
0.10
1
PIN 1
(A1 CORNER)
TOP VIEW
2
3
4
5
0.230
0.400
BOTTOM VIEW
PACKAGE OUTLINE
0.240
0.05 Z
Z SEATING PLANE
3
0.400
0.290
2
0.265 ±0.035
0.10
0.05
ZXY
Z
4
6 NSMD
0.200 ±0.030
TYPICAL RECOMMENDED LAND PATTERN
0.500 ±0.050
SIDE VIEW
NOTES:
1. Dimensions and tolerance per ASME Y14.5 - 1994.
2. Dimension is measured at the maximum bump diameter parallel to
primary datum Z .
3. Primary datum Z and seating plane are defined by the spherical
crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
5. All dimensions are in millimeters.
6. NSMD refers to non-solder mask defined pad design per Intersil
Techbrief TB451.
1