CCD area image sensor S10747-0909 Enhanced near-infrared sensitivity by using fully-depleted CCD technology The S10747-0909 is a back-illuminated CCD area image sensor that has significantly improved near-infrared sensitivity and soft X-ray detection efficiency. This has been achieved by using a thick silicon substrate that allows the depletion layer to be thickened by applying a bias voltage. Features Applications Quantum efficiency: 70% (λ=1000 nm, Ta=25 °C) Space telescope Pixel size: 24 × 24 μm 512 × 512 pixels Low readout noise Spectral response (without window) Soft X-ray detection efficiency (Typ. Ta=25 °C) 100 (Calculated data, with AR coating) 100 90 80 Detection efficiency (%) Quantum efficiency (%) 80 70 60 Back-thinned CCD 50 40 30 S10747-0909 60 40 20 20 Back-thinned CCD S10747-0909 10 0 200 400 600 800 1000 1200 0 0.1 Wavelength (nm) 1 10 100 X-ray energy (keV) KMPDB0313EA KMPDB0317EA General ratings Parameter Pixel size Number of pixels Number of active pixels Active area Vertical clock phase Horizontal clock phase Output circuit Package Window Specification 24 (H) × 24 (V) μm 532 (H) × 520 (V) 512 (H) × 512 (V) 12.288 (H) × 12.288 (V) mm 2 phases 2 phases One-stage MOSFET source follower 24-pin ceramic DIP (refer to dimensional outline) None (temporary glass window) www.hamamatsu.com 1 CCD area image sensor S10747-0909 Structure of fully-depleted back-illuminated CCD Back-thinned CCDs the silicon substrate is only a few dozen microns thick. This means that near-infrared light is more likely to pass through the substrate (see Figure 1), thus resulting in a loss of quantum efficiency in infrared region. Thickening the silicon substrate increases the quantum efficiency in the near-infrared region but also makes the resolution worse since the generated charges diffuse into the neutral region unless a bias voltage is applied (see Figure 2). Fully-depleted back-illuminated CCDs use a thick silicon substrate that has no neutral region when a bias voltage is applied and therefore deliver high quantum efficiency in the near-infrared region while maintaining a good resolution (see Figure 3). One drawback, however, is that the dark current becomes large so that these devices must usually be cooled to about -70 °C during use. [Figure 1] Back-thinned CCD [Figure 2] When no bias voltage is applied to thick silicon [Figure 3] When a bias voltage is applied to thick silicon (fully-depleted backilluminated CCD) CCD surface CCD surface Depletion layer CCD side Charge diffusion Neutral region Depletion layer GND Photosensitive Blue light Near-infrared light surface Depletion layer GND Photosensitive Blue light Near-infrared light surface BIAS Photosensitive Blue light Near-infrared light surface KMPDC0332EA Absolute maximum ratings (Ta=-70 °C) Parameter Operating temperature Storage temperature Substrate voltage (applied bias voltage) OD voltage RD voltage ISV voltage ISH voltage IGV voltage IGH voltage SG voltage OG voltage RG voltage TG voltage Vertical clock voltage Horizontal clock voltage Symbol Topr Tstg Vss VOD VRD VISV VISH VIG1V, VIG2V VIG1H, VIG2H VSG VOG VRG VTG VP1V, VP2V VP1H, VP2H Min. -120 -200 -0.5 -25 -18 -18 -18 -15 -15 -15 -15 -15 -15 -15 -15 Typ. - Max. +50 +70 +30 +0.5 +0.5 +0.5 +0.5 +10 +10 +10 +10 +10 +10 +10 +10 Unit °C °C V V V V V V V V V V V V V Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the product within the absolute maximum ratings. 2 CCD area image sensor S10747-0909 Operating conditions (Ta=-70 °C) Parameter Output transistor drain voltage Reset drain voltage Output gate voltage Substrate voltage Vertical input source Horizontal input source Test point Vertical input gate Horizontal input gate High Vertical shift register clock voltage Low High Horizontal shift register clock voltage Low High Summing gate voltage Low High Reset gate voltage Low High Transfer gate voltage Low External load resistance Symbol VOD VRD VOG VSS VISV VISH VIG1V, VIG2V VIG1H, VIG2H VP1VH, VP2VH VP1VL, VP2VL VP1HH, VP2HH VP1HL, VP2HL VSGH VSGL VRGH VRGL VTGH VTGL RL Min. -22 -13 -6 0.5 -8 2 -8 2 -8 2 -8 2 -8 2 20 Typ. -20 -12 -5 20 VRD VRD 0 0 -7 3 -7 3 -7 3 -7 3 -7 3 22 Max. -18 -11 -4 25 3 3 -6 4 -6 4 -6 4 -6 4 -6 4 24 Unit V V V V V V V V Symbol fc CP1V, CP2V CP1H, CP2H CSG CRG CTG CTE Vout Zo P Min. 0.99995 -15 - Typ. 600 110 20 30 60 0.99999 -13 3 12 Max. 150 -11 13 Unit kHz pF pF pF pF pF V kΩ mW Max. 2.0 10 60 ±10 - Unit V V V V V V kΩ Electrical characteristics (Ta=25 °C) Parameter Signal output frequency Vertical shift register capacitance Horizontal shift register capacitance Summing gate capacitance Reset gate capacitance Transfer gate capacitance Charge transfer efficiency*1 DC output level*2 Output impedance*2 Power consumption*2 *3 *1: Charge transfer efficiency per pixel measured at half of the full well capacity *2: The values depend on the load resistance. (VOD=-20 V, load resistance=22 kΩ) *3: Power consumption of the on-chip amplifier plus load resistance Electrical and optical characteristics (Ta=-70 °C, unless otherwise noted) Parameter Saturation output voltage Vertical Full well capacity Horizontal, summing gate CCD node sensitivity*4 Dark current*5 Readout noise*6 Line binning Dynamic range*7 Area scanning Photo response non-uniformity*8 Spectral response range Ta=25 °C *4: *5: *6: *7: *8: Symbol Vsat Fw Sv DS Nr DR PRNU λ Min. 150 600 1.4 20000 5000 - Typ. Fw × Sv 200 800 1.7 1 30 26667 6666 ±3 300 to 1100 keμV/ee-/pixel/s e- rms % nm Load resistance=22 kΩ Dark current is reduced to half for every 5 to 7 °C decrease in temperature. Operating frequency=150 kHz Dynamic range = Full well capacity / Readout noise Measured at one-half of the saturation output (full well capacity) using LED light (peak emission wavelength: 560 nm) Fixed pattern noise (peak to peak) Photo response non-uniformity (PRNU) = × 100 [%] Signal 3 CCD area image sensor S10747-0909 Dark current vs. temperature (Typ.) 100000 Dark current (e-/pixel/s) 10000 1000 100 10 1 0.1 -70 -60 -50 -40 -30 -20 -10 0 10 20 Temperature (°C) KMPDB0314EA Device structure (conceptual drawing of top view) Effective pixels Effective pixels 23 21 15 19 13 14 4-dummy 22 512 signal out 512 12 5 4 3 2 12345 512 4-dummy 24 1 2 Horizontal shift register 3 4 5 8 10 9 512 signal out 4 blank pixels Horizontal shift register 8-dummy 11 V=512 H=512 4 blank pixels 4-dummy Note: When viewed from the direction of the incident light, the horizontal shift register is covered with a thick silicon layer (dead layer). However, long-wavelength light passes through the silicon dead layer and may possibly be detected by the horizontal shift register. To prevent this, provide light shield on that area as needed. KMPDC0337EB 4 CCD area image sensor S10747-0909 Timing chart Integration period (Shutter must be open) Readout period (Shutter must be closed) Tpwv 1 2 3 4..519 520←512 + 8 (dummy) P1V P2V, TG P1H P2H, SG RG OS Enlarged view Tovr Tpwh, Tpws TG P1H P2H, SG Tpwr RG OS D1 D2 D3 D18 D19 D20 D4..D12, S1..S512, D13..D17 KMPDC0338EA KMPDC0338EA P1V, P2V, TG* P1H, P2H*9 SG*9 RG TG-P1H 9 Parameter Pulse width Rise and fall times Pulse width Rise and fall times Duty ratio Pulse width Rise and fall times Duty ratio Pulse width Rise and fall times Overlap time Symbol Tpwv Tprv, Tpfv Tpwh Tprh, Tpfh Tpws Tprs, Tpfs Tpwr Tprr, Tpfr Tovr Min. 100 4000 3.3 5 3.3 5 60 5 60 Typ. 50 50 - Max. - Unit μs ns μs ns % μs ns % ns ns μs *9: Symmetrical pulses should be overlapped at 50% of maximum amplitude. 5 CCD area image sensor S10747-0909 Dimensional outline (unit: mm) 34 ± 0.34 Active area 12.288 1 2 22.4 ± 0.3 14 13 12.288 24 23 11 12 Index mark 1st pin 4.40 ± 0.44 3.90 ± 0.39 (24 ×) 0.5 2.58 ± 0.15 3.0 ± 0.1 Photosensitive surface KMPDA0256EA Pin connections Pin no. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RD OS OD OG SG P2H P1H IG2H IG1H ISH TG P2V P1V SS ISV IG2V IG1V RG Function Reset drain Output transistor source Output transistor drain Output gate Summing gate CCD horizontal register clock-2 CCD horizontal register clock-1 Test point (horizontal input gate-2) Test point (horizontal input gate-1) Test point (horizontal input source) Transfer gate CCD vertical register clock-2 CCD vertical register clock-1 Remark (standard operation) -12 V RL=22 kΩ -20 V -5 V 0V 0V Connect to RD Substrate voltage (applied bias voltage) +20 V Test point (vertical input source) Test point (vertical input gate-2) Test point (vertical input gate-1) Reset gate Connect to RD 0V 0V 6 CCD area image sensor S10747-0909 Precaution for use (Electrostatic countermeasures) Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. O Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge. O Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. O Ground the tools used to handle these sensors, such as tweezers and soldering irons. O It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. Element cooling/heating temperature incline rate Element cooling/heating temperature incline rate should be set at less than 5 K/min. Information described in this material is current as of February, 2014. Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always contact us for the delivery specification sheet to check the latest specifications. Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or a suffix "(Z)" which means developmental specifications. The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use. Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. www.hamamatsu.com HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184 U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Thorshamnsgatan 35 16440 Kista, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 China: Hamamatsu Photonics (China) Co., Ltd.: 1201 Tower B, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866 Cat. No. KMPD1117E03 Feb. 2014 DN 7