RFP25N05
Data Sheet
July 1999
25A, 50V, 0.047 Ohm, N-Channel Power
MOSFET
Ordering Information
PART NUMBER
RFP25N05
PACKAGE
TO-220AB
BRAND
2112.4
Features
• 25A, 50V
The RFP25N05 N-channel power MOSFET is manufactured
using the MegaFET process. This process which uses
feature sizes approaching those of LSI integrated circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. This transistor can be operated directly
from integrated circuits.
Formerly developmental type TA09771.
File Number
• rDS(ON) = 0.047Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
RFP25N05
NOTE: When ordering use the entire part number.
G
S
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
4-504
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFP25N05
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
RFP25N05
50
50
±20
25
Refer to Peak Current Curve
Refer to UIS Curve
72
0.48
-55 to 175
UNITS
V
V
V
A
A
300
260
oC
oC
W
W/oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
50
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS , ID = 250mA (Figure 10)
2
-
4
V
VDS = Rated BVDSS, VGS = 0V
-
-
1
µA
VDS = 0.8 x Rated BVDSS,TC = 150oC
-
-
25
µA
VGS = ±20V
-
-
±100
nA
ID = 25A, VGS = 10V (Figure 9)
-
-
0.047
Ω
VDD = 25V, ID ≈ 12.5A, RL = 2.0Ω,
VGS = 10V, RG = 10Ω
(Figure 13)
-
-
60
ns
-
14
-
ns
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
tr
-
30
-
ns
td(OFF)
-
45
-
ns
tf
-
22
-
ns
tOFF
-
-
100
ns
-
-
80
nC
-
-
45
nC
-
-
3
nC
-
1075
-
pF
-
350
-
pF
-
100
-
pF
-
-
2.083
oC/W
-
-
80
oC/W
MIN
TYP
MAX
UNITS
Fall Time
Turn-Off Time
Total Gate Charge
QG(TOT)
VGS = 0V to 20V
Gate Charge at 10V
QG(10)
VGS = 0V to 10V
Threshold Gate Charge
QG(TH)
VGS = 0V to 2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to Ambient
RθJA
VDD = 40V,
ID = 25A, RL = 1.6Ω
Ig(REF) = 0.75mA
(Figure 13)
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
(Figure 3)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
Source to Drain Diode Voltage (Note 2)
VSD
ISD = 25A
-
-
1.5
V
Reverse Recovery Time
tRR
ISD = 25A, dISD/dt = 100A/µs
-
-
125
ns
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
4-505
RFP25N05
Typical Performance Curves
30
25
1.0
ID , DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
20
15
10
5
0.2
0
25
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
175
150
50
75
100
125
150
175
TC , CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
ZθJC, NORMALIZED TRANSIENT
THERMAL IMPEDANCE
2
1
0.5
0.2
PDM
0.1
0.1
0.05
t1
t2
0.02
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TA
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t1 , RECTANGULAR PULSE DURATION (s)
200
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
ID, DRAIN CURRENT (A)
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
1ms
10ms
100ms
DC
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
4-506
100
IDM , PEAK CURRENT CAPABILITY (A)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
VGS = 20V
200
VGS = 10V
100
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
175 - TC
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFP25N05
Typical Performance Curves
(Continued)
100
70
ID , DRAIN CURRENT (A)
IAS , AVALANCHE CURRENT (A)
VGS = 20V
VGS = 8V
VGS = 10V
60
STARTING TJ = 25oC
10
STARTING TJ = 150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
50
40
VGS = 7V
30
VGS = 6V
20
VGS = 4.5V
VGS = 5V
10
0
1
0.01
0.1
1
tAV , TIME IN AVALANCHE (ms)
0
10
2
4
6
VDS , DRAIN TO SOURCE VOLTAGE (V)
8
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
70
2.5
VDD = 15V
PULSE DURATION 80µs
DUTY CYCLE = 0.5% MAX
60
FIGURE 7. SATURATION CHARACTERISTICS
-55oC
25oC
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
IDS(ON) , DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
50
175oC
40
30
20
10
0
0
2
4
6
8
2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 25A
1.5
1
0.5
0
-80
10
-40
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
200
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2
2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS
ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
1.5
1
0.5
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
4-507
ID = 250µA
1.5
1
0.5
0
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFP25N05
Typical Performance Curves
(Continued)
50
1200
CISS
800
COSS
400
CRSS
0
0
5
10
15
20
VDS , DRAIN TO SOURCE VOLTAGE (V)
10
VDD = BVDSS
VDD = BVDSS
7.5
37.5
5.0
25
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
12.5
2.5
RL = 2.0Ω
IG(REF) = 0.75mA
VGS = 10V
0
VGS , GATE TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
VDS , DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
1600
0
25
20
IG (REF)
t, TIME (µs)
IG (ACT)
80
IG (REF)
IG (ACT)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
-
VGS
VDS
IAS
VDD
VDD
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
RG
-
VDD
10%
10%
0
DUT
90%
VGS
VGS
0
FIGURE 16. SWITCHING TIME TEST CIRCUIT
4-508
10%
50%
50%
PULSE WIDTH
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
RFP25N05
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
-
VGS = 2V
DUT
0
Ig(REF)
Qg(TH)
Ig(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
4-509
FIGURE 19. GATE CHARGE WAVEFORM
RFP25N05
PSPICE Electrical Model
.SUBCKT
RFP25N05 2 1 3;
rev 8/19/94
CA 12 8 1.83e-9
CB 15 14 1.98e-9
CIN 6 8 9.7e-10
DPLCAP
5
10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
RSCL1
RSCL2
EBREAK 11 7 17 18 65.9
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
+ 51
5
51
ESG
+
IT 8 17 1
GATE
LDRAIN 2 5 1e-9
LGATE 1 9 4.92e-9
LSOURCE 3 7 4.5e-9
9
1
LGATE
20
EVTO
+ 18
6
8
ESCL
16
VTO
-
+
21
6
MOS2
DBODY
-
MOS1
CIN
8
S1A
RSOURCE
7
LSOURCE
3
SOURCE
S2A
14
13
13
8
S1B
RBREAK
15
17
18
S2B
13
RVTO
CB
CA
+
17
EBREAK
18
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
12
11
RDRAIN
8
RGATE
DBREAK
50
RIN
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 1.1e-3
RGATE 9 20 2.88
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 20.3e-3
RVTO 18 19 RVTOMOD 1
+
EGS
-
6
8
+
EDS
-
14
5
8
IT
19
VBAT
+
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.764
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/108,6))}
.MODEL DBDMOD D (IS = 2.32e-13 RS = 5.72e-3 TRS1 = 2.56e-3 TRS2 = -5.13e-6 CJO = 1.18e-9 TT = 5.62e-8)
.MODEL DBKMOD D (RS = 2.00e-1 TRS1 = 3.33e-4 TRS2 = 2.68e-6)
.MODEL DPLCAPMOD D (CJO = 6.55e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.89 KP = 15.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.04e-3 TC2 = -1.04e-6)
.MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 1.77e-5)
.MODEL RSCLMOD RES (TC1 = 2.0e-3 TC2 = 1.5e-6)
.MODEL RVTOMOD RES (TC1 = -5.35e-3 TC2 = -3.77e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.04 VOFF= -3.04)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.04 VOFF= -5.04)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.02 VOFF= 1.98)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.98 VOFF= -3.02)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
4-510
DRAIN
2
LDRAIN
RFP25N05
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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