RFP42N03L, RF1S42N03LSM
Data Sheet
42A, 30V, 0.025 Ohm, Logic Level,
N-Channel Power MOSFET
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. These transistors can be operated directly from
integrated circuits.
Ordering Information
PACKAGE
File Number
4302.2
Features
• 42A, 30V
• rDS(ON) = 0.025Ω
• Temperature Compensating PSPICE® Model
• Can be Driven Directly from CMOS, NMOS, and TTL
Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
Formerly developmental type TA49030.
PART NUMBER
July 1999
BRAND
RFP42N03L
TO-220AB
FP42N03L
RF1S42N03LSM
TO-263AB
F42N03L
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to
obtain the TO-263AB variant in tape and reel, e.g., RF1S42N03LSM9A.
G
S
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN (FLANGE)
6-267
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFP42N03L, RF1S42N03LSM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFP42N03L, RF1S42N03LSM
30
30
±10
42
Refer to Peak Current Curve
Refer to UIS Curve
90
0.606
-55 to 175
UNITS
V
V
V
A
300
260
oC
oC
W
W/oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V
30
-
-
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
1
-
2
V
VDS = Rated BVDSS, VGS = 0V
-
-
1
µA
Zero Gate Voltage Drain Current
IDSS
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC
-
-
25
µA
VGS = ±10V
-
-
±100
nA
ID = 42A, VGS = 5V (Figure 11)
-
-
0.025
Ω
VDD = 15V, ID ≈ 42A, RL = 0.357Ω,
VGS = 5V, RGS = 5Ω
(Figures 10, 18, 19)
-
-
260
ns
-
15
-
ns
tr
-
160
-
ns
td(OFF)
-
20
-
ns
tf
-
20
-
ns
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tOFF
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
Thermal Resistance Junction-to-Case
Thermal Resistance Junction-to-Ambient
VDD = 24V, ID ≈ 42A,
RL = 0.571Ω
IG(REF) = 0.6mA
(Figures 15, 20, 21)
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 14)
-
-
60
ns
-
50
60
nC
-
30
36
nC
-
1.5
1.8
nC
-
1650
-
pF
-
575
-
pF
CRSS
-
200
-
pF
RθJC
-
-
1.65
oC/W
RθJA
-
-
80
oC/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Diode Reverse Recovery Time
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = 42A
-
-
1.5
V
ISD = 42A, dISD/dt = 100A/µs
-
-
125
ns
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
6-268
RFP42N03L, RF1S42N03LSM
Typical Performance Curves
Unless Otherwise Specified
50
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
30
20
10
0
25
175
150
40
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
0.5
0.2
PDM
0.1
0.1
0.05
t1
0.02
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TC = 25oC, TJ = 175oC
100
100µs
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
10ms
100ms
DC
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
6-269
50
IDM, PEAK CURRENT CAPABILITY (A)
ID, DRAIN CURRENT (A)
500
VGS = 10V
VGS = 5V
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I
175 - TC
= I25
150
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
TC = 25oC
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFP42N03L, RF1S42N03LSM
Typical Performance Curves
Unless Otherwise Specified (Continued)
100
VGS = 10V
VGS = 5V
100
STARTING TJ = 25oC
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
200
STARTING TJ = 150oC
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
1
0.001
0.01
75
VGS = 4.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
50
VGS = 4V
VGS = 3.5V
25
VGS = 3V
1
0.1
10
tAV, TIME IN AVALANCHE (ms)
0
100
0
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
5
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
100
100
-55oC
175oC
75
25oC
50
25
ON RESISTANCE (mΩ)
VDD = 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
0
0
1.5
3.0
4.5
6.0
ID = 42A
25
ID = 2A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
350
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.0
tr
250
200
150
tf
100
td(OFF)
50
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VDD = 15V, ID = 42A, RL = 0.357Ω
300
SWITCHING TIME (ns)
5.0
3.0
3.5
4.0
4.5
VGS, GATE TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
ID = 30A
50
0
7.5
ID = 15A
75
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V, ID = 42A
1.5
1.0
0.5
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
6-270
50
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
RFP42N03L, RF1S42N03LSM
Typical Performance Curves
Unless Otherwise Specified (Continued)
2.0
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.5
1.0
0.5
0
-80
-40
0
40
80
120
1.5
1.0
0.5
0
-80
200
160
TJ, JUNCTION TEMPERATURE (oC)
VGS = 0V, f = 0.1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
C, CAPACITANCE (pF)
1500
1000
COSS
500
0
CRSS
0
5
10
15
0
40
80
120
160
200
20
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VDS , DRAIN TO SOURCE VOLTAGE (V)
2500
CISS
-40
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2000
ID = 250µA
30
5
4
24
18
VDS, DRAIN TO SOURCE VOLTAGE (V)
3
0.75 BVDSS
0.50 BVDSS
12
2
0.25 BVDSS
RL = 0.714Ω
IG(REF) = 0.6mA
VGS = 5V
6
1
0
0
I G ( REF )
20 ---------------------I G ( ACT )
25
VDD = BVDSS
VDD = BVDSS
t, TIME (µs)
I G ( REF )
80 ---------------------I G ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-271
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
RFP42N03L, RF1S42N03LSM
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(ON)
td(OFF)
VDS
tf
tr
VDS
90%
90%
RL
VGS
+
-
DUT
10%
10%
0
VDD
90%
RGS
VGS
VGS
0
50%
50%
PULSE WIDTH
10%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
VDS
RL
VDD
Qg(TOT)
VDS
VGS = 10V
VGS
+
Qg(5)
VDD
-
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
IG(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
6-272
FIGURE 21. GATE CHARGE WAVEFORMS
RFP42N03L, RF1S42N03LSM
PSPICE Electrical Model
.SUBCKT RFP42N03L 2 1 3 ;
rev 12/24/96
CA 12 8 2.55e-9
CB 15 14 2.64e-9
CIN 6 8 1.45e-9
DPLCAP
2
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 33.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.9e-9
LSOURCE 3 7 4.9e-9
RLDRAIN DRAIN
RSCL2
RSCL1
+ 51
5
51
-
EVTO
20 + 18 8
RGATE
VTO +
EBREAK
+
17
18
DBODY
-
16
21
6
9
MOS2
MOS1
RLGATE
CIN
8
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 0.14e-3
RGATE 9 20 0.89
RLDRAIN 2 5 10
RLGATE 1 9 49
RLSOURCE 3 7 49
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 10.31e-3
RVTO 18 19 RVTOMOD 1
11
RDRAIN
+
GATE
LGATE
1
DBREAK
ESCL
50
6
8
ESG
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
S1A
S1B
S2A
S2B
LDRAIN
5
10
RSOURCE
LSOURCE
7
3
RLSOURCE
S2A
S1A
12
13
8
S1B
RBREAK
15
14
13
17
18
S2B
13
CA
RVTO
CB
+
EGS
-
14
+
6
8
EDS
-
5
8
IT
19
VBAT
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.583
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/176,6))}
.MODEL DBDMOD D (IS = 3.61e-13 RS = 5.06e-3 TRS1 = 3.05e-3 TRS2 = 7.57e-6 CJO = 2.16e-9 TT = 2.18e-8)
.MODEL DBKMOD D (RS = 1.66e-1 TRS1 = -2.97e-3 TRS2 = 7.57e-6)
.MODEL DPLCAPMOD D (CJO = 0.96e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.313 KP = 53.82 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.95e-4 TC2 = -1e-7)
.MODEL RDSMOD RES (TC1 = 3.82e-3 TC2 = 1.17e-5)
.MODEL RSCLMOD RES (TC1 = 2.03e-3 TC2 = 0.45e-5)
.MODEL RVTOMOD RES (TC1 = -2.27e-3 TC2 = -5.75e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.82 VOFF= -2.82)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.82 VOFF= -4.82)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.67 VOFF= 2.33)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.33 VOFF= -2.67)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
6-273
SOURCE
RFP42N03L, RF1S42N03LSM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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6-274
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