RFK70N06 Data Sheet 70A, 60V, 0.014 Ohm, N-Channel Power MOSFET The RFK70N06 N-Channel power MOSFET is manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They are designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers and emitter switches for bipolar transistors. These transistors can be operated directly from integrated circuits. September 1998 File Number 4331.1 Features • 70A, 60V • rDS(ON) = 0.014Ω • Temperature Compensating PSPICE Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature Symbol D Formerly developmental type TA49007. Ordering Information PART NUMBER RFK70N06 PACKAGE TO-204AE G BRAND RFK70N06 S NOTE: When ordering, use the entire part number. Packaging TO-204AE DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFK70N06 Absolute Maximum Ratings TC = 25oC Unless Otherwise Specified Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL RFK70N06 60 60 70 Refer to Peak Current Curve ±20 Refer to UIS Curve 150 1.0 -55 to 175 UNITS V V A 260 oC V W W/oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 60 - - V Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2 - 4 V VDS = Rated BVDSS, VGS = 0V - - 1 µA VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC - - 25 µA VGS = ±20V - - ±100 nA ID = 70A, VGS = 10V (Figure 10) - - 0.014 Ω VDD = 30V, ID ≈ 70A, RL = 0.43Ω, VGS = 10V, RG = 2.5Ω (Figures 14, 17, 18) - - 125 ns - 12 - ns tr - 50 - ns td(OFF) - 40 - ns tf - 15 - ns tOFF - - 125 ns - 185 215 nC - 100 115 nC - 5.5 6.5 nC - 3000 - pF - 900 - pF - 300 - pF Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDD = 48V, ID ≈ 70A, RL = 0.68Ω, IG(REF) = 1.0mA (Figures 19, 20) VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) Thermal Resistance Junction to Case RθJC - - 1.0 oC/W Thermal Resistance Junction to Ambient RθJA - - 80 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Reverse Recovery Time trr MIN TYP MAX UNITS ISD = 70A TEST CONDITIONS - - 1.5 V ISD = 70A, dISD/dt = 100A/µs - - 125 ns NOTES: 2. Pulse test: pulse width ≤ 300ms, duty cycle ≤ 2%. 3. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Temperature curve (Figure 3). 2 RFK70N06 Typical Performance Curves 80 70 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 60 50 40 30 20 10 0 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 THERMAL IMPEDANCE ZθJC, NORMALIZED TRANSIENT 1 100 150 125 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 2 75 50 25 175 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-1 10-2 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 1000 TJ = MAX RATED TC = 25oC 100 100µs 1ms 10 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 100ms DC 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 3 100 IDM, PEAK CURRENT (A) ID, DRAIN CURRENT (A) 500 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TC 125 VGS = 10V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 10-5 10-4 10-3 10-2 10-1 100 t, PULSE WIDTH (s) FIGURE 5. PEAK CURRENT CAPABILITY 101 RFK70N06 Typical Performance Curves 200 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R) ln [(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 100 VGS = 8V ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 300 (Continued) STARTING TJ = 25oC STARTING TJ = 150oC VGS = 7V 160 VGS = 20V PULSE DURATION = 250µs TC = 25oC 120 VGS = 10V 80 VGS = 6V VGS = 5V 40 VGS = 4.5V 10 0.01 0 1 0.1 tAV, TIME IN AVALANCHE (ms) 10 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 7. SATURATION CHARACTERISTICS 200 50 VDD = 15V 25oC 160 175oC -55oC 120 80 40 ID = 140A ID = 70A 30 ID = 35A 20 ID = 17.5A 10 PULSE DURATION = 250µs, VDD = 15V 0 0 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 5 4 10 6 7 8 9 10 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 2 2.5 250µs PULSE TEST VGS = 10V, ID = 70A VGS = VDS, ID = 250µA 2 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE TC = 25oC 40 ON RESISTANCE (mΩ) DUTY CYCLE = 0.5% MAX PULSE DURATION = 250µs rDS(ON), DRAIN TO SOURCE IDS(ON), DRAIN TO SOURCE CURRENT (A) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 1.5 1 1.5 1 0.5 0.5 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4 200 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE RFK70N06 Typical Performance Curves (Continued) 5000 ID = 250µA 4000 C, CAPACITANCE (pF) 1.5 1 0.5 0 -80 CISS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS 3000 2000 COSS 1000 CRSS 0 -40 160 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 0 200 VDS , DRAIN TO SOURCE VOLTAGE (V) 60 10.0 VDD = BVDSS VDD = BVDSS 45 7.5 RL = 0.86Ω IG(REF) = 2.2mA VGS = 10V 30 5.0 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS 0 I G ( REF ) 20 ---------------------I G ( ACT ) t, TIME (µs) 2.5 0 I G ( REF ) 80 ---------------------I G ( ACT ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT 5 25 FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 15 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 2 RFK70N06 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) VDS td(OFF) tf tr VDS 90% 90% RL VGS + - DUT 10% 10% 0 VDD 90% RGS VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 50% 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD DUT IG(REF) VGS = 10V VGS - VGS = 2V 0 Qg(TH) IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT 6 FIGURE 20. GATE CHARGE WAVEFORMS RFK70N06 PSPICE Electrical Model .SUBCKT RFK70N06 2 1 3 ; rev 1/16/97 CA 12 8 5.56e-9 CB 15 14 5.30e-9 CIN 6 8 2.63e-9 RLDRAIN DPLCAP 10 LDRAIN DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD DBREAK - 11 6 8 ESG RLGATE GATE 1 9 - EVTO 20 + RGATE 18 8 - LGATE VTO + 21 6 RIN CIN RLSOURCE RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 4.66e-3 RLDRAIN 2 5 10 RGATE 9 20 1.21 RLGATE 1 9 114.5 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.92e-3 RLSOURCE 3 7 46 RVTO 18 19 RVTOMOD 1 RSOURCE 7 3 SOURCE LSOURCE S2A S1A 12 - MOS2 MOS1 8 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 DBODY + EBREAK 17 18 16 + LDRAIN 2 5 1e-9 LGATE 1 9 11.45e-9 LSOURCE 3 7 4.60e-9 S1A S1B S2A S2B 2 DRAIN RDRAIN EBREAK 11 7 17 18 65.18 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 5 13 8 S1B RBREAK 15 14 13 17 18 S2B 13 CA RVTO CB + EGS - 14 + 6 8 EDS - 5 8 IT 19 VBAT + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.605 .MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8) .MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5) .MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7) .MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6) .MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global ature Options; written by William J. Hepp and C. Frank Wheatley. 7 Temper- RFK70N06 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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