IRFIB5N65A, SiHFIB5N65A Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Low Gate Charge Qg Results in Simple Drive Requirement 650 RDS(on) (Ω) VGS = 10 V 0.93 Qg (Max.) (nC) 48 Qgs (nC) 12 Qgd (nC) 19 Configuration RoHS* COMPLIANT • Fully Characterized Capacitance and Avalanche Voltage and Current • Compliant to RoHS directive 2002/95/EC Single APPLICATIONS D TO-220 FULLPAK • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness Available • Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply • High Speed Power Switching G • High Voltage Isolation = 2.5 kVRMS (t = 60 s, f = 60 Hz) TYPICAL SMPS TOPOLOGIES G D S S • Single Transistor Flyback N-Channel MOSFET • Single Transistor Forward ORDERING INFORMATION Package Lead (Pb)-free SnPb TO-220 FULLPAK IRFIB5N65APbF SiHFIB5N65A-E3 IRFIB5N65A SiHFIB5N65A ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Currente TC = 25 °C VGS at 10 V Continuous Drain Current TC = 100 °C Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range for 10 s Soldering Recommendations (Peak Temperature)d Mounting Torque 6-32 or M3 screw SYMBOL LIMIT VDS VGS 650 ± 30 5.1 3.2 21 0.48 325 5.2 6 60 2.8 - 55 to + 150 300 10 1.1 ID IDM EAS IAR EAR PD dV/dt TJ, Tstg UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 24 mH, RG = 25 Ω, IAS = 5.2 A (see fig. 12). c. ISD ≤ 5.2 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. Drain current limited by maximum junction temperature. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91174 S09-0518-Rev. B, 13-Apr-09 www.vishay.com 1 IRFIB5N65A, SiHFIB5N65A Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 2.1 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS VDS VGS = 0 V, ID = 250 µA MIN. TYP. MAX. UNIT 650 - - V - 670 - mV/°C 2.0 - 4.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance ΔVDS/TJ VGS(th) Reference to 25 °C, ID = 1 VDS = VGS, ID = 250 µA IGSS IDSS RDS(on) gfs mAd VGS = ± 30 V - - ± 100 VDS = 650 V, VGS = 0 V - - 25 VDS = 520 V, VGS = 0 V, TJ = 125 °C - - 250 - - 0.93 Ω VDS = 50 V, ID = 3.1 A 3.9 - - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 1417 - - 177 - - 7.0 - VDS = 1.0 V, f = 1.0 MHz - 1912 - VDS = 520 V, f = 1.0 MHz - 48 - - 84 - - - 48 - - 12 - - 19 - 14 - - 20 - - 34 - - 18 - - - 5.2 - - 21 ID = 3.1 Ab VGS = 10 V µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Output Capacitance Coss Effective Output Capacitance Coss eff. Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time VGS = 0 V tr td(off) VDS = 0 V to 520 VGS = 10 V Vc ID = 5.2 A, VDS = 400 V see fig. 6 and 13b VDD = 325 V, ID = 5.2 A RG = 9.1 Ω, RD = 62 Ω, see fig. 10b tf pF nC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 5.2 A, VGS = 0 S Vb TJ = 25 °C, IF = 5.2 A, dI/dt = 100 A/µsb - - 1.5 V - 493 739 ns - 2.1 3.2 µC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS. d. t = 60 s, f = 60 Hz. www.vishay.com 2 Document Number: 91174 S09-0518-Rev. B, 13-Apr-09 IRFIB5N65A, SiHFIB5N65A Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 100 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP 10 1 20µs PULSE WIDTH 4.5V TJ = 25 °C 0.1 0.1 1 10 10 TJ = 150 ° C TJ = 25 ° C 1 0.1 4.0 100 Fig. 1 - Typical Output Characteristics I D , Drain-to-Source Current (A) 10 4.5V 1 20µs PULSE WIDTH TJ = 150 ° C 10 VDS , Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics Document Number: 91174 S09-0518-Rev. B, 13-Apr-09 100 RDS(on) , Drain-to-Source On Resistance (Normalized) 3.0 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 1 6.0 7.0 8.0 9.0 Fig. 3 - Typical Transfer Characteristics TOP 0.1 5.0 VGS , Gate-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) 100 V DS = 100V 20µs PULSE WIDTH ID = 5.2A 2.5 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 TJ , Junction Temperature ( °C) Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 IRFIB5N65A, SiHFIB5N65A Vishay Siliconix 2000 ISD , Reverse Drain Current (A) 1600 C, Capacitance (pF) 100 V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd iss 1200 oss 800 400 rss 0 10 100 TJ = 150 ° C 1 TJ = 25 ° C 0.1 0.2 A 1 10 1000 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 0.8 1.0 1.2 Fig. 7 - Typical Source-Drain Diode Forward Voltage 100 ID = 5.2A OPERATION IN THIS AREA LIMITED BY RDS(on) VDS = 520V VDS = 325V VDS = 130V 16 10us ID , Drain Current (A) VGS , Gate-to-Source Voltage (V) 0.6 VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) 20 V GS = 0 V 0.4 12 8 10 100us 1ms 1 10ms 4 FOR TEST CIRCUIT SEE FIGURE 13 0 0 10 20 30 40 50 0.1 TC = 25 ° C TJ = 150 ° C Single Pulse 10 100 1000 QG , Total Gate Charge (nC) VDS , Drain-to-Source Voltage (V) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area www.vishay.com 4 10000 Document Number: 91174 S09-0518-Rev. B, 13-Apr-09 IRFIB5N65A, SiHFIB5N65A Vishay Siliconix RD VDS 6.0 VGS D.U.T. RG 5.0 + ID , Drain Current (A) - VDD 4.0 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 3.0 Fig. 10a - Switching Time Test Circuit 2.0 VDS 90 % 1.0 0.0 25 50 75 100 125 150 10 % VGS TC , Case Temperature ( ° C) t d(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr t d(off) t f Fig. 10b - Switching Time Waveforms Thermal Response (Z thJC ) 10 D = 0.50 1 0.20 0.10 PDM 0.05 0.1 t1 0.02 t2 0.01 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC SINGLE PULSE (THERMAL RESPONSE) 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t1 , Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case V DS tp 15 V L VDS D.U.T. RG IAS 20 V tp Driver + A - VDD 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91174 S09-0518-Rev. B, 13-Apr-09 A I AS Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 IRFIB5N65A, SiHFIB5N65A EAS , Single Pulse Avalanche Energy (mJ) Vishay Siliconix 800 TOP BOTTOM ID 2.3A 3.3A 5.2A QG 600 10 V QGS 400 Q GD VG Charge 200 Fig. 13a - Basic Gate Charge Waveform 0 25 50 75 100 125 150 Starting TJ , Junction Temperature ( °C) Current regulator Same type as D.U.T. Fig. 12c - Maximum Avalanche Energy vs. Drain Current 50 kΩ 12 V 0.2 µF 0.3 µF 800 + V DSav , Avalanche Voltage (V) D.U.T. 780 - VDS VGS 3 mA 760 IG ID Current sampling resistors Fig. 13b - Gate Charge Test Circuit 740 720 700 A 0 1 2 3 4 5 6 I av , Avalanche Current (A) Fig. 12d - Typical Drain-to Source Voltage vs. Avalanche Current www.vishay.com 6 Document Number: 91174 S09-0518-Rev. B, 13-Apr-09 IRFIB5N65A, SiHFIB5N65A Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - • • • • RG dV/dt controlled by R G Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor crurent Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91174. Document Number: 91174 S09-0518-Rev. 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