IRFIB7N50A, SiHFIB7N50A Datasheet

IRFIB7N50A, SiHFIB7N50A
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
500
RDS(on) (Ω)
VGS = 10 V
0.52
Qg (Max.) (nC)
52
Qgs (nC)
13
Qgd (nC)
18
Configuration
Single
Available
RoHS*
COMPLIANT
APPLICATIONS
D
TO-220 FULLPAK
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully
Characterized
Capacitance
and
Avalanche Voltage and Current
• Effective Coss Specified
• Compliant to RoHS directive 2002/95/EC
•
•
•
•
G
Switch Mode Power Supply (SMPS)
Uninterruptible Power Supply
High Speed Power Switching
High Voltage Isolation = 2.5 kVRMS (t = 60 s, f = 60 Hz)
TYPICAL SMPS TOPOLOGIES
G D S
S
N-Channel MOSFET
• Two Transistor Forward
• Half and Full Bridge Convertors
• Power Factor Correction Boost
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
TO-220 FULLPAK
IRFIB7N50APbF
SiHFIB7N50A-E3
IRFIB7N50A
SiHFIB7N50A
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Currentf
TC = 25 °C
VGS at 10 V
Continuous Drain Current
TC = 100 °C
Pulsed Drain Currenta, e
Linear Derating Factor
Single Pulse Avalanche Energyb, e
Repetitive Avalanche Currenta, e
Repetitive Avalanche Energya
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc, e
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
Mounting Torque
6-32 or M3 screw
SYMBOL
LIMIT
VDS
VGS
500
± 30
6.6
4.2
44
0.48
275
11
6.0
60
6.9
- 55 to + 150
300d
10
1.1
ID
IDM
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 4.5 mH, RG = 25 Ω, IAS = 11 A (see fig. 12).
c. ISD ≤ 11 A, dI/dt ≤ 140 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. Uses IRFB11N50A, SiHFB11N50A data and test conditions.
f. Drain current limited by maximum junction temperature.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91176
S09-0517-Rev. B, 13-Apr-09
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1
IRFIB7N50A, SiHFIB7N50A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
2.1
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mAd
-
610
-
mV/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
-
-
0.52
Ω
6.1
-
-
S
-
1423
-
-
208
-
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 4.0 Ab
VGS = 10 V
VDS = 50 V, ID = 6.6
Ad
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Total Gate Charge
Coss
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Fall Time
-
8.1
-
VDS = 1.0 V, f = 1.0 MHz
-
2000
-
VDS = 400 V, f = 1.0 MHz
-
55
-
VDS = 0 V to 400 Vc, d
-
97
-
-
-
52
-
-
13
-
-
18
-
14
-
-
35
-
-
32
-
-
28
-
-
-
6.6
-
-
44
Qg
Qgs
Rise Time
VGS = 0 V
Coss eff.
Gate-Source Charge
Turn-Off Delay Time
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5 d
tr
td(off)
VGS = 10 V
ID = 11 A, VDS = 400 V
see fig. 6 and 13b, d
VDD = 250 V, ID = 11 A
RG = 9.1 Ω, RD = 22 Ω,
see fig. 10b, d
tf
pF
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 11 A, VGS = 0 Vb
TJ = 25 °C, IF = 11 A, dI/dt = 100 A/µsb, d
-
-
1.5
V
-
510
770
ns
-
3.4
5.1
µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
d. Uses IRFB11N50A, SiHFB11N50A data and test conditions.
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Document Number: 91176
S09-0517-Rev. B, 13-Apr-09
IRFIB7N50A, SiHFIB7N50A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
10
1
4.5V 20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
10
TJ = 150 ° C
TJ = 25 ° C
1
0.1
4.0
100
VDS , Drain-to-Source Voltage (V)
I D , Drain-to-Source Current (A)
10
20µs PULSE WIDTH
TJ = 150 ° C
1
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91176
S09-0517-Rev. B, 13-Apr-09
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.5V
6.0
7.0
8.0
9.0
Fig. 3 - Typical Transfer Characteristics
TOP
1
5.0
VGS , Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
100
V DS = 100V
20µs PULSE WIDTH
ID = 11A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFIB7N50A, SiHFIB7N50A
Vishay Siliconix
2400
ISD , Reverse Drain Current (A)
2000
C, Capacitance (pF)
100
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
Ciss
1600
Coss
1200
800
Crss
400
0
10
TJ = 150° C
1
TJ = 25 ° C
0.1
0.0
A
1
10
100
1000
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS = 400 V
VDS = 250 V
VDS = 100 V
16
100
12
8
10us
10
100us
1ms
1
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
10
20
30
40
50
QG , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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1.6
1000
A
ID = 11
6.6A
0
1.2
Fig. 7 - Typical Source-Drain Diode Forward Voltage
I D , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
0.8
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
20
V GS = 0 V
0.4
0.1
10ms
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91176
S09-0517-Rev. B, 13-Apr-09
IRFIB7N50A, SiHFIB7N50A
Vishay Siliconix
7.0
RD
VDS
VGS
6.0
D.U.T.
ID , Drain Current (A)
RG
+
- VDD
5.0
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
4.0
3.0
Fig. 10a - Switching Time Test Circuit
2.0
VDS
90 %
1.0
0.0
25
50
75
100
125
150
TC , Case Temperature ( °C)
10 %
VGS
t d(on)
tr
t d(off) t f
Fig. 10b - Switching Time Waveforms
Fig. 9 - Maximum Drain Current vs. Case Temperature
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
P DM
0.05
0.1
t1
0.02
t2
0.01
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
V DS
tp
15 V
L
VDS
D.U.T.
RG
IAS
20 V
tp
Driver
+
A
- VDD
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91176
S09-0517-Rev. B, 13-Apr-09
A
I AS
Fig. 12b - Unclamped Inductive Waveforms
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IRFIB7N50A, SiHFIB7N50A
EAS , Single Pulse Avalanche Energy (mJ)
Vishay Siliconix
600
TOP
500
BOTTOM
ID
4.9A
7.0A
11A
QG
10 V
400
QGS
300
Q GD
VG
200
Charge
100
Fig. 13a - Basic Gate Charge Waveform
0
25
50
75
100
125
150
Current regulator
Same type as D.U.T.
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
50 kΩ
12 V
V DSav , Avalanche Voltage (V)
660
0.2 µF
0.3 µF
D.U.T.
+
V
- DS
640
VGS
3 mA
620
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
600
580
0.0
A
1.0
2.0
3.0
4.0
5.0
6.0
7.0
I av , Avalanche Current (A)
Fig. 12d -Typical Drain-to-Source Voltage vs. Avalanche
Current
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Document Number: 91176
S09-0517-Rev. B, 13-Apr-09
IRFIB7N50A, SiHFIB7N50A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T .
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by R G
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Body diode
VDD
forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91176.
Document Number: 91176
S09-0517-Rev. B, 13-Apr-09
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Revision: 02-Oct-12
1
Document Number: 91000