95751

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R079-98
98-04-06
Raymond L. Monnin
B
Update boilerplate to MIL-PRF-38535 and updated appendix A. Editorial
changes throughout. - tmh
00-10-05
Monica L. Poelking
C
Correct title to more accurately describe the function. Update the radiation
features in section 1.5 and paragraphs 4.4.41, 4.4.4.4 and 4.4.4.3. Update the
boilerplate paragraphs to current requirements as specified in
MIL-PRF-38535. - jak
09-09-02
Thomas M. Hess
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PMIC N/A
PREPARED BY
Rick C. Officer
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Thanh V. Nguyen
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Monica L. Poelking
DRAWING APPROVAL DATE
95-11-03
AMSC N/A
REVISION LEVEL
C
MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS,
RADIATION HARDENED, NON-INVERTING
OCTAL BUFFER/LINE DRIVER WITH THREESTATE OUTPUTS, TTL COMPATIBLE INPUTS,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-95751
22
5962-E399-09
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962



Federal
stock class
designator
\
R



RHA
designator
(see 1.2.1)
95751
01



Device
type
(see 1.2.2)
V



Device
class
designator
(see 1.2.3)
/
X



Case
outline
(see 1.2.4)
C



Lead
finish
(see 1.2.5)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
Circuit function
HCTS541
Radiation hardened, SOS, high speed CMOS,
non-inverting octal buffer/line driver with
three-state outputs, TTL compatible inputs
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device requirements documentation
Device class
M
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
R
X
Descriptive designator
CDIP2-T20
CDFP4-F20
Terminals
Package style
20
20
Dual-in-line package
Flat package
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
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REVISION LEVEL
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1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VCC) .................................................................................. -0.5 V dc to +7.0 V dc
DC input voltage range (VIN) ................................................................................ -0.5 V dc to VCC + 0.5 V dc
DC output voltage range (VOUT) ........................................................................... -0.5 V dc to VCC + 0.5 V dc
DC input current, any one input (IIN)..................................................................... ±10 mA
DC output current, any one output (IOUT) ............................................................. ±25 mA
Storage temperature range (TSTG) ....................................................................... -65°C to +150°C
Lead temperature (soldering, 10 seconds) .......................................................... +265°C
Thermal resistance, junction-to-case (JC):
Case outline R ................................................................................................... 24°C/W
Case outline X ................................................................................................... 28°C/W
Thermal resistance, junction-to-ambient (JA):
Case outline R ................................................................................................... 72°C/W
Case outline X ................................................................................................... 107°C/W
Junction temperature (TJ) .................................................................................... +175°C
Maximum package power dissipation at TA = +125°C (PD): 4/
Case outline R ................................................................................................... 0.69 W
Case outline X ................................................................................................... 0.47 W
1.4 Recommended operating conditions. 2/ 3/
Supply voltage range (VCC) .................................................................................. +4.5 V dc to +5.5 V dc
Input voltage range (VIN) ...................................................................................... +0.0 V dc to VCC
Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC
Maximum low level input voltage (VIL).................................................................. 0.8 V
Minimum high level input voltage (VIH) ................................................................. VCC/2
Case operating temperature range (TC) ............................................................... -55°C to +125°C
Maximum input rise or fall time at VCC = 4.5 V (tr, tf) ............................................ 500 ns
1.5 Radiation features.
Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) ..................... > 2 x 105 Rads (Si)
Single event phenomenon (SEP) effective
linear energy threshold (LET), no upsets (see 4.4.4.4) .................................. > 100 MeV/(cm2/mg) 5/
Dose rate upset (20 ns pulse) .......................................................................... > 1 x 1010 Rads (Si)/s 5/
Latch-up ........................................................................................................... None 5/
Dose rate survivability ...................................................................................... > 1 x 1012 Rads (Si)/s 5/
1/
2/
3/
4/
5/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Unless otherwise specified, all voltages are referenced to GND.
The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of
-55°C to +125°C unless otherwise noted.
If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is
based on JA) at the following rate:
Case R .......................................................................................................................... 13.9 mW/°C
Case X .......................................................................................................................... 9.3 mW/°C
Guaranteed by design or process but not tested.
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REVISION LEVEL
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2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those
cited in the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM F1192
-
Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of semiconductor Devices.
(Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive,
P.O. Box C700, West Conshohocken, PA, 19428-2959).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
3.2.5 Switching waveform and test circuit. The switching waveforms and test circuits shall be as specified on figure 4.
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3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in
MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to
this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 37 (see MIL-PRF-38535, appendix A).
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TABLE I. Electrical performance characteristics.
Test
Symbol
High level output
voltage
Low level output
voltage
Input current high
VOH
VOL
IIH
Test conditions 1/ 2/
-55C  TC  +125C
unless otherwise specified
IIL
For all inputs affecting
output under test
VIH = 2.25 V or VIL = 0.8 V
For all other inputs
VIN = VCC or GND
IOH = -50 A
All
4.5 V
1, 2, 3
4.40
For all inputs affecting
output under test
VIH = 2.75 V or VIL = 0.8 V
For all other inputs
VIN = VCC or GND
IOH = -50 A
All
5.5 V
1, 2, 3
5.40
For all inputs affecting
output under test
VIH = 2.25 V or VIL = 0.8 V
For all other inputs
VIN = VCC or GND
IOL = 50 A
All
4.5 V
1, 2, 3
0.1
For all inputs affecting
output under test
VIH = 2.75 V or VIL = 0.8 V
For all other inputs
VIN = VCC or GND
IOL = 50 A
All
5.5 V
1, 2, 3
0.1
For input under test, VIN = 5.5 V
For all other inputs
VIN = VCC or GND
All
5.5 V
1
+0.5
2, 3
+5.0
1
+5.0
1
-0.5
2, 3
-5.0
1
-5.0
All
All
For input under test, VIN = GND
For all other inputs
VIN = VCC or GND
M, D, P, L, R
2/
Output current high
(Source)
IOH
Limits 3/
VCC
M, D, P, L, R
2/
Input current low
Group A
subgroups
Device
type
5.5 V
All
For all inputs affecting output
under test, VIN = 4.5 V or 0.0 V
For all other inputs
VIN = VCC or GND
VOUT = 4.1 V
All
4.5 V
1
-7.2
2, 3
-6.0
1
-6.0
All
M, D, P, L, R
2/
Min
Unit
Max
V
V
A
A
mA
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Output current low
(Sink)
IOL
Test conditions 1/ 2/
-55C  TC  +125C
unless otherwise specified
Device
type
VCC
All
4.5 V
For all inputs affecting output
under test, VIN = 4.5 V or 0.0 V
For all other inputs
VIN = VCC or GND
VOUT = 0.4 V
ICC
4/
For inputs under test
VIN = VCC - 2.1 V
For all other inputs
VIN = VCC or GND
All
IOZH
OEm = 5.5 V
For all other inputs
VIN = 0.0 V or 5.5 V
VOUT = 5.5 V
Three-state output
leakage current
low
IOZL
ICC
All
CIN
Power dissipation
capacitance
CPD
5/
Functional test
Propagation delay
time, data to
output
6/
tPHL,
tPLH
VIN = VCC or GND
All
1
+6.0
1
1.6
1
1.0
2, 3
50.0
1
50.0
1
-1.0
2, 3
-50.0
1
-50.0
1
40.0
2, 3
750
1
750
5.5 V
5.5 V
A
4
10
pF
All
5.0 V
4
38
pF
5, 6
60
All
All
All
4.5 V
7, 8
L
H
7
L
H
9
2.0
20.0
10, 11
2.0
22.0
9
2.0
22.0
4.5 V
All
M, D, P, L, R
2/
A
5.0 V
VIH = 2.25 V, VIL = 0.80 V
CL = 50 pF
RL = 500
See figure 4
mA
All
See 4.4.1b
M, D, P, L, R
2/
mA
1.6
5.5 V
Unit
Max
1, 2, 3
All
VIH = 5.0 V, VIL = 0.0 V
f = 1 MHz, see 4.4.1c
7/
+6.0
All
M, D, P, L, R
2/
M, D, P, L, R
2/
Input capacitance
2, 3
All
M, D, P, L, R
2/
OEm = 5.5 V
For all other inputs
VIN = 0.0 V or 5.5 V
VOUT = 0.0 V
Quiescent supply
current
All
Min
+7.2
All
M, D, P, L, R
2/
Three-state output
leakage current
high
5.5 V
Limits 3/
1
All
M, D, P, L, R
2/
Quiescent supply
current delta,
TTL input levels
Group A
subgroups
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
Propagation delay
time, output
enable, OEm to Yn
Symbol
tPZL
7/
Test conditions 1/ 2/
-55C  TC  +125C
unless otherwise specified
Device
type
VCC
All
4.5 V
CL = 50 pF
RL = 500
See figure 4
7/
CL = 50 pF,
RL = 500,
See figure 4
All
Propagation delay
time, output
disable, OEm to Yn
tPLZ
7/
CL = 50 pF,
RL = 500,
See figure 4
7/
tTHL,
tTLH
8/
2.0
23.0
10, 11
2.0
26.0
9
2.0
26.0
9
2.0
20.0
10, 11
2.0
21.0
9
2.0
21.0
9
2.0
22.0
10, 11
2.0
23.0
9
2.0
23.0
9
2.0
21.0
10, 11
2.0
22.0
9
2.0
22.0
4.5
All
CL = 50 pF,
RL = 500,
See figure 4
All
4.5
All
M, D, P, L, R
2/
Output transition
time
9
4.5
All
M, D, P, L, R
2/
tPHZ
Max
All
M, D, P, L, R
2/
CL = 50 pF,
RL = 500,
See figure 4
All
Limits 3/
Min
All
M, D, P, L, R
2/
tPZH
Group A
subgroups
4.5 V
9
12.0
10, 11
18.0
Unit
ns
ns
ns
ns
1/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Output terminals not designated shall be high level logic, low level logic, or open, except for the ICC and ICC tests, the
output terminals shall be open. When performing the ICC and ICC tests, the current meter shall be placed in the circuit such
that all current flows through the meter.
2/ Devices supplied to this drawing meet all levels M, D, P, L, and R of irradiation. However, this device is only tested at the "R"
level. Pre and post irradiation values are identical unless otherwise specified in table I. When performing post irradiation
electrical measurements for any RHA level, TA = +25C.
3/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
the direction of current flow respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein.
4/ This parameter is guaranteed, if not tested, to the limits specified in table I herein.
5/ Power dissipation capacitance (CPD) determines both the power consumption (PD) and current consumption (IS).
Where:
PD = (CPD + CL) (VCC x VCC)f + (ICC x VCC) + (n x d x ICC x VCC)
IS = (CPD + CL) VCCf + ICC + (n x d x ICC)
f is the frequency of the input signal; n is the number of device inputs at TTL levels; and d is the duty cycle of the input
signal.
6/ The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible
input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. For VOUT
measurements, L  0.5 V and H  4.0 V.
7/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V. For propagation delay tests, all paths must be tested.
8/ This parameter is guaranteed but not tested. This parameter is characterized upon initial design or process changes which
affect this characteristic.
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Device type
01
Case outlines
R and X
Terminal number
Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
FIGURE 1. Terminal connections.
Inputs
Outputs
OE1
OE2
An
Yn
L
L
H
H
H
X
X
Z
X
H
X
Z
L
L
L
L
H = High voltage level
L = Low voltage level
X = Don't care
Z = High impedance
FIGURE 2. Truth table.
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FIGURE 3. Logic diagram.
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NOTES:
1. When measuring tPLZ and tPZL, S1 is closed and S2 is open.
2. When measuring tPLH, tPHL, tPHZ, and tPZH, S1 is open and S2 is closed.
3. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance).
4. RL = 500 or equivalent.
5. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR  10 MHz; tr  3.0 ns; tf  3.0 ns; tr and tf shall be measured
from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively.
FIGURE 4. Switching waveforms and test circuit.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015.
(2) TA = +125C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of
MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in
accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be
those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
c.
Subgroup 4, 5 and 6 (CIN and CPD measurement) shall be measured only for the initial qualification and after process
or design changes which may affect capacitance. CIN shall be measured between the designated terminal and GND at
a frequency of 1 MHz. For CIN and CPD the tests shall be sufficient to validate the limits defined in table I herein.
STANDARD
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TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M
Device
class Q
Device
class V
Interim electrical
parameters (see 4.2)
1, 7, 9
Final electrical
parameters (see 4.2)
1/ 1, 2, 3, 7, 8, 9, 10,
11
1/ 1, 2, 3, 7,
8, 9, 10, 11
2/ 3/ 1, 2, 3, 7,
8, 9, 10, 11
Group A test
requirements (see 4.4)
1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11
1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11
1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 3, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9,
10, 11
3/ 1, 2, 3, 7, 8,
9, 10, 11
Group D end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
Group E end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1/ PDA applies to subgroup 1 and 7.
2/ PDA applies to subgroups 1, 7, 9 and deltas.
3/ Delta limits as specified in table IIB shall be required where specified, and the delta limits shall be completed
with reference to the zero hour electrical parameters (see Table I)
TABLE IIB. Burn-in and operating life test, Delta parameters (+25°C).
Parameters 1/
Delta limits
ICC
+12.0 A
IOL/IOH
-15%
IOZL/IOZH
200 nA
1/ These parameters shall be recorded before and after the required burn-in
and life test to determine delta limits.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
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4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-PRF-38535. End-point electrical
parameters shall be as specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019,condition A and as specified herein.
4.4.4.1.1 Accelerated annealing testing. Accelerated annealing testing shall be performed on all devices requiring a RHA
level greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and
shall be the pre-irradiation end-point electrical parameter limits at 25C 5C. Testing shall be performed at initial qualification
and after any design or process changes which may affect the RHA response of the device.
4.4.4.2 Dose rate induced latch-up testing. When required by the customer, dose rate induced latch-up testing shall be
performed in accordance with method 1020 of MIL-STD-883 and as specified herein. Tests shall be performed on devices,
SEC, or approved test structures at technology qualification and after any design or process changes which may affect the RHA
capability of the process.
4.4.4.3 Dose rate upset testing. When required by the customer, dose rate upset testing shall be performed in accordance
with method 1021 of MIL-STD-883 and herein.
a. Transient dose rate upset testing for class M devices shall be performed at initial qualification and after any design or
process changes which may affect the RHA performance of the devices. Test 10 devices with 0 defects unless
otherwise specified.
b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535. Device parametric parameters that influence upset immunity
shall be monitored at the wafer level in accordance with the wafer level hardness assurance plan and MIL-PRF-38535.
4.4.4.4 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The test conditions for SEP are as follows:
a.
The ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive
(i.e. 0  angle  60). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b.
The fluence shall be  100 errors or ≥ 107 ions/cm2.
c.
The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d.
The particle range shall be  20 microns in silicon.
e. The upset test temperature shall be +25C. The latchup test temperature shall be at the maximum rated operating
temperature 10C for the latchup measurements.
f.
Bias conditions shall be defined by the manufacturer for latchup measurements.
g.
For SEP test limits, see table IB herein.
4.5 Methods of inspection. Methods of inspection shall be as specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
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5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. A copy of the following additional data shall be maintained and available from the device
manufacturer:
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
STANDARD
MICROCIRCUIT DRAWING
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95751
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number
(PIN). When available a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
A.1.2 PIN. The PIN shall be as shown in the following example:
5962
R
Federal
Stock class
designator
95751
RHA
designator
(see A.1.2.1)
01
V
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
Details
(see A.1.2.4)
Drawing Number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels.
A dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
Generic number
01
Circuit function
HCTS541
Radiation hardened, SOS,
high speed CMOS, noninverting octal buffer/line
driver with three-state
outputs, TTL compatible
inputs.
A.1.2.3 Device class designator.
Device class
Q or V
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95751
A.1.2.4 Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.4.1 Die Physical dimensions.
Die Types
Figure number
01
A-1
A.1.2.4.2 Die Bonding pad locations and Electrical functions.
Die Types
Figure number
01
A-1
A.1.2.4.3 Interface Materials.
Die Types
Figure number
01
A-1
A.1.2.4.4 Assembly related information.
Die Types
Figure number
01
A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 within the body of this drawing for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 within the body of this drawing for details.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95751
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specifications, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
-
Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103
MIL-HDBK-780
-
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence.
A.3 REQUIREMENTS
A.3.1 Item Requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not effect the form, fit or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as
specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
A.3.2.1 Die Physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be
as specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and figure A-1.
A.3.2.5 Truth table. The truth table shall be as defined within paragraph 3.2.3 of the body of this document.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined within paragraph 3.2.6 of the body of
this document.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95751
A.3.3 Electrical performance characteristics and post- irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table I.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN
listed in A.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not effect the form, fit or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum it shall consist of:
a) Wafer Lot acceptance for Class V product using the criteria defined within MIL-STD-883 TM 5007.
b) 100% wafer probe (see paragraph A.3.4).
c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 TM2010
or the alternate procedures allowed within MIL-STD-883 TM5004.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95751
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
30.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified within paragraphs 4.4.4.1,
4.4.4.1.1, 4.4.4.2, 4.4.4.3, and 4.4.4.4.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be in accordance with the manufacturer’s QM plan
or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43218-3990 or telephone
(614)-692-0547.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined with
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of Supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and
have agreed to this drawing.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95751
o DIE PHYSICAL DIMENSIONS
Die Size:
Die Thickness:
2160 x 2570 microns.
21 +/- 2 mils.
The following metallization diagram supplies the locations and electrical functions of the bonding pads. The internal
metallization layout and alphanumeric information contained within this diagram may or may not represent the actual circuit
defined by this SMD.
NOTE: Pad numbers reflect terminal numbers when placed in Case Outlines R, X (see Figure 1).
FIGURE A-1. Die bonding pad locations and electrical functions.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95751
o INTERFACE MATERIALS
Top Metallization:
SiAl
11.0kÅ +/- 1kÅ
Backside Metallization
None
Glassivation
Type:
Thickness
SiO2
13.0kÅ +/- 2.6kÅ
Substrate:
Silicon on Sapphire (SOS)
o ASSEMBLY RELATED INFORMATION
Substrate Potential:
Insulator
Special assembly
instructions:
Bond pad #20 (VCC) first.
FIGURE A-1. Die bonding pad locations and electrical functions - Continued.
STANDARD
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STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 09-09-02
Approved sources of supply for SMD 5962-95751 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962R9575101VRC
34371
HCTS541DMSR
5962R9575101VXC
34371
HCTS541KMSR
5962R9575101V9A
34371
HCTS541HMSR
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
1001 Murphy Ranch Road
Milpitas, CA 95035-6803
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.