® RT8240A/B/C High Efficiency Single Synchronous Buck PWM Controller General Description Features The RT8240A/B/C PWM controller provides high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers. z Built-in 0.5% Reference Voltage z 1 Bit Programmable Output Voltage Between 1V and 1.05V with Integrated Transition Support Output Voltage Range from 1V to 3.6V Quick Load-Step Response within 100ns Support Pure MLCC Output Capacitor 4700ppm/°°C Programmable Current Limit by Low Side RDS(ON) Sensing 4.5V to 26V Battery Input Range Internal Ramp Current Limit Soft-Start Control Drives Large Synchronous Rectifier FETs Integrated Boost Switch Over/Under Voltage Protection Thermal Shutdown Power Good Indicator RoHS Compliant and Halogen Free The RT8240A/B/C supports on chip voltage programming function between 1V and 1.05V by controlling G0 digital inputs. z z z z z The constant on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. The RT8240A/B/C achieves high efficiency at a reduced cost by eliminating the current sense resistor found in traditional current mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs and enter diode emulation mode at light load condition. The buck conversion allows this device to directly step down high voltage batteries at the highest possible efficiency. The RT8240A/B/C is intended for CPU core, chipset, DRAM, or other low voltage supplies as low as 1V. The RT8240A/B/C is available in a WQFN -12L 2x2 package. z z z z z z z Applications z z z z Notebook Computers CPU/GPU Core Supply Chipset/RAM Supply Generic DC/DC Power Regulator Pin Configurations Note : PHASE UGATE 2 CS 10 GND 13 3 4 5 6 VOUT Switching Frequency Operation A : 300kHz B : 400kHz C : 500kHz 1 11 VCC Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) LGATE 12 BOOT Package Type QW : WQFN-12L 2x2 (W-Type) G0 RT8240A/B/C GND (TOP VIEW) Ordering Information 9 PGOOD 8 EN RGND 7 WQFN-12L 2x2 Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8240A/B/C-04 January 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8240A/B/C Marking Information RT8240AGQW RT8240CGQW 45: Product Code 45W 43 : Product Code YMDNN : Date Code 43W RT8240AZQW RT8240CZQW 45: Product Code 45W YMDNN : Date Code 43 : Product Code YMDNN : Date Code 43W YMDNN : Date Code RT8240BGQW 29 : Product Code 29W YMDNN : Date Code RT8240BZQW 29 : Product Code 29W YMDNN : Date Code Typical Application Circuit (1) Remote Sense RT8240A/B/C VCC 5 VCC 9 PGOOD Chip Enable VIN UGATE 3 PHASE 2 8 EN 11 12, 13 (Exposed Pad) 10 VOUT LGATE 1 G0 6 GND VOUT CS RGND 7 Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 BOOT 4 Remote (+) Remote (-) is a registered trademark of Richtek Technology Corporation. DS8240A/B/C-04 January 2014 RT8240A/B/C (2) Local Sense RT8240A/B/C VCC 5 VCC 9 PGOOD Chip Enable BOOT 4 VIN UGATE 3 PHASE 2 8 EN 11 12, 13 (Exposed Pad) 10 VOUT LGATE 1 G0 GND CS VOUT 6 RGND 7 VID Table G0 VOUT 0 1V 1 1.05V Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8240A/B/C-04 January 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8240A/B/C Functional Pin Description Pin No. Pin Name Pin Function 1 LGATE Gate Drive Output for Low Side External MOSFET. 2 PHASE External Inductor Connection Pin for PWM Converter. It behaves as the current sense comparator input for low side MOSFET RDS(ON) sensing and reference voltage for on time generation. 3 UGATE Gate Drive Output for the High Side External MOSFET. 4 BOOT 5 VCC 6 VOUT Output Voltage Feedback Input. Connect VOUT to converter output node. 7 RGND Remote Voltage Sense Ground Pin. 8 EN PWM Enable Pin. Pull low to GND to disable the PWM. 9 PGOOD Open Drain Power Good Indicator. High impedance indicates power is good. CS Current Limit Threshold Setting Input. Connect a setting resistor to GND and the current limit threshold is equal to 1/8 of the voltage at this pin. 10 Supply Input for High Side Driver. Connect a capacitor to the floating node (PHASE) pin. Control Voltage Input. Provides the power for the buck controller, the low side driver and the bootstrap circuit for high side driver. Bypass to GND with a 4.7μF ceramic capacitor. 11 G0 12, GND 13 (Exposed Pad) Input Pin for Programming the Output Voltage Between 1V and 1.05V. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Function Block Diagram TRIG On-time compute One shot PHASE S Q + 1V Q + 120% VREF - 70% VREF + BOOT R - COMP GM + VREF TON OV Latch S1 Q UV Latch S1 Q BST switch resistance Voltage Programmer VOUT RGND EN 90% VREF UGATE PHASE VCC LGATE DRV LG RDS(ON) ZCD + - GND PGOOD leakage + SS Timer Thermal Shutdown Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 UG RDS(ON) Min toff TRIG One shot - G0 DRV FCCM/DEM + - OC threshold 1/8 10µA CS is a registered trademark of Richtek Technology Corporation. DS8240A/B/C-04 January 2014 RT8240A/B/C Absolute Maximum Ratings (Note 1) VCC, VOUT, PGOOD, EN, CS, G0 to GND ------------------------------------------------------------------------RGND to GND -------------------------------------------------------------------------------------------------------------z PHASE to GND DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------z BOOT to PHASE ----------------------------------------------------------------------------------------------------------z UGATE to PHASE DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------z LGATE to GND DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C WQFN-12L 2x2 -----------------------------------------------------------------------------------------------------------z Package Thermal Resistance (Note 2) WQFN-12L 2x2, θJA ------------------------------------------------------------------------------------------------------z Junction Temperature ----------------------------------------------------------------------------------------------------z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------z Storage Temperature Range -------------------------------------------------------------------------------------------z ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------z z Recommended Operating Conditions z z z z −0.3V to 6V −0.7V to 0.7V −0.3V to 32V −8V to 38V −0.3V to 6V −0.3V to 6V −5V to 7.5V −0.3V to 6V −2.5V to 7.5V 0.606W 165°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Input Voltage, VIN -----------------------------------------------------------------------------------------------Control Voltage, VCC -----------------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------------------- 4.5V to 26V 4.5V to 5.5V −40°C to 125°C −40°C to 85°C Electrical Characteristics (VCC = 5V, VIN = 8V, VEN = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit PWM Controller VCC Quiescent Supply Current IQ FB forced above the regulation point, VEN = 5V -- 500 1250 μA VCC Shutdown Current ISHDN VCC current, VEN = 0V -- -- 1 μA CS Shutdown Current CS pull to GND -- -- 1 μA VOUT Error Comparator Threshold VCC = 4.5 to 5.5V, DEM −0.5 0 0.5 % 1 -- 3.6 V fSW = 300kHz, VOUT = 1.05V 371 437 502 fSW = 400kHz, VOUT = 1.05V 279 328 377 fSW = 500kHz, VOUT = 1.05V -- 262 -- VOUT Voltage Range VOUT RT8240A On-Time, Pulse Width RT8240B RT8240C tON Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8240A/B/C-04 January 2014 ns is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8240A/B/C Parameter Minimum Off-Time Symbol Test Conditions Min Typ Max Unit 250 400 550 ns 9 10 11 μA -- 4700 -- ppm/°C −10 -- 5 mV GND − PHASE = VCS / 8 −20 0 20 mV PHASE − GND = VCS / 8 -- 3 -- mV 65 70 75 % 115 120 125 % -- 5 -- μs 3.6 3.8 4 V -- 100 -- mV tOFF Current Sensing CS Source Current ICS CS to GND CS Source Current Temperature Coefficient Zero Crossing Threshold Protection Function Current Limit ILIM Negative Current Limit Output Under Voltage Protection VUVP Threshold Over Voltage Protection VOVP OVP Fault Delay VCC Under Voltage Lockout (UVLO) Threshold VUVLO VCC UVLO Hysteresis ΔVUVLO With respect to error comparator threshold VOUT forced above OVP threshold Rising edge, PWM disabled below this level VOUT Soft-Start From EN = high to VOUT = 95% -- 1300 -- μs UV Blank Time From EN signal going high -- 3 -- ms Thermal Shutdown TSD -- 150 -- °C Thermal Shutdown Hysteresis ΔTSD -- 10 -- °C Driver On Resistance UGATE Driver Source RUGATEsr BOOT − PHASE forced to 5V -- 1.8 3.6 Ω UGATE Driver Sink RUGATEsk BOOT − PHASE forced to 5V -- 1.2 2.4 Ω LGATE Driver Source RLGATEsr LGATE, High State -- 1.8 3.6 Ω LGATE Driver Sink RLGATEsk LGATE, Low State -- 0.67 1.34 Ω LGATE Rising (VPHASE = 1.5V) -- 30 -- UGATE Rising -- 30 -- VCC to BOOT, 10mA -- -- 80 Logic-High 1.8 -- -- Logic-Low -- -- 0.5 Logic-High 735 -- -- Logic-Low -- -- 315 Dead Time Internal Boost Charging Switch On Resistance ns Ω EN Threshold EN Input Threshold Voltage V Voltage Programming Input Threshold G0 Input Threshold Voltage Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 mV is a registered trademark of Richtek Technology Corporation. DS8240A/B/C-04 January 2014 RT8240A/B/C Parameter Symbol Test Conditions PGOOD (upper side threshold determined by OVP threshold) Falling edge, measured at Trip Threshold VOUT, with respect to reference, no load. Trip Hysteresis Min Typ Max Unit −19 −15 −11 % -- 3 -- % Fault Propagation Delay Falling edge, VOUT forced below PGOOD trip threshold -- 2.5 -- μs Output Low Voltage ISINK = 1mA -- -- 0.4 V Leakage Current High state, forced to 5V -- -- 1 μA Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a low effective thermal conductivity single-layer test board per JEDEC 51-3. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8240A/B/C-04 January 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8240A/B/C Typical Operating Characteristics VOUT Efficiency vs. Load Current 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) VOUT Efficiency vs. Load Current 100 60 50 40 30 20 60 50 40 30 20 VIN = 8V, VOUT = 1.05V, EN = G0 = VCC 10 0 0.001 0.01 0.1 1 VIN = 12V, VOUT = 1.05V, EN = G0 = VCC 10 0 0.001 10 0.01 VOUT Efficiency vs. Load Current 90 440 Efficiency (%) 80 70 60 50 40 30 20 VIN = 20V, VOUT = 1.05V, EN = G0 = VCC 0.01 0.1 1 Switching Frequency (kHz)1 480 0 0.001 400 360 320 280 240 200 160 120 80 40 0 0.001 10 0.01 VIN = 12V, VOUT = 1.05V, EN = G0 = VCC 440 360 320 280 240 200 160 120 80 40 0 0.001 0.01 0.1 1 Load Current (A) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 1 10 VOUT Switching Frequency vs. Load Current 480 Switching Frequency (kHz)1 Switching Frequency (kHz)1 400 0.1 Load Current (A) VOUT Switching Frequency vs. Load Current 440 10 VIN = 8V, VOUT = 1.05V, EN = G0 = VCC Load Current (A) 480 1 VOUT Switching Frequency vs. Load Current 100 10 0.1 Load Current (A) Load Current (A) 10 VIN = 20V, VOUT = 1.05V, EN = G0 = VCC 400 360 320 280 240 200 160 120 80 40 0 0.001 0.01 0.1 1 10 Load Current (A) is a registered trademark of Richtek Technology Corporation. DS8240A/B/C-04 January 2014 RT8240A/B/C Standby Current vs. Input Voltage 680 1.061 670 Standby Current (μA) Output Voltage (V) VOUT Output Voltage vs. Load Current 1.062 1.060 1.059 1.058 1.057 1.056 1.055 VIN = 12V, VOUT = 1.05V, EN = G0 = VCC 1.054 0.001 0.01 0.1 1 660 650 640 630 620 EN = VCC, No Load 610 5 10 7 9 11 13 15 17 19 Load Current (A) Input Voltage (V) Shutdown Input Current vs. Input Voltage Power On from EN 21 23 25 Shutdown Input Current (μA)1 1.0 0.9 PGOOD (5V/Div) 0.8 0.7 0.6 EN (5V/Div) 0.5 0.4 PHASE (10V/Div) 0.3 0.2 0.1 EN = GND, No Load 0.0 5 7 9 11 13 15 17 19 21 23 VOUT (2V/Div) VIN = 12V, VOUT = 1.05V, EN = G0 = VCC, IOUT = 0.1A Time (1ms/Div) 25 Input Voltage (A) Power Off from EN VIN = 12V, VOUT = 1.05V, EN = G0 = VCC, IOUT = 0.1A PGOOD (5V/Div) Dynamic VID Up G0 (10V/Div) VIN = 12V, VOUT = 1V up to 1.05V 1.05V VOUT (20mV/Div) EN (5V/Div) 1V PHASE (10V/Div) VOUT (2V/Div) UGATE (20V/Div) LGATE (10V/Div) Time (2ms/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8240A/B/C-04 January 2014 EN = VCC, No Load Time (20μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8240A/B/C Dynamic VID Down G0 (10V/Div) VOUT DEM-Mode Load Transient Response VIN = 12V, VOUT = 1.05V, EN = G0 = VCC, IOUT = 0A to 8.5A VIN = 12V, VOUT = 1.05V down to 1V VOUT_ac (20mV/Div) 1.05V VOUT (20mV/Div) 1V UGATE (20V/Div) LGATE (10V/Div) EN = VCC, No Load I LOAD (5A/Div) UGATE (20V/Div) LGATE (10V/Div) Time (20μs/Div) Time (100μs/Div) OVP UVP VIN = 12V, VOUT = 1.05V, EN = G0 = VCC, No Load PGOOD (5V/Div) PGOOD (5V/Div) LGATE (5V/Div) UGATE (20V/Div) LGATE (10V/Div) VOUT (500mV/Div) VOUT (1V/Div) Time (100μs/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 VIN = 12V, VOUT = 1.05V, EN = G0 = VCC Time (100μs/Div) is a registered trademark of Richtek Technology Corporation. DS8240A/B/C-04 January 2014 RT8240A/B/C Application Information The RT8240A/B/C is a single, Mach ResponseTM PSRTM mode synchronous buck controller which supports chip voltage programming function between 1V and 1.05V by controlling the G0 digital input. The Richtek's PSRTM technology is specifically designed to support low ESR output capacitor system. The Richtek's Mach ResponseTM technology provides fast response to load steps. The topology circumvents the poor load transient timing problems of fixed-frequency current mode PWMs while avoiding the problems caused by widely varying switching frequency in conventional constant-on-time and constantoff-time PWM schemes. A special adaptive on-time control trade off the performance and efficiency over wide input voltage range. The PSRTM mode PWM modulator is specifically designed to have better noise immunity for such a single output application. PWM Operation The Mach ResponseTM PSRTM mode controller internally provides a pseudo ramp signal, so the controller can support low ESR output capacitor to increase the flexibility of output capacitor selection. Refer to the function block diagram of RT8240A/B/C, the synchronous high side MOSFET will be turned on at the beginning of each cycle. After the internal one shot timer expires, the MOSFET will be turned off. The pulse width of this one shot is determined by the converter's input voltage and the output voltage to keep the frequency constant in a specific input voltage range. Another one shot sets a minimum off-time (400ns typ.). The on-time one shot will be triggered if the error comparator is high, the low side switch current is below the current limit threshold, and the minimum offtime one shot has timed out. and inversely proportional to input voltage. The implementation results in a nearly constant switching frequency without the need a clock generator. Diode Emulation Mode In diode-emulation mode, the RT8240A/B/C automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increasing VOUT ripples or load regulation. As the output current decreases from heavy load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulation the behavior of diodes, the low side MOSFET allows only partial of negative current when the inductor freewheeling current reach negative. As the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level than requires the next “ON” cycle. The on-time is kept the same as that in the heavy load condition. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. The transition load point to the light load operation can be calculated as follows (Figure 1) : (VIN − VOUT ) × tON 2L where tON is the on-time. ILOAD ≈ IL Slope = (VIN-VOUT) / L IL_Peak ILOAD = IL_Peak/2 On-Time Control The on-time one shot comparator has two inputs. One input monitors the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high side switch directly proportional to output voltage Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8240A/B/C-04 January 2014 0 tON t Figure 1. Boundary Condition of CCM/DCM The switching waveforms may appear noisy and asynchronous when light loading causes diode emulation operation, but this is a normal operating condition that results in high light load efficiency. Trade-offs in DEM noise vs. light load efficiency is made by varying the inductor is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT8240A/B/C value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values include larger physical size and degrade load transient response (especially at low input voltage levels). 1V reference. The G0 digital input control the gate of internal MOSFET whose drain is connected to the bottom resistor of the internal resistor divider (Figure 3). A logic high signal on G0 will be selected to the internal resistor divider. When the G0 input changes state, the change quickly causes three actions : Output Voltage Setting ` Change from uni-feedback to internal resistor divider. The RT8240A/B/C output voltage can be adjusted from 1V to 3.6V by setting the feedback resistor R1 and R2, see Figure 2 (a). With G0 in low state, the VOUT is at the lowest value (1V). Choose R2 to be approximately 10kΩ, and solve for R1 using the below equation : VOUT = VREF × ⎛⎜ 1 + R1 ⎞⎟ where VREF is 1V typically. ⎝ R2 ⎠ The RT8240A/B/C output voltage can also set by differential, remote sense inputs to eliminate the effects of voltage drops along PC board traces. Connect to VOUT to Remote (+) and connect to RGND to Remote (−), see Figure 2 (b). ` The PGOOD output is temporarily latched into its present state. This prevents chattering or false tripping while VOUT moves to the new level. ` When G0 changes state whether DEM is set or not, then enter the PWM mode and count 32 clock cycles. For the duration of 32 clock cycles, the RT8240A/B/C will keep to monitor the UVP and OVP function. This behavior allows the output to slew down to the new level with tripping the OVP or UVP function when the G0 change causes a rapid change at VOUT pin. VREF = 1V VOUT VOUT VIN VOUT UGATE PHASE LGATE GND VOUT R1 R2 G0 Figure 3. Output Voltage Selection by G0 Input RGND Output Voltage Transition Operation (a) Resistor Divider VIN VOUT UGATE PHASE LGATE GND VOUT Remote (+) RGND Remote (-) (b) Remote sense Figure 2. Setting VOUT Output Voltage Transition Control The RT8240A/B/C provides one digital input G0 to allow selection among two output voltages. The output voltage is regulated by comparing the VOUT pin to the internal Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 The digital input control pin G0 allows VOUT to transition to both higher and lower values. For a down transition, the rapid change G0 from high to low suddenly will cause VOUT to go above 1V. At this time, the LGATE will drive high to turn on the low side MOSFET and draw current from the output capacitor via the inductor. The LGATE will remain on until VOUT falls to 1V, at which point a normal UGATE switching cycle begins, as shown in Figure 4. For a down transition, the low side MOSFET stays on before VOUT reaches to 1V, thus the negative inductor current will be increased. If the negative current too large to trigger the negative current limit, the low side MOSFET is turned off which can avoid too much negative current to damage component. Refer to the Negative Current Limit section for a full description. is a registered trademark of Richtek Technology Corporation. DS8240A/B/C-04 January 2014 RT8240A/B/C G0 G0 GND GND VOUT VOUT UGATE UGATE LGATE Initial VOUT VOUT Final VOUT Figure 4. Output Voltage Down Transition For an up transition (from lower to higher VOUT) as shown in Figure 5, the G0 change from low to high and causes VOUT to drop below 1V. This quickly trips the comparator regardless of whether DEM is active or not, generating an UGATE on-time and a subsequent LGATE will be turned on. At the end of the minimum off-time (400ns), if VOUT is still below 1V then another UGATE on-time is started. This sequence continues until the VOUT pin exceeds 1V. G0 VOUT UGATE LGATE Minimum off-time Final VOUT Initial VOUT Figure 5. Output Voltage Up Transition If the VOUT change is significant, there can be several consecutive cycle of UGATE on-time followed by minimum LGATE time. This can cause a rapid increase in inductor current : typically it only takes a few switching cycles for inductor current to rise up to the current limit. At some point the VOUT will rise up to 1V and the UGATE pulses will cease, but the inductor's LI2 energy must then flow into the output capacitor. This can create a significant overshoot, as shown in Figure 6. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8240A/B/C-04 January 2014 Final VOUT VOUT Initial VOUT Figure 6. Output Voltage Up Transition with Overshooting The overshooting can be approximated by the following equation, where ICL is the current limit, VFINAL is the desired set point for the final voltage, L is in μH and COUT is in μF : I 2 ×L VMAX = ( CL ) + VFINAL2 COUT Current Limit Setting (CS) GND VOUT LGATE The RT8240A/B/C provides cycle-by-cycle current limiting control. The current limit circuit employs a unique “Valley” current sensing algorithm. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle (Figure 7). The actual peak current is greater than the current limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and battery and output voltage. IL IL, peak ILoad ILIM 0 t Figure 7. “Valley” Current Limit is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT8240A/B/C The RT8240A/B/C uses the on resistance of the synchronous rectifier as the current sense element and supports temperature compensated MOSFET RDS(ON) MOSFET is turned off, the high side MOSFET is then turned on, and the device resumes normal operation. sensing The RILIM setting resistor between CS pin and GND sets the current limit threshold. The CS pin sources ICS current, which is 10μA typically at room temperature and this current has 4700ppm/°C temperature slope to compensate the temperature dependency of the RDS(ON). When the voltage drop across low side MOSFET equals the voltage across the RILIM setting resistor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the MOSFET falls below the current limit threshold. MOSFET Gate Driver (UGATE, LGATE) Choose a current limit setting resistor by following equation : RILIM = (IILIM x RDS(ON)) x 8 / ICS Moreover, the recommended resistance value range between 40kΩ to 160kΩ. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current sense signal seen by PHASE and GND. Negative Over Current Limit (CCM Only) The RT8240A/B/C also supports cycle-by-cycle negative over current limiting in CCM Mode only. The over current limit is set to be negative but is the same absolute value as the positive over current limit. If output voltage continues to rising, the low side MOSEFT stays on, thus inductor current is reduced and reverses direction after it reaches zero. When there is too much negative current in the inductor, the low side MOSFET is turned off and the current flows to VIN through the body diode of the high side MOSFET. Because this protection limits current to discharge the output capacitor, output voltage tends to rise, eventually hitting the over voltage protection threshold and shutdown. If the device hits the negative over current threshold again before output voltage is discharged to the target level, the low side MOSFET is turned off and process repeats. It ensures maximum allowable discharge capability when output voltage continues to rise. On the other hand, if the output is discharged to the target level before negative current threshold is reached, the low side The high side driver is designed to drive high current, low RDS(ON) N-MOSFET (s). When configured as a floating driver, 5V bias voltage is delivered from VCC supply. The average drive current is proportional to the gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between BOOT and PHASE pins. A dead time to prevent shoot through is internally generated between high side MOSFET off to low side MOSFET on, and low side MOSFET off to high side MOSFET on. The low side driver is designed to drive high current, low RDS(ON) N-MOSFET (s). The internal pulldown transistor that drives LGATE low is robust, with a 0.67Ω typical on resistance. A 5V bias voltage is delivered form VCC supply. The instantaneous drive current is supplied by the flying capacitor between VCC and GND. For high current applications, some combinations of high and low side MOSFETs might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency killing, EMI-producing shoot through currents. This is often remedied by adding a resistor in series with BOOT, which increases the turn-on time of the high side MOSFET without degrading the turn-off time, as shown in Figure 8. VIN UGATE BOOT R PHASE Figure 8. Increasing the UGATE Rise Time Power Good Output (PGOOD) The power good output is an open-drain output and requires a pull-up resistor. When the output voltage is 15% above or 15% below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within these tolerances once more. In soft start, PGOOD is actively held low and is allowed to transition high until soft start is over and the output reaches 88% of its set voltage. There is a 2.5μs delay built into PGOOD circuitry to prevent false transition. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS8240A/B/C-04 January 2014 RT8240A/B/C POR, UVLO and Soft-Start Thermal Protection Power On Reset (POR) occurs when VCC rises above to approximately 4V. After POR is triggered, the RT8240A/ B/C will reset the fault latch and prepare the PWM for operation. Below 3.8V (typ.), the VCC Under Voltage Lockout (UVLO) circuitry inhibits switching by keeping UGATE and LGATE low. A built-in soft-start is used to prevent surge current from power supply input after EN is enabled. It clamps the ramping of the internal reference voltage which is compared with FB signal. The typical soft-start duration is 1.3ms. The RT8240A/B/C monitors the temperature of itself. If the temperature exceeds the threshold value, 150°C (typ.), all internal circuitry is inactive during thermal shutdown. The RT8240A/B/C is latched once thermal shutdown is triggered and can only be released by toggling EN or VCC power on reset. Over Voltage Protection (OVP) The output voltage can be continuously monitored for over voltage. If the output exceeds 20% of its set voltage threshold, over voltage protection is triggered and the LGATE low side gate driver is forced high. This activates the low side MOSFET switch which rapidly discharges the output capacitor and reduces the input voltage. The RT8240A/B/C will be latched once OVP is triggered and only be released by toggling EN or VCC power on reset. There is a 5μs delay built into the OVP circuit to prevent false alarm. Note that LGATE latching high causes the output voltage to dip slightly negative when energy has been previously stored in the LC tank circuit. For loads that cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse polarity clamp. If the over voltage condition is caused by a short in high side switch, turning the low side MOSFET on 100% creates an electrical short between the battery and GND, blowing the fuse and disconnecting the battery from the output. Under Voltage Protection (UVP) The output voltage can be continuously monitored for under voltage. When under voltage protection is enabled, if the output is less than 70% of its set voltage threshold, under voltage protection is triggered, then both UGATE and LGATE gate drivers are forced low. In order to remove the residual charge on the output capacitor during the under voltage period, if PHASE is greater than 1V, the LGATE is forced high until PHASE is lower than 1V. During soft- Output Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows : t × (VIN − VOUT ) L = ON LIR × ILOAD(MAX) where LIR is the ratio of the peak to peak ripple current to the maximum average inductor current. Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK) : IPEAK = ILOAD(MAX) + ⎛⎜ LIR × ILOAD(MAX) ⎞⎟ ⎝ 2 ⎠ The calculation above shall serve as a general reference. To further improve transient response, the output inductor could be reduced further. This needs to be considered along with the selection of the output capacitor. Output Capacitor Selection The capacitor value and ESR determines the amount of output voltage ripple and load transient response. So, the capacitor value must be greater than the largest value calculated from below equations. VSAG = ( ΔILOAD )2 × L × ( tON + tOFF(MIN) ) 2 × COUT ⎡⎣ VIN × tON − VOUT × ( t ON + tOFF(MIN) ) ⎤⎦ VSOAR = ( ΔILOAD )2 × L 2 × COUT × VOUT 1 ⎞ VP-P = LIR × ILOAD(MAX) × ⎛⎜ ESR + ⎟ 8 × C × f OUT ⎝ ⎠ Where VSAG and VSOAR are the allowable amount of undershoot voltage and overshoot voltage in load transient, VP-P is output ripple voltage, tOFF(MIN) is minimum off-time. start, the UVP blanking time is 3ms. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8240A/B/C-04 January 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT8240A/B/C Thermal Considerations Layout Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-12L 2x2 packages, the thermal resistance, θJA, is 165°C/W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula: For best performance of the RT8240A/B/C, the following guidelines should be strictly followed. Connect RC low pass filter from VCC, 1μF and 10Ω are recommended. Place the filter capacitor close to the IC. ` Keep current limit setting network as close as possible to the IC. Routing of the network should be kept away from high voltage switching nodes to prevent it from coupling. ` Connections from the drivers to the respective gate of the high side or the low side MOSFET should be as short as possible to reduce stray inductance. ` All sensitive analog traces and components such as VOUT, RGND, EN, PGOOD, CS, G0 and VCC should be placed away from high voltage switching nodes such as PHASE, LGATE, UGATE, or BOOT nodes to prevent it from coupling. Use internal layer (s) as ground plane (s) and shield the feedback trace from power traces and components. ` Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. ` Power sections should connect directly to ground plane (s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. PD(MAX) = (125°C − 25°C) / (165°C/W) = 0.606W for WQFN-12L 2X2 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 9 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 0.65 Single-Layer PCB 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 25 50 75 100 125 Ambient Temperature (°C) Figure 9. Derating Curve of Maximum Power Dissipation Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS8240A/B/C-04 January 2014 RT8240A/B/C Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 1.900 2.100 0.075 0.083 E 1.900 2.100 0.075 0.083 e 0.400 0.016 D2 0.850 0.950 0.033 0.037 E2 0.850 0.950 0.033 0.037 L 0.250 0.350 0.010 0.014 W-Type 12L QFN 2x2 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS8240A/B/C-04 January 2014 www.richtek.com 17