APW8868B

APW8868B
DDR2 AND DDR3/DDR3L SYNCHRONOUS BUCK CONTROLLER
WITH 1.5A LDO SUPPORT LOW IQ & DROOP
Features
General Description
Buck Controller (VDDQ)
•
•
The APW8868B integrates a synchronous buck PWM con-
High Input Voltages Range from 3V to 28V Input
Power
troller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It offers the lowest total
Provide Adjustable Output Voltage from 0.675V to
solution cost in system where space is at a premium.
5.5V +1% Accuracy over Temperature
•
The APW8868B provides excellent transient response
Integrated MOSFET Drivers and Bootstrap Forward
and accurate DC voltage output in either PFM or PWM
Mode. In Pulse Frequency Mode (PFM), the APW8868B
P-CH MOSFET
•
Low Quiescent Current (200µA)
•
Excellent Line and Load Transient Responses
•
PFM Mode for Increased Light Load Efficiency
•
Constant On-Time Controller Scheme
provides very high efficiency over light to heavy loads with
loading-modulated switching frequencies. On TQFN-20
Package, the Forced PWM Mode works nearly at constant frequency for low-noise requirements.
- Switching Frequency Compensation for PWM
The APW8868B is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections.
Mode
- Adjustable Switching Frequency from 400kHz to
A Power-On- Reset function monitors the voltage on VCC
prevents wrong operation during power on.
550kHz in PWM Mode with DC Output Current
•
S3 and S5 Pins Control The Device in S0, S3 or S4/
The LDO is designed to provide a regulated voltage with
bi-directional output current for DDR-SDRAM termination.
S5 State
•
Power Good Monitoring
•
70% Under-Voltage Protection (UVP)
•
The device integrates two power transistors to source or
sink current up to 1.5A. It also incorporates current-limit
125% Over-Voltage Protection (OVP)
•
and thermal shutdown protection.
Adjustable Current-Limit Protection
The output voltage of LDO tracks the voltage at VREF pin.
- Using Sense Low-Side MOSFET’s RDS(ON)
•
TQFN-20 3mmx3mm Thin package
•
Lead Free Available (RoHS Compliant)
An internal resistor divider is used to provide a half voltage of VREF for VTTREF and VTT Voltage. The VTT output
voltage is only requiring 20µF of ceramic output capacitance for stability and fast transient response. The S3
+1.5A LDO Section (VTT)
•
Sourcing or Sinking Current up to 1.5A
•
Fast Transient Response for Output Voltage
•
Output Ceramic Capacitors Support at least 10µF
and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.
MLCC
•
VTT and VTTREF Track at Half the VDDQSNS by
internal divider
•
+20mV Accuracy for VTT and VTTREF
•
Independent Over-Current Limit (OCL)
•
Thermal Shutdown Protection
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
1
www.anpec.com.tw
APW8868B
Simplified Application Circuit
Applications
5V
VIN
+3V~28V
VCC
CS
DDR2, and DDR3/DDR3L Memory Power Supplies
•
SSTL-2 SSTL-18 and HSTL Termination
RCS
Q1
VDDQ
•
LOUT
PWM
Q2
DDR
LDO
S3
VTT
VDDQ/2
S5
Ordering and Marking Information
APW8868B
Package Code
QB : TQFN3x3-20
Operating Ambient Temperature Range
I : -40 to 85 °C
Handling Code
TR : Tape & Reel
Lead Free Code
G : Halogen and Lead Free Device
Lead Free Code
Handling Code
Temperature Range
Package Code
APW8868B QB :
APW
8868B
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
PHASE
BOOT
UGATE
VTT
LDOIN
Pin Configuration
20 19 18 17 16
15 LGATE
VTTGND 1
VTTSNS 2
14 PGND
21
PGND
GND 3
13 CS
VTTREF 4
12 VCC
VDDQSNS 5
9
10
TON
PGOOD
S3
8
S5
7
FB
11 VCC
6
= Thermal Pad (connected to GND plane for better heat dissipation)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
2
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APW8868B
Absolute Maximum Ratings (Note 1,2)
Symbol
VCC
VBOOT
VBOOT-GND
Parameter
Rating
Unit
VCC Supply Voltage (VCC to GND)
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to GND)
-0.3 ~ 35
V
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3
V
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3
V
-5 ~ 35
-0.3 ~ 28
V
-0.3 ~ 0.3
V
-0.3 ~ 7
V
UGATE Voltage (UGATE to PHASE)
<400ns pulse width
>400ns pulse width
LGATE Voltage (LGATE to GND)
<400ns pulse width
>400ns pulse width
PHASE Voltage (PHASE to GND)
<400ns pulse width
>400ns pulse width
PGND, VTTGND and CS_GND to GND Voltage
All Other Pins (CS, S3, S5, VTTSNS, VDDQSNS, VLDOIN, VFB,
PGOOD, VTT, VTTREF GND)
Tj
TSTG
TSDR
Maximum Junction Temperature
Storage Temperature
Maximum Soldering Temperature, 10 Seconds
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Note 2: The device is ESD sensitive. Handling precautions are recommended.
Thermal Characteristics (Note 3)
Symbol
Parameter
Typical Value
θJA
Thermal Resistance -Junction to Ambient
50
θJC
Thermal Resistance -Junction to Case
8
Unit
°C/W
°C/W
Note 3: θJA and θJCare measured with the component mounted on a high effective the thermal conductivity test board in free air. The
exposed pad of package is soldered directly on the PCB
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
3
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APW8868B
Recommended Operating Conditions (Note 4)
Symbol
Parameter
VCC
VCC Supply Voltage
VIN
Converter Input Voltage
VVDDQ
LDO Output Voltage
IOUT
Converter Output Current
IVTT
LDO Output Current
CVCC
VCC Capacitance
CVTT
Unit
4.5 ~ 5.5
V
3 ~ 28
V
0.75 ~5.5V
V
0.375 ~ 2.75
V
Converter Output Voltage
VVTT
Range
0 ~ 15
A
-1.5 ~ +1.5
A
1~
µF
VTT Output Capacitance
10~100
µF
VTTREF Output Capacitance
0.01~0.1
µF
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
CVTTREF
C
C
Note 4: Refer to the typical application circuit.
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Sym bol
Param eter
APW 8868 B
Test Conditions
Unit
Min
Typ
Max
-
180
2 20
µA
-
120
1 60
µA
µA
SUP PLY CURRENT
I VC C
VCC S upp ly Curre nt
o
T A = 2 5 C, VS3 = V S5 = 5V, no load , VCC Cu rrent
o
I VC CSTB
I VC CSDN
I LDOIN
I LDOIN STB
VCC Standb y Curre nt
VCC S hutdown Current
LDOIN S uppl y Curren t
LDOIN Standb y Curre nt
I LDOIN SDN LDOIN S hutdown Cu rrent
T A = 2 5 C, VS3 = 0 V, V S5 = 5V, no load, VCC
Current
o
T A =25 C, V S3 = VS5 = 0V, no loa d
-
0.1
1
o
-
1
10
o
-
0.1
10
o
-
0.1
1
3 .9 5
4.1
4.4
V
-
0.1
-
V
T A = 2 5 C, VS3 = V S5 = 5V, no load
T A = 2 5 C, VS3 = 0 V, V S5 = 5V, no load,
T A = 2 5 C, VS3 = V S5 = 0V, no load
µA
POWER-ON-RESET
VCC P OR Thr eshold
VCC Rising
VCC P OR Hyste resis
VTT OUTP UT
VVTT
VTT O utp ut Voltage
VLD OIN = VVDD QSNS = 1.5V
-
0.75
-
VLD OIN = VVDD QSNS = 1.35 V
-
0.6 75
-
VLD OIN = VVDD QSNS = 1.2V
-
0.6
-
-20
-
20
-30
-
30
VLD OIN = VVDD QSNS = 1.5V , VVDDQSNS/2 - VVTT,
IVTT = 0 A
VLD OIN = VVDD QSNS = 1.5V , VVDDQSNS/2 - VVTT,
IVTT = 1 A
VVTT
VTT O utp ut Tolera nce
mV
VLD OIN = VVDD QSNS = 1.35 V, VVD DQSNS/2 - VVTT,
IVTT = 0 A
VLD OIN = VVDD QSNS = 1.35 V, VVD DQSNS/2 - VVTT,
IVTT = 1 A
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
V
4
-20
-
20
-30
-
30
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APW8868B
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Sym bol
Param eter
APW 8868 B
Test Conditions
Unit
Min
Typ
Max
-20
-
20
VTT OUTP UT
VLD OIN = VVDD QSNS = 1.2V , VVDDQSNS/2 - VVTT,
IVTT = 0 A
VVTT
VTT O utp ut Tolera nce
mV
VLD OIN = VVDD QSNS = 1.2V , VVDDQSNS/2 - VVTT,
-30
-
30
25
30
35
T J=2 5oC
1.2
1.8
2.6
T J=2 5oC
-1.3
-1 .8
-2 .6
o
1.1
1.8
2.6
o
T J=2 5 C
-1.2
-1 .8
-2 .6
T J=2 5oC
1
1.8
2.6
-1.05
-1 .8
-2 .6
Upper MOS FE T
-
3 50
500
Lower MOS FE T
-
3 50
500
-1.0
-
1.0
µA
-1.00
0.01
1 .00
µA
15
25
-
mA
IVTT = 1 A
T SSVTT
IL IM
R DS(ON )
I VTTLK
VTT S oft Start time
Curr ent-Limit
VTT P owe r MO SFETs R DS(ON)
VTT Le akage Curre nt
I VTTSNSLK VTTSNS Leakag e Cu rrent
S3 is go high to 0.9 5*VTT Regu lation
Sour cin g Cu rrent
(VLD OIN=1.5V)
Sinking Curr ent
(VLD OIN =1.5V)
Sour cin g Cu rrent
(VLD OIN =1.35 V)
Sinking Curr ent
(VLD OIN =1.35 V)
Sinking Curr ent
(VLD OIN =1.2V)
Sinking Curr ent
(VLD OIN =1.2V)
us
A
T J=2 5 C
A
A
o
T J=2 5 C
mΩ
VVTT = 1.25V, VS3 = 0 V, V S5 = 5V,
o
TA = 2 5 C
o
VVTT = 1.25V, T A = 2 5 C
o
I VTTDIS
VTT Discharge Curr ent
VVTT = 0.5V, VS3 = VS5 = 0 V, T A = 25 C
VVREF = 0V
VTTRE F O UTPUT
VVTTR EF
VTTREF Outp ut Voltage
VLD OIN = VVDD QSNS = 1.5V, VVD DQSN S/2
-
0.75
-
VLD OIN = VVDD QSNS = 1.35V, V VDDQSNS/2
-
0 .6 75
-
VLD OIN = VVDD QSNS = 1.2V, VVD DQSN S/2
-
0.6
-
-20
-
20
-20
-
20
-20
-
20
-10mA < IVTTREF < 10 mA, VVD DQSN S/2 - VVTTR EF
VLD OIN = VVTTR EF =1.5V
VTTREF Toler ance
-10mA < IVTTREF < 10 mA, VVD DQSN S/2 - VVTTR EF
V
mV
VLD OIN = VVDD QSNS = 1.35 V
-10mA < IVTTREF < 10 mA, VVD DQSN S/2 - VVTTR EF
VLD OIN = VVDD QSNS = 1.2V
I VTTREF
VTTREF So urce Curren t
VVTTR EF = 0V
-10
-2 0
- 50
mA
I VTTREF
VTTREF Si nk Curre nt
VVTTR EF = 1.5V
10
20
60
mA
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
5
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APW8868B
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Sym bol
Param eter
APW 8868 B
Test Conditions
Min
Typ
Unit
Max
VDDQ OUTPUT
o
TA = 2 5 C
T A = - 40 oC to 85 oC
0.67
0.6 75
0.685
V
0 .6 675
0.6 75
0 .6 825
V
-0.1
-
+0.1
%
-1
-
+1
%
-0.1
-
+0.1
µA
15
25
-
mA
o
VVFB
VFB Regula ti on Vo lta ge
T A = 2 5 C,
VVCC = 4 .5V to 5.5V, VIN = 3V to 2 8V
o
T A = 2 5 C,
Load = 0 to 10A , VVC C = 4.5 V to 5.5V
VFB Input Cu rrent
VVFB= 0.78V
VDDQ Discha rge Curren t
VS3 = VS5 = 0 V, V VDDQSNS = 0.5 V,
PWM CONTROLLE RS
F SW
Ope rating Frequ ency
Adju stabl e Fre quen cy
400
-
550
KHz
T SS
Internal So ft Sta rt Time
S5 is Hi gh to 0.9*VO UT Regula tio n
0.77
1.1
1 .4
ms
TO
Fast on time
VIN =1 9V, V VDDQ =1 .5V , R TON =620KΩ
175
2 05
235
ns
-
3 00
-
ns
80
11 0
140
ns
-9.5
0.5
10.5
mV
4
5
6
µA
-
450 0
-
ppm/
o
C
-18
0
+1 8
mV
TOFF(MIN)
Minimum off time
T ON (MIN)
Slo w on time
Zero-Crossing Thresh old
VDDQ PROTECTIONS
o
TA = 2 5 C
CS Pin Sink Curren t
Tempera tur e Co efficient,
On The Basis of 25 °C
OCP Comparator Offset
(VVCC – V CS) – (V PHASE – PGND),
VVCC – VC S = 6 0mV
VDDQ Curren t Limit S ettin g Ran ge VVCC -VCS
30
-
200
mV
120
1 25
130
%
-
1.5
-
µs
60
70
80
%
-
10
-
µs
PG OOD in fr om Lo we r ( PGOOD Goes High)
87
90
93
%
PGOOD in from High er (PGOOD Goes Hi gh)
120
1 25
130
%
VDDQ OVP Tr ip Thre sh old
VVDD Q Risin g
VDDQ OVP Debo unce Delay
VFB Rising, DV=1 0mV
VDDQ UVP Trip Threshol d
VVDD Q Falling
VDDQ UVP Deboun ce
PGOOD
VPGOOD
I PGOOD
PG OOD Th reshold
PG OOD Leakag e Cu rrent
VPGOOD=5V
PG OOD Sink Curren t
VPGOOD=0.3V
PG OOD Debou nce Time
TSSPOK
PO K Soft Star t tim e
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
S5 is Hi gh to POK Ready
6
-
0.1
1 .0
µA
2.5
7.5
-
mA
-
63
-
µs
1.5
2
2 .6
ms
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APW8868B
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Sym bol
Param eter
APW 8868 B
Test Conditions
Unit
Min
Typ
Max
GATE DRIVE RS
UGATE P ull-Up Resistan ce
BO OT-UGATE=0.5V
-
5
7
Ω
UGATE S ink Resistance
UGATE-PHAS E=0.5 V
-
1
2 .5
Ω
LGATE Pu ll -Up Resistance
PV CC-L GATE=0.5V
-
5
7
Ω
LGATE Sink Resistance
LGATE-P GND=0.5V
-
1
2 .5
Ω
UGATE to LGATE Dead time
UGATE falli ng to LGATE rising , no loa d
-
20
-
ns
LGATE to UGATE Dead time
LGATE falling to UGATE rising , no loa d
-
20
-
ns
BOO TS TRAP DIODE
o
Forward Voltage
VVCC – VBOOT , I F = 1 0mA, T A = 25 C
-
0.3
0 .5
V
Reve rse Leakag e
VBOOT = 30V, VPHASE = 25V, VVC C=5V, T A = 25 C
-
-
0 .5
µA
2
-
-
V
o
LOG IC THRESHOLD
VIH
S3, S5 High Thresho ld V oltage
S3, S5 Risi ng
VIL
S3, S5 Low Threshol d V oltage
S3, S5 Falling
-
-
0 .8
V
I ILEAK
Logi c Input Leakag e Cu rrent
VS3 = VS5 = 5 V, T A =25 C
-1
-
1
µA
T J Rising
-
1 60
-
o
-
25
-
o
o
THE RMAL SHUTDOWN
TSD
Thermal Shutdown Te mperature
Thermal Shutdown Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
7
C
C
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APW8868B
Typical Operating Characteristics
Supply Current In S3 VS Temperature
Supply Current In S0 VS Temperature
250
200
175
200
Supply Current (uA)
Supply Current (uA)
225
175
150
125
100
75
150
125
100
75
50
50
25
25
0
-60 -40 -20
0
20 40 60 80 100 120 140 160
0
-60 -40 -20
0
o
20 40 60 80 100 120 140 160
Temperature(oC)
Temperature( C)
Shutdown Current VS Temperature
On-Time VS Temperature
1.6
240
235
1.4
225
On-Time (ns)
Shutdown Current (uA)
230
1.2
1.0
0.8
0.6
220
215
210
205
200
0.4
195
190
0.2
185
0
-60 -40 -20
180
-60 -40 -20
20 40 60 80 100 120 140 160
0
Temperature (oC)
0
20 40 60 80 100 120 140 160
Temperature (oC)
Reference Voltage VS Temperature
755
Reference Voltage (mV)
754
753
752
751
750
749
748
747
746
745
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (oC)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
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APW8868B
Operating Waveforms
Enable S3 – No Load
Enable VCC – No Load
CH2
CH2
CH3
CH3
CH1
CH1
CH4
CH4
CH1:VS3-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-10A/div
Time:50us/div
CH1:VCC-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-2A/div
Time:5ms/div
Disable S3/S5 – No Load
OTP
CH2
CH1
CH3
CH2
CH4
CH1
CH3
CH1:VS3/S5-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-1A/div
Time:500us/div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
CH1:VDDQ-1V/div
CH2:VTT-500mV/div
CH3:IL-10A/div
Time:200ms/div
9
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APW8868B
Operating Waveforms (Cont.)
Normal Operaion
UVP
CH2
CH2
CH3
CH3
CH1
CH1
CH4
CH4
CH1:Phase-2V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-10A/div
Time:20us/div
CH1:Phase-20V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-5A/div
Time:2us/div
POK-Enable S3/S5
OCP
CH2
CH2
CH3
CH3
CH1
CH1
CH4
CH4
CH1:Phase-20V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-10A/div
Time:100us/div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
CH1:POK-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:VS3/S5-5V/div
Time:500us/div
10
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APW8868B
Operating Waveforms (Cont.)
Load Transient-Load=1.2A<-->12A
CH1
CH2
CH1:VDDQ-50mV/div
CH2:IL-5A/div
Time:50us/div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
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APW8868B
Pin Description
NO .
NAM E
FUNCTION
1
VTTGND
Po wer gr ound ou tp ut for the VTT LDO.
2
VTTSNS
Vo lta ge se nse inp ut for the VTT L DO. Conne ct to plus te rmi nal of the VTT LDO output cap acito r.
3
GND
4
VTTRE F
5
VDDQSNS
6
FB
VDDQ outpu t vo ltage setting p in.
7
S3
S3 signa l input.
8
S5
S5 signa l input.
9
TON
10
PGOO D
11, 1 2
VCC
13
CS
14
PGND
15
LGATE
16
PHASE
17
UGATE
18
BOOT
19
LDOIN
20
VTT
Sig nal Gro und.
VTTREF b uffere d referen ce ou tp ut.
VDDQ refere nce i nput for VTT and VTTREF. Power supp ly for the VTTREF. Dischar ge curren t
sinking terminal for VDDQ non -tra cking d ischa rge.
This Pin is Al lowed to Adjust The Switching Freq uency. Conn ect a resisto r R TON = 1 00KΩ ~
1.2MΩ fr om TON pin to PHASE p in.
Po wer -goo d o utp ut pi n. PG OOD is an ope n d rain outpu t used to Indicate th e status of the ou tp ut
voltage. W hen VDDQ output voltage is within the target rang e, it is in high state.
5V po we r sup ply voltag e input pin fo r both internal control circuitry a nd low-side MOSFET gate
driver.
Over-cur rent trip voltag e setting inpu t for R DS(ON) curre nt sense sch eme if conne cted to GND
throug h th e vol tag e setting resistor.
Po wer gr ound of the LGATE lo w-sid e MO SFET driver. Co nnect the pin to th e Source of the
low-side MOSFET.
Ou tpu t of the lo w-sid e MO SFET d rive r for PWM. Con nect this pin to G ate o f the low-side
MOSFET. Swings from PG ND to VCC.
Junction poin t of the high -side MO SFET Source, output filter indu ctor and the low-side MOSFET
Drain. Conne ct th is pin to th e S ource of the hi gh-side MOSFE T. PHASE serves as the lower
suppl y rail for the UGATE high -si de gate driver.
Ou tpu t of the h igh-side MOSFET driver for PWM. Con nect this p in to Ga te of th e high- sid e
MOSFET.
Su pply Inp ut fo r the UGATE Gate Dri ver an d a n i nte rnal level-shift circuit. Conne ct to an exter nal
capacitor and d iode to cre ate a b ooste d vo ltag e su ita ble to d rive a log ic-level N-chann el
MOSFET.
Su pply vol tag e i nput fo r the VTT LDO .
Po wer ou tp ut for the VTT LDO.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
12
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APW8868B
Block Diagram
0.5 x VDDQ
VDDQSNS
VTTREF
VLDOIN
Thermal
Shutdown
S3
Current Limit
S3,S5 Control Logic
VTT
S5
0.5 x VDDQ +5/10%
VTTSNS
0.5 x VDDQ -5/10%
VTTGND
Non-Tracking
Discharge
VCC
Soft Start
POR
VCC
GND
1.25V
VREF
Current
Limit
CS
VREF
FB
5uA
125% x VREF
OV
Error
Comparator
BOOT
UGATE
UV
PWM
Signal
Controller
70% x VREF
TON
PHASE
TON Generator
PHASE
VCC
ZC
LGATE
VREF x 125%/122%
PGOOD
PGND
Delay
VREF x 90%/87%
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
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APW8868B
Typical Application Circuit
CBOOT
VIN
7V~25V
CIN
0.1uF
Q1
LOUT
1uH
PHASE
VDDQ
10uF x 2
VTT
VDDQ/2
VDDQ
10A
COUT
22uF x 4
(MLCC)
PHASE
UGATE
BOOT
CVTT
10uF x 2
LDOIN
VTT
Q2
VTTGND
LGATE
VTTSNS
PGND
RCS
APW8868B
RVCC
5.1K, 1%
TQFN-20
VTTREF
VDDQ/2
VCC
CS
VCC
VTTREF
2.2
CVCC
1uF
PGOOD
TON
S3
S5
VDDQSNS
FB
CVTTREF
0.033uF
CPVCC
4.7uF
RPGOOD
PGOOD
RTON
VDDQ
RTOP
75K, 1%
100k
VIN or PHASE
RGND
75K, 1%
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
620k
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APW8868B
Function Description
The APW8868B integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO
Both in PFM and PWM, the on-time generator, which
senses input voltage on PHASE pin, provides very fast
on-time response to input line transients.
linear regulator to generate VTT. It provides a complete
power supply for DDR2 and DDR3/DDR3L memory sys-
Another one-shot sets a minimum off-time (typical:
300ns). The on-time one-shot is triggered if the error com-
tem in a 20-pin TQFN package. User defined output voltage is also possible and can be adjustable from 0.675V
parator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
to 5.5V. Input voltage range of the PWM converter is 3V to
28V. The converter runs an adaptive on-time PWM opera-
shot has timed out.
Power-On-Reset
tion at high-load condition and automatically reduces frequency to keep excellent efficiency down to several mA.
A Power-On-Reset (POR) function is designed to prevent
The VTT LDO can source and sink up to 1.5A peak current with only 10µF ceramic output capacitor. VTTREF
wrong logic controls when the VCC voltage is low. The
POR function continually monitors the bias supply volt-
tracks VDDQ/2 within 1% of VDDQ. VTT output tracks
VTTREF within 20 mV at no load condition while 40 mV at
age on the VCC pin if at least one of the enable pins is set
high. When the rising VCC voltage reaches the rising
full load. The LDO input can be separated from VDDQ
and optionally connected to a lower voltage by using
POR voltage threshold (4.1V typical), the POR signal goes
high and the chip initiates soft-start operations. Should
VLDOIN pin. This helps reducing power dissipation in
sourcing phase. The APW8868B is fully compatible to
this voltage drop lower than 4V (typical), the POR disables the chip.
JEDEC DDR2 and DDR3/DDR3L specifications at S3/
S5 sleep state (see Table 1). When both VTT and VDDQ
Soft- Start
are disabled, the non-tracking discharge mode discharges outputs using internal discharge MOSFETs that
The APW8868B integrates digital soft-start circuits to ramp
up the output voltage of the converter to the programmed
are connected to VDDQSNS and VTT.
regulation set point at a predictable slew rate. The slew
rate of output voltage is internally controlled to limit the
inrush current through the output capacitors during soft-
Constant-On-Time PWM Controller with Input Feed-Forward
start process. The figure 1 shows VDDQ soft-start
sequence. When the S5 pin is pulled above the rising S5
The constant on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar-
threshold voltage, the device initiates a soft-start process
to ramp up the output voltage. The soft-start interval is 1.
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resistor,
2ms (typical) and independent of the UGATE switching
frequency.
so the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input
2ms
VCC and VPVCC
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
1.2ms
VOUT
a switching frequency control circuit in the on-time generator block. The switching frequency control circuit
senses the switching frequency of the high-side switch
and keeps regulating it at a constant frequency in PWM
S5
mode. The design improves the frequency variation and
be more outstanding than a conventional constant ontime controller which has large switching frequency variation over input voltage, output current and temperature.
VPGOOD
Fig1. Soft-Start Sequence
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
15
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APW8868B
Function Description (cont.)
Soft- Start (cont.)
Over Voltage Protection (OVP)
During soft-start stage before the PGOOD pin is ready,
The feedback voltage should increase over 125% of the
the under voltage protection is prohibited. The over voltage and current limit protection functions are enabled. If
reference voltage due to the high-side MOSFET failure or
for other reasons, and the over voltage protection com-
the output capacitor has residue voltage before startup,
both low-side and high-side MOSFETs are in off-state
parator designed with a 1.5µs noise filter will force the
low-side MOSFET gate driver to be high. This action ac-
until the internal digital soft start voltage equal the internal feedback voltage. This will ensure the output voltage
tively pulls down the output voltage and eventually attempts to blow the battery fuse.
starts from its existing voltage level.
The VTT LDO part monitors the output current, both sourc-
When the OVP occurs, the PGOOD pin will pull down and
latch-off the converter. This OVP scheme only clamps the
ing and sinking current, and limits the maximum output
current to prevent damages during current overload or
voltage overshoot, and does not invert the output voltage
when otherwise activated with a continuously high output
short circuit (shorted from VTT to GND or VLDOIN)
conditions.
from low-side MOSFET driver. It’s a common problem for
OVP schemes with a latch. Once an over-voltage fault
The VTT LDO provides a soft-start function, using the
constant current to charge the output capacitor that gives
condition is set, toggling VCC power-on-reset signal can
only reset it.
a rapid and linear output voltage rise. If the load current is
above the current limit start-up, the VTT cannot start
PWM Converter Current Limit
successfully.
APW8868B has an independent counter for each output,
The current-limit circuit employs a unique “valley” current
sensing algorithm (Figure 2). CS pin should be con-
but the PGOOD signal indicates only the status of VDDQ
and does not indicate VTT power good externally.
nected to GND through the trip voltage-setting resistor,
RCS. CS terminal sinks 5uA current, ICS, and the current
limit threshold is set to the voltage across the RCS. The
voltage between or CS_GND pin and PHASE pin moni-
Power-Good Output (PGOOD)
PGOOD is an open-drain output and the PGOOD comparator continuously monitors the output voltage. PGOOD
tors the inductor current so that PHASE pin should be
connected to the drain terminal of the low side MOSFET.
is actively held low in shutdown, and standby. When PWM
converter’s output voltage is greater than 95% of its tar-
PGND is used as the positive current sensing node so
that PGND should be connected to the proper current
get value, the internal open-drain device will be pulled
low. After 63µs debounce time, the PGOOD goes high.
sensing device, i.e. the sense resistor or the source terminal of the low side MOSFET.
The PGOOD goes low if VVDDQ output is 10% below or
above its nominal regulation point.
If the magnitude of the current-sense signal is above the
current-limit threshold, the PWM is not allowed to initiate
Under Voltage Protection
In the process of operation, if a short-circuit occurs, the
a new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the induc-
output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage
tor ripple current. Therefore, the exact current- limit characteristic and maximum load capability are a function of
will fall out of the required regulation range. The undervoltage continually monitors the setting output voltage
the sense resistance, inductor value, and input voltage.
The equation for the current limit threshold is as follows:
after 2ms of PWM operations to ensure startup. If a load
step is strong enough to pull the output voltage lower
ILIMIT=
than the under voltage threshold (70% of normal output
voltage), APW8868B shuts down the output gradually and
1/10×RCS×5uA (VIN− VVDDQ) VVDDQ
+
×
RDS(ON)
2×L×fsw
VIN
latches off both high and low side MOSFETs.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
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APW8868B
Function Description (cont.)
PWM Converter Current Limit(cont.)
S3, S5 Control
Where ILIMIT is the desired current limit threshold, RCS is
the value of the current sense resistor connected to CS
In the DDR2/DDR3/DDR3L memory applications, it is
important to keep VDDQ always higher than VTT/VTTREF
and GND pins VCS is the voltage across the RCS resistor
IRIPPLE is inductor peak to peak current FSW is the PWM
including both start-up and shutdown. The S3 and S5
signals control the VDDQ, VTT, VTTREF states and these
switching frequency.
In a current limit condition, the current to the load ex-
pins should be connected to SLP_S3 and SLP_S5 signals respectively. The table1 shows the truth table of the
ceeds the current to the output capacitor thus the output
voltage tends to fall down. If the output voltage becomes
S3 and S5 pins. When both S3 and S5 are above the
logic threshold voltage, the VDDQ, VTT and VTTREF are
less than power good level, the VCS is cut into half and the
output voltage tends to be even lower. Eventually, it
turned on at S0 state. When S3 is low and S5 is high, the
VDDQ and VTTREF are kept on while the VTT voltage is
crosses the under voltage protection threshold and
shutdown.
disabled and left high impedance in S3 state. When both
S3 and S5 are low, the VDDQ, VTT and VTTREF are turned
off and discharged to the ground.
INDUCTOR CURRENT
IPEAK
STATE S3 S5
ILIMIT
IVALLEY
S0
H
H
S3
L
H
S4/5
L
L
VDDQ
VTTREF
VTT
1
1
1
1
1
0 (high-Z)
0 (discharge) 0 (discharge) 0 (discharge)
Table1. The Truth Table of S3 and S5 pins.
0
Time
Thermal Shutdown
Fig2. Current Limit Algorithm
A thermal shutdown circuit limits the junction temperature of APW8868B. When the junction temperature ex-
VTT Sink/Source Regulator
ceeds +160oC, PWM converter, VTTLDO and VTTREF are
shut off, allowing the device to cool down. The regulator
The output voltage at VTT pin tracks the reference voltage
applied at VTTREF pin. Two internal N-channel MOSFETs
regulates the output again through initiation of a new softstart cycle after the junction temperature cools by 25oC,
controlled by separate high bandwidth error amplifiers
regulate the output voltage by sourcing current from
resulting in a pulsed output during continuous thermal
overload conditions. The thermal shutdown designed with
VLDOIN pin or sinking current to GND pin. To prevent two
pass transistors from shoot-through, a small voltage off-
a 25oC hysteresis lowers the average junction temperature during continuous thermal overload conditions, ex-
set is created between the positive inputs of the two error
amplifiers. The VTT with fast response feedback loop
tending life time of the device. For normal operation, device power dissipation should be externally limited so
keeps tracking to the VTTREF within +40 mV at all conditions including fast load transient.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
that junction temperatures will not exceed +125oC.
17
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APW8868B
Function Description (cont.)
Programming the On-Time Control and PWM Switching Frequency
The APW8868B does not use a clock signal to produce
PWM. The device uses the constant on-time control architecture to produce pseudo-fixed frequency with input
voltage feed-forward. The on-time pulse width is proportional to output voltage VDDQ and inverse proportional to
input voltage VIN. In PWM, the on-time calculation is written as below equation.
 2 × V VDDQ
TON = 6.3 × 10 −12 × R TON ×  3
VIN






Where:
RTON is the resistor connected from TON pin to PHASE
pin. Furthermore, The approximate PWM switching frequency is written as:
TON =
VOUT / VIN
D
= FSW =
TON
FSW
Where:
FSW is the PWM switching frequency
APW8868B doesn’t have VIN pin to calculate on-time
pulse width. Therefore, monitoring VPHASE voltage as input voltage to calculate on-time when the high-side
MOSFET is turned on. And then, use the relationship between on-time and duty cycle to obtain the switching
frequency.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
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APW8868B
Application Information
Output Voltage Selection
PWM can be also adjusted from 0.675V to 5.5V with a
In some types of inductors, especially core that is made
of ferrite, the ripple current will increase abruptly when it
resistor-driver at FB between VDDQSNS and GND. Using 1% or better resistors for the resistive divider is
saturates. This will be result in a larger output ripple
voltage.
recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.675V. Take
Output Capacitor Selection
the example, the output voltage of PWM is determined
by:
Output voltage ripple and the transient voltage deviation
are factors that have to be taken into consideration when
selecting an output capacitor. Higher capacitor value and

 R
V OUT = 0.675 × 1 + TOP 
 RGND 
lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low
Where RTOP is the resistor connected from VOUT to FB and
RGND is the resistor connected from FB to GND.
ESR capacitors is intended for switching regulator
applications. In addition to high frequency noise related
Output Inductor Selection
MOSFET turn-on and turn-off, the output voltage ripple
includes the capacitance voltage drop and ESR voltage
The duty cycle of a buck converter is the function of the
drop caused by the AC peak-to-peak current. These two
voltages can be represented by:
input voltage and output voltage. Once an output voltage
is fixed, it can be written as:
D=
∆VCOUT =
VOUT
VIN
The inductor value determines the inductor ripple current
∆VESR = IRIPPLE × RESR
and affects the load transient response. Higher inductor
value reduces the inductor’s ripple current and induces
These two components constitute a large portion of the
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
IRIPPLE =
IRIPPLE
8C OUT FSW
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
VIN − VOUT VOUT
×
FSW × L
VIN
ESR value. If the output of the converter has to support
another load with high pulsating current, more capaci-
Where FSW is the switching frequency of the regulator.
Although increase the inductor value and frequency re-
tors are needed in order to reduce the equivalent ESR
and suppress the voltage ripple to a tolerable level. A
duce the ripple current and voltage, there is a tradeoff
between the inductor’s ripple current and the regulator
small decoupling capacitor in parallel for bypassing the
noise is also recommended, and the voltage rating of the
load transient response time.
A smaller inductor will give the regulator a faster load
output capacitors must also be considered.
To support a load transient that is faster than the switch-
transient response at the expense of higher ripple current.
Increasing the switching frequency (FSW ) also reduces
ing frequency, more capacitors have to be used to reduce the voltage excursion during load step change. An-
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
other aspect of the capacitor selection is that the total AC
current going through the capacitors has to be less than
tion of the converter. The maximum ripple current occurs
at the maximum input voltage. A good starting point is to
the rated RMS current specified on the capacitors to prevent the capacitor from over-heating.
choose the ripple current to be approximately 30% of the
maximum output current. Once the inductance value has
been chosen, selecting an inductor is capable of carrying
the required peak current without going into saturation.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
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APW8868B
Application Information (cont.)
Phigh-side = IOUT2(1+TC)(RDS(ON))D+(0.5)(IOUT)(VIN)(tSW )FSW
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation,
select the capacitor voltage rating to be at least 1.3 times
Plow-side = IOUT2(1+TC)(RDS(ON))D(1-D)
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2,
Where
I is the load current
where IOUT is the load current. During power up, the input
capacitors have to handle large amount of surge current.
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
In low-duty notebook applications, ceramic capacitors are
recommended. The capacitors must be connected be-
tSW is the switching interval
D is the duty cycle
tween the drain of high-side MOSFET and the source of
low-side MOSFET with very low-impedance PCB layout.
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transition
loss. The switching internal, t SW , is the function of the
MOSFET Selection
The application for a notebook battery with a maximum
voltage of 24V, at least a minimum 30V MOSFETs should
reverse transfer capacitance CRSS. The (1+TC) term is to
factor in the temperature dependency of the RDS(ON) and
be used. The design has to trade off the gate charge with
the RDS(ON) of the MOSFET:
can be extracted from the “RDS(ON) vs Temperature” curve
of the power MOSFET.
- For the low-side MOSFET, before it is turned on, the
body diode has been conducted. The low-side MOSFET
Layout Consideration
driver will not charge the miller capacitor of this MOSFET.
- In the turning off process of the low-side MOSFET, the
In any high switching frequency converter, a correct layout is important to ensure proper operation of the
load current will shift to the body diode first. The high dv/
dt of the phase node voltage will charge the miller ca-
regulator. W ith power devices switching at higher
frequency, the resulting current transient will cause volt-
pacitor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the
age spike across the interconnecting impedance and
parasitic circuit elements. As an example, consider the
low-side MOSFETs. The duty cycle is often very small in
high battery voltage applications, and the low-side
turn-off transition of the PWM MOSFET. Before turn-off
condition, the MOSFET is carrying the full load current.
MOSFET will conduct most of the switching cycle;
therefore, the RDS(ON) of the low-side MOSFET, the less
During turn-off, current stops flowing in the MOSFET and
is freewheeling by the lower MOSFET and parasitic diode.
the power loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFET
Any parasitic inductance of the circuit generates a large
voltage spike during the switching interval. In general,
does not have this zero voltage switching condition, and
because it conducts for less time compared to the low-
using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of
side MOSFET, the switching loss tends to be dominant.
Priority should be given to the MOSFETs with less gate
voltage spike. And signal and power grounds are to be
kept separating and finally combined to use the ground
charge, so that both the gate driver loss and switching
loss will be minimized.
plane construction or single point grounding. The best
tie-point between the signal ground and the power ground
The selection of the N-channel power MOSFETs are determined by the RDS(ON), reversing transfer capacitance
is at the negative side of the output capacitor on each
channel, where there is less noise. Noisy traces beneath
(CRSS) and maximum output current requirement. The
losses in the MOSFETs have two components: conduc-
the IC are not recommended. Below is a checklist for
your layout:
tion loss and transition loss. For the high-side and lowside MOSFETs, the losses are approximately given by
the following equations:
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
20
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APW8868B
Application Information (cont.)
Layout Consideration
3mm
- Keep the switching nodes (UGATE, LGATE, BOOT, and
PHASE) away from sensitive small signal nodes(VFB,
VTTREF, and CS) since these nodes are fast moving
signals. Therefore, keep traces to these nodes as short
0.5mm *
as possible and there should be no other weak signal
traces in parallel with theses traces on any layer.
1.66 mm
0.2mm
- The signals going through theses traces have both high
dv/dt and high di/dt, with high peak charging and discharging current. The traces from the gate drivers to the
MOSFETs (UGATE and LGATE) should be short and wide.
3mm
0.4mm
1.66 mm
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimiz-
0.17mm
0.5mm
ing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
- Decoupling capacitor, the resistor dividers, boot
capacitors, and current limit stetting resistor should be
TQFN3x3-20
close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET
* Just Recommend
Figure3. Recommended Minimum Footprint
as close as possible. The bulk capacitors are also placed
near the drain).
- The input capacitor should be near the drain of the upper MOSFET; the high quality ceramic decoupling capacitor can be put close to the VCC and GND pins; the VTTREF
decoupling capacitor should be close to the VTTREF pin
and GND; the VDDQ and VTT output capacitors should
be located right across their output pin as close as possible to the part to minimize parasitic. The input capacitor
GND should be close to the output capacitor GND and
the lower MOSFET GND.
- The drain of the MOSFETs (VIN and PHASE nodes)
should be a large plane for heat sinking. And PHASE pin
traces are also the return path for UGATE. Connect this
pin to the converter’s upper MOSFET source.
- The APW8868B used ripple mode control. Build the resistor divider close to the VFB pin so that the high impedance trace is shorter. And the VFB pin traces can’t be
closed to the switching signal traces (UGATE, LGATE,
BOOT, and PHASE).
- The PGND trace should be a separate trace, and independently go to the source of the low-side MOSFETs for
current limit accuracy.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
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APW8868B
Package Information
TQFN3x3-20
D
E
b
A
Pin 1
A1
A3
D2
NX
aaa C
L
K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TQFN3x3-20
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.25
0.006
0.010
A3
0.20 REF
0.008 REF
b
0.15
D
2.90
3.10
0.114
0.122
D2
1.50
1.80
0.059
0.071
E
2.90
3.10
0.114
0.122
E2
1.50
1.80
0.059
0.071
0.50
0.012
e
0.40 BSC
L
0.30
K
0.20
0.016 BSC
0.008
0.08
aaa
0.020
0.003
Note : 1. Followed from JEDEC MO-220 WEEE
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
22
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APW8868B
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN3x3-20
A
H
T1
C
d
D
330±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.00±0.20
4.0±0.10
8.0±0.10
W
E1
12.0±0.30 1.75±0.10
F
5.5±0.05
(mm)
Devices Per Unit
Package Type
TQFN3x3-20
Unit
Tape & Reel
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
Quantity
3000
23
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APW8868B
Taping Direction Information
TQFN3x3-20
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
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APW8868B
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2015
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
25
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW8868B
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
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