APW8868A

APW8868A
DDR2 AND DDR3/DDR3L SYNCHRONOUS BUCK CONTROLLER
WITH 1.5A LDO SUPPORT LOW IQ
Features
General Description
Buck Controller (VDDQ)
•
The APW8868A integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It offers the lowest total
solution cost in system where space is at a premium.
High Input Voltages Range from 3V to 28V Input
Power
•
Provide Adjustable Output Voltage from 0.75V to
5.5V +1% Accuracy over Temperature
•
The APW8868A provides excellent transient response and
accurate DC voltage output in either PFM or PWM Mode.
In Pulse Frequency Mode (PFM), the APW8868A provides
very high efficiency over light to heavy loads with loadingmodulated switching frequencies. On TQFN-20 Package,
the Forced PWM Mode works nearly at constant frequency
for low-noise requirements.
Integrated MOSFET Drivers and Bootstrap Forward
P-CH MOSFET
•
Low Quiescent Current (200µA)
•
Excellent Line and Load Transient Responses
•
PFM Mode for Increased Light Load Efficiency
•
Constant On-Time Controller Scheme
- Switching Frequency Compensation for PWM
Mode
- Adjustable Switching Frequency from 400kHz to
The APW8868A is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections.
A Power-On- Reset function monitors the voltage on VCC
prevents wrong operation during power on.
550kHz in PWM Mode with DC Output Current
•
S3 and S5 Pins Control The Device in S0, S3 or S4/
The LDO is designed to provide a regulated voltage with
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source or
sink current up to 1.5A. It also incorporates current-limit
and thermal shutdown protection.
S5 State
•
Power Good Monitoring
•
70% Under-Voltage Protection (UVP)
•
125% Over-Voltage Protection (OVP)
•
Adjustable Current-Limit Protection
The output voltage of LDO tracks the voltage at VREF pin.
An internal resistor divider is used to provide a half voltage of VREF for VTTREF and VTT Voltage. The VTT output
voltage is only requiring 20µF of ceramic output capacitance for stability and fast transient response. The S3
and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.
- Using Sense Low-Side MOSFET’s RDS(ON)
•
•
TQFN-20 3mmx3mm Thin package
Lead Free Available (RoHS Compliant)
+1.5A LDO Section (VTT)
•
Sourcing or Sinking Current up to 1.5A
•
Fast Transient Response for Output Voltage
•
Output Ceramic Capacitors Support at least 10µF
MLCC
•
VTT and VTTREF Tr ack a t Ha lf the VDDQSNS by
internal divider
•
+20mV Accuracy for VTT and VTTREF
•
Independent Over-Current Limit (OCL)
•
Thermal Shutdown Protection
ANP EC res erves the right to ma ke cha nges to imp rove relia bility or m anufac turab ility witho ut no tice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
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APW8868A
Simplified Application Circuit
Applications
5V
V IN
+3V~28V
VCC
CS
Q1
VDDQ
•
DDR2, and DDR3/DDR3L Memory Power Supplies
•
SSTL-2 SSTL-18 and HSTL Termination
RC S
LOUT
PWM
Q2
DDR
LDO
S3
VTT
VDDQ/2
S5
Ordering and Marking Information
APW8868A
Package Code
QB : TQFN3x3-20
Operating Ambient Temperature Range
I : -40 to 85 °C
Handling Code
TR : Tape & Reel
Lead Free Code
G : Halogen and Lead Free Device
Lead Free Code
Handling Code
Temperature Range
Package Code
APW8868A QB :
APW
8868A
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; w hich
are fully compliant w ith RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-fr ee (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by w eight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
w eight).
PHASE
BOOT
UGATE
LDOIN
VTT
Pin Configuration
20 19 18 17 16
VTTGND 1
15 LGATE
VTTSNS 2
14 PGND
21
PGND
GND 3
13 CS
VTTREF 4
12 VCC
7
8
9
TON
10
PGOOD
6
S5
11 VCC
S3
5
FB
VDDQSNS
= Thermal Pad (connected to GND plane for better heat
dissipation)
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APW8868A
Absolute Maximum Ratings (Note
Symbol
VCC
VBOOT
VBOOT-GND
1,2)
Parameter
Rating
Unit
VCC Supply Voltage (VCC to GND)
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to GND)
-0.3 ~ 35
V
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3
V
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3
V
-5 ~ 35
-0.3 ~ 28
V
-0.3 ~ 0.3
V
-0.3 ~ 7
V
UGATE Voltage (UGATE to PHASE)
<400ns pulse width
>400ns pulse width
LGATE Voltage (LGATE to GND)
<400ns pulse width
>400ns pulse width
PHASE Voltage (PHASE to GND)
<400ns pulse width
>400ns pulse width
PGND, VTTGND and CS_GND to GND Voltage
All Other Pins (CS,S3, S5, VTTSNS, VDDQSNS, VLDOIN, VFB,
PGOOD, VTT, VTTREF GND)
Tj
TSTG
TSDR
Maximum Junction Temperature
o
150
Storage Temperature
C
o
-65 ~ 150
Maximum Soldering Temperature, 10 Seconds
C
o
260
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Note 2: The device is ESD sensitive. Handling precautions are recommended.
Thermal Characteristics (Note
Symbol
3)
Parameter
Typical Value
θJA
Thermal Resistance -Junction to Ambient
50
θJC
Thermal Resistance -Junction to Case
8
Unit
°C/W
°C/W
Note 3: θJA and θJCare measured with the component mounted on a high effective the thermal conductivity test board in free air. The
exposed pad of package is soldered directly on the PCB
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APW8868A
Recommended Operating Conditions (Note
Symbol
Parameter
VCC
VCC Supply Voltage
V IN
Converter Input Voltage
VVDDQ
Converter Output Voltage
V VTT
LDO Output Voltage
IOUT
Converter Output Current
I VTT
LDO Output Current
CVCC
VCC Capacitance
CVTT
CVTTREF
TA
TJ
4)
Range
Unit
4.5 ~ 5.5
V
3 ~ 28
V
0.75 ~5.5V
V
0.375 ~ 2.75
V
0 ~ 15
A
-1.5 ~ +1.5
A
1~
µF
VTT Output Capacitance
10~100
µF
VTTREF Output Capacitance
0.01~0.1
µF
Ambient Temperature
-40 ~ 85
Junction Temperature
-40 ~ 125
o
o
C
C
Note 4: Refer to the typical application circuit.
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APW8868A
Electrical Characteristics
Ref er to the typical applic ation cir cuits . These s pecif ications apply over V VCC=V BOO T =5V, V IN=12V and TA= -40 ~ 85oC, unless
otherw ise specified. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APW8868A
Unit
Min
Typ
Max
-
180
220
µA
-
120
160
µA
µA
SUPPLY CURRENT
IVCC
VCC Supply Current
T A = 25oC, VS3 = V S5 = 5V, no load, VCC Current
o
IVCCSTB
IVCCSDN
ILDOIN
VCC Standby Current
VCC Shutdown Current
LDOIN Supply Current
T A = 25 C, VS3 = 0V, VS5 = 5V, no load, VCC
Current
o
-
0.1
1
o
-
1
10
o
-
0.1
10
o
-
0.1
1
3.95
4.1
4.4
V
-
0.1
-
V
VLDOIN = VVDDQSNS = 1.5V
-
0.75
-
VLDOIN = VVDDQSNS = 1.35V
-
0.675
-
VLDOIN = VVDDQSNS = 1.2V
-
0.6
-
VLDOIN = VVDDQSNS = 1.5V, V VDDQSNS/2 - VVTT,
IVTT = 0A
-20
-
20
VLDOIN = VVDDQSNS = 1.5V, V VDDQSNS/2 - VVTT,
IVTT = 1A
-30
-
30
VLDOIN = VVDDQSNS = 1.35V, VVDDQSNS/2 - VVTT,
IVTT = 0A
-20
-
20
VLDOIN = VVDDQSNS = 1.35V, VVDDQSNS/2 - VVTT,
IVTT = 1A
-30
-
30
VLDOIN = VVDDQSNS = 1.2V, V VDDQSNS/2 - VVTT,
IVTT = 0A
-20
-
20
VLDOIN = VVDDQSNS = 1.2V, V VDDQSNS/2 - VVTT,
IVTT = 1A
-30
-
30
S3 is go high to 0.95*VTT Regulation
25
30
35
T A =25 C, VS3 = VS5 = 0V, no load
T A = 25 C, VS3 = V S5 = 5V, no load
ILDOINSTB LDOIN Standby Current
T A = 25 C, VS3 = 0V, VS5 = 5V, no load,
ILDOINSDN LDOIN Shutdown Current
T A = 25 C, VS3 = V S5 = 0V, no load
µA
POWER-ON-RESET
VCC POR Threshold
VCC Rising
VCC POR Hysteresis
VTT OUTPUT
VVTT
VVTT
T SSVTT
VTT Output Voltage
VTT Output Tolerance
VTT Soft Start Time
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V
mV
µs
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APW8868A
Electrical Characteristics
Ref er to the typical applic ation cir cuits . These s pecif ications apply over V VCC=V BOO T =5V, V IN=12V and TA= -40 ~ 85oC, unless
otherw ise specified. Typical values are at TA=25oC.
Symbol
Parameter
APW8868A
Test Conditions
Unit
Min
Typ
Max
1.2
1.8
2.6
T J=25 C
-1.3
-1.8
-2.6
T J=25o C
1.1
1.8
2.6
T J=25 C
-1.2
-1.8
-2.6
T J=25o C
1
1.8
2.6
-1.05
-1.8
-2.6
-
350
500
-
350
500
-1.0
-
1.0
µA
-1.00
0.01
1.00
µA
15
25
-
mA
V LDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2
-
0.75
-
V LDOIN = VVDDQSNS = 1.35V, VVDDQSNS /2
-
0.675
-
V LDOIN = VVDDQSNS = 1.2V, VVDDQSNS/2
-
0.6
-
-20
-
20
-20
-
20
-20
-
20
VTT OUTPUT
ILIM
Current-Limit
RDS(ON)
VTT Power MOSFETs RDS(ON)
IVTTLK
VTT Leakage Current
IVTTSNSLK VTTSNS Leakage Current
Sourcing Current
(VLDOIN=1.5V)
Sinking Current
(VLDOIN=1.5V)
Sourcing Current
(VLDOIN=1.35V)
Sinking Current
(VLDOIN=1.35V)
Sourcing Current
(VLDOIN=1.2V)
Sinking Current
(VLDOIN=1.2V)
Upper MOSFET
T J=25o C
A
o
A
o
A
o
T J=25 C
Lower MOSFET
V VTT = 1.25V, VS3 = 0V, VS5 = 5V,
o
T A = 25 C
V VTT = 1.25V, T A = 25oC
mΩ
o
IVTTDIS
VTT Discharge Current
V VTT = 0.5V, VS3 = V S5 = 0V, TA = 25 C
V VREF = 0V
VTTREF OUTPUT
VVTTREF
VTTREF Output Voltage
-10mA < IVTTREF < 10mA, V VDDQSNS/2 - V VTTREF
V LDOIN = VVTTREF =1.5V
VTTREF Tolerance
-10mA < IVTTREF < 10mA, V VDDQSNS/2 - V VTTREF
V LDOIN = VVDDQSNS = 1.35V
-10mA < IVTTREF < 10mA, V VDDQSNS/2 - V VTTREF
V LDOIN = VVDDQSNS = 1.2V
V
mV
IVTTREF
VTTREF Source Current
V VTTREF = 0V
-10
-20
-50
mA
IVTTREF
VTTREF Sink Current
V VTTREF = 1.5V
10
20
60
mA
0.745
0.75
0.757
V
VDDQ OUTPUT
T A = 25 oC
o
o
0.7425
0.75
0.7575
V
T A = 25 oC,
V VCC = 4.5V to 5.5V, V IN = 3V to 28V
-0.1
-
+0.1
%
T A = 25 oC,
Load = 0 to 10A, VVCC = 4.5V to 5.5V
-1
-
+1
%
V VFB = 0.78V
-0.1
-
+0.1
µA
V S3 = VS5 = 0V, VVDDQSNS = 0.5V,
15
25
-
mA
T A = -40 C to 85 C
V VFB
VFB Regulation Voltage
VFB Input Current
VDDQ Discharge Current
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APW8868A
Electrical Characteristics
Ref er to the typical applic ation cir cuits . These s pecif ications apply over V VCC=V BOO T =5V, V IN=12V and TA= -40 ~ 85oC, unless
otherw ise specified. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APW8868A
Min
Typ
Max
Unit
PWM CONTROLLERS
FSW
Operating Frequency
Adjustable Frequency
400
-
550
KHz
T SS
Internal Soft Start Time
S5 is High to 0.9*VOUT Regulation
0.77
1.1
1.4
ms
VIN =19V, V VDDQ =1.5V, RTON =620KΩ
175
205
235
ns
-
300
-
ns
Slow on time
80
110
140
ns
Zero-Crossing Threshold
-9.5
0.5
10.5
mV
9
10
11
µA
-
4500
-
ppm/
o
C
-18
0
+18
mV
VDDQ Current Limit Setting Range VVCC-VCS
30
-
200
mV
VDDQ OVP Trip Threshold
VVDDQ Rising
120
125
130
%
VDDQ OVP Debounce Delay
VFB Rising, DV=10mV
PWM CONTROLLERS
TO
Fast on time
T OFF(MIN) Minimum off time
TON(MIN)
VDDQ PROTECTIONS
T A = 25 o C
CS Pin Sink Current
OCP Comparator Offset
VDDQ UVP Trip Threshold
Temperature Coefficient,
On The Basis of 25°C
(VVCC – VCS) – (VPHASE – PGND),
VVCC – V CS = 60mV
-
1.5
-
µs
60
70
80
%
-
10
-
µs
PGOOD in from Lower (PGOOD Goes High)
87
90
93
%
PGOOD in from Higher (PGOOD Goes High)
120
125
130
%
-
0.1
1.0
µA
-
mA
VVDDQ Falling
VDDQ UVP Debounce
PGOOD
VPGOOD
I PGOOD
PGOOD Threshold
PGOOD Leakage Current
VPGOOD=5V
PGOOD Sink Current
VPGOOD=0.3V
2.5
7.5
-
63
-
µs
S5 is High to POK Ready
1.5
2
2.6
ms
PGOOD Debounce Time
T SSPOK
POK Soft Start Time
GATE DRIVERS
UGATE Pull-Up Resistance
BOOT-UGATE=0.5V
-
5
7
Ω
UGATE Sink Resistance
UGATE-PHASE=0.5V
-
1
2.5
Ω
LGATE Pull-Up Resistance
PVCC-LGATE=0.5V
-
5
7
Ω
LGATE Sink Resistance
LGATE-PGND=0.5V
-
1
2.5
Ω
UGATE to LGATE Dead time
UGATE falling to LGATE rising, no load
-
20
-
ns
LGATE to UGATE Dead time
LGATE falling to UGATE rising, no load
-
20
-
ns
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APW8868A
Electrical Characteristics
Ref er to the typical applic ation cir cuits . These s pecif ications apply over V VCC=V BOO T =5V, V IN=12V and TA= -40 ~ 85oC, unless
otherw ise specified. Typical values are at TA=25oC.
Symbol
Parameter
APW8868A
Test Conditions
Unit
Min
Typ
Max
-
0.3
0.5
V
VBOOT = 30V, VPHASE = 25V, V VCC=5V, TA = 25 C
-
-
0.5
µA
2
-
-
V
BOOTSTRAP DIODE
Forward Voltage
Reverse Leakage
o
VVCC – V BOOT, IF = 10mA, TA = 25 C
o
LOGIC THRESHOLD
VIH
S3, S5 High Threshold Voltage
S3, S5 Rising
VIL
S3, S5 Low Threshold Voltage
S3, S5 Falling
-
-
0.8
V
IILEAK
Logic Input Leakage Current
VS3 = V S5 = 5V, TA =25oC
-1
-
1
µA
T J Rising
-
160
-
o
C
-
25
-
o
C
THERMAL SHUTDOWN
TSD
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
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APW8868A
Pin Description
NO.
NAME
1
VTTGND
Power ground output for the VTT LDO.
FUNCTION
2
VTTSNS
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor.
3
GND
4
VTTREF
5
VDDQSNS
6
FB
VTTREF buffered reference output.
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current sinking
terminal for VDDQ non-tracking discharge.
VDDQ output voltage setting pin.
7
S3
S3 signal input.
8
S5
9
TON
10
PGOOD
11, 12
VCC
13
CS
14
PGND
15
LGATE
16
PHASE
17
U GATE
18
BOOT
19
LDOIN
S5 signal input.
This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RTON = 100KΩ ~ 1.2MΩ from
TON pin to PHASE pin.
Power-good output pin. PGOOD is an open drain output used to Indicate the status of the output
voltage. When VDDQ output voltage is within the target range, it is in high state.
5V power s upply voltage input pin for both internal control circuitry and low-side MOSFET gate driver.
Over-current tripvoltage setting input for RDS(ON) current sense scheme if connected to VCC through the
voltage setting resistor.
Power ground of the LGATE low-side MOSFET driver. Connect the pin to the Source of the low-side
MOSFET.
Output of the low-side MOSFET driver for PWM. Connect this pin to Gate of the low-side MOSFET.
Swings from PGND to VCC.
Junction point of the high-side MOSFET Source, output filter inductor and the low-side MOSFET Drain.
Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the
UGATE high-side gate driver.
Output of the high-side MOSFET driver for PWM. Connect this pin to Gate of the high-side MOSFET.
Supply Input for the UGATE Gate Driver and an internal level-shift circuit. Connect to an external
capacitor and diode to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
Supply voltage input for the VTT LDO.
20
VTT
Signal Ground
Power output for the VTT LDO.
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APW8868A
Typical Operating Characteristics
Supply Current In S3 VS Temperature
250
200
225
175
200
Supply Current (uA)
Supply Current (uA)
Supply Current In S0 VS Temperature
175
150
125
100
75
150
125
100
75
50
50
25
25
0
-60 -40 -20
0
0
20
40 60
80 100 120 140 160
-60 -40 -20
0
80 100 120 140 160
On-Time VS Temperature
Shutdown Current VS Temperature
240
1.6
235
1.4
230
1 .2
225
On-Time (ns)
Shutdown Current (uA)
20 40 60
Temperature (℃)
Temperature(℃)
1.0
0.8
0.6
220
215
210
205
200
195
0.4
190
0.2
185
180
-60 -40 -20
0
-60 -40 -20
0
20 40 60
80 100 120 140 160
0
20 40 60
80 100 120 140 160
Temperature (℃)
Temperature (℃)
Reference Voltage VS Temperature
755
Reference Voltage (mV)
754
753
752
751
750
749
748
747
746
745
-60 -40 -20
0
20
40 60
80 100 120 140 160
Temperature (℃)
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APW8868A
Operating Waveforms
Enable S3 – No Load
Enable VCC – No Load
CH2
CH2
CH3
CH3
CH1
CH1
CH4
CH4
CH1:VS3 -5V/div
CH2:VDDQ-1V/div
CH3:VT T-500mV/div
CH4:IL-10A/div
Time:50us/div
CH1:VCC -5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-2A/div
Time:5ms/div
Disable S3/S5 – No Load
OTP
CH2
CH1
CH3
CH2
CH4
CH1
CH3
CH1:VS3/S5-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-1A/div
Time:500us/div
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CH1:VDDQ-1V/div
CH2:VTT -500mV/div
CH3:IL -10A/div
Time:200ms/div
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APW8868A
Operating Waveforms
UVP
Normal Operaion
CH2
CH2
CH3
CH3
CH1
CH1
CH4
CH4
CH1:Phase-2V/div
CH2:VDDQ-1V/div
CH3:VT T-500mV/div
CH4:IL -10A/div
Time:20us/div
CH1:Phase-20V/div
CH2:V DDQ-1V/div
CH3:V TT-500mV/div
CH4:IL -5A/div
Time:2us/div
POK-Enable S3/S5
OCP
CH2
CH2
CH3
CH3
CH1
CH1
CH4
CH4
CH1:Phase-20V/div
CH2:V DDQ-1V/div
CH3:V TT-500mV/div
CH4:I L-10A/div
Time:100us/div
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CH1:POK-5V/div
CH2:VDDQ-1V/div
CH3:VTT -500mV/div
CH4:VS3/S5-5V/div
Time:500us/div
12
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APW8868A
Operating Waveforms
Load Transient-Load=1.2A<-->12A
CH1
CH2
CH1:VDDQ-50mV/div
CH2:I L-5A/div
Time:50us/div
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APW8868A
Block Diagram
0.5 x VDDQ
VDDQSNS
VTTREF
VLDOIN
Thermal
Shutdown
S3
Current Limit
S3,S5 Control Logic
VTT
S5
0.5 x VDDQ +5/10%
VTTSNS
0.5 x VDDQ -5/10%
VTTGND
Non-Tracking
Discharge
VCC
Soft
Start
GND
POR
VCC
VREF
1.25V
Current
Limit
CS
VREF
FB
10uA
125% x VREF
OV
Error
Comparator
BOOT
UGATE
UV
TON
PWM
Signal
Controller
70% x VREF
PHASE
TON
Generator
PHASE
VCC
ZC
LGATE
VREF x
125%/122%
PGOOD
PGND
Delay
VREF x 90%/87%
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APW8868A
Typical Application Circuit
CBOOT
VIN
7V~25V
CIN
0.1uF
Q1
LOUT
PHASE
VDDQ
10uF x 2
1uH
VTT
VDDQ/2
VDDQ
10A
COUT
22uF x 4
(MLCC)
PHASE
UGATE
BOOT
CVTT
10uF x 2
LDOIN
VTT
Q2
LGATE
VTTGND
PGND
VTTSNS
RC S
APW8868A
5.1K, 1%
TQFN-20
VTTREF
VDDQ/2
VCC
CS
VTTREF
VCC
RVCC
VCC
2.2
CVCC
1u F
PGOOD
TON
S5
S3
VDDQSNS
FB
CVTTREF
0.033uF
CPVCC
4.7uF
RPGOOD
PGOOD
RTON
VDDQ
RTOP
75K, 1%
100k
VIN or PHASE
RGND
620K
75K, 1%
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APW8868A
Function Description
The APW8868A integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It provides a complete
power supply for DDR2 and DDR3/DDR3L memory system in a 20-pin TQFN package. User defined output voltage is also possible and can be adjustable from 0.75V to
5.5V. Input voltage range of the PWM converter is 3V to
28V. The converter runs an adaptive on-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiency down to several mA.
The VTT LDO can source and sink up to 1.5A peak current with only 10µF ceramic output capacitor. VTTREF
tracks VDDQ/2 within 1% of VDDQ. VTT output tracks
VTTREF within 20 mV at no load condition while 40 mV at
full load. The LDO input can be separated from VDDQ
and optionally connected to a lower voltage by using
VLDOIN pin. This helps reducing power dissipation in
sourcing phase. The APW8868A is fully compatible to
JEDEC DDR2 and DDR3/DDR3L specifications at S3/
S5 sleep state (see Table 1). When both VTT and VDDQ
are disabled, the non-tracking discharge mode discharges outputs using internal discharge MOSFETs that
are connected to VDDQSNS and VTT.
Both in PFM and PWM, the on-time generator, which
senses input voltage on PHASE pin, provides very fast
on-time response to input line transients.
Another one-shot sets a minimum off-time (typical:
300ns). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time oneshot has timed out.
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
wrong logic co ntrols w hen the VCC voltag e is low . The
POR function continuall y monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set
hi gh. When the ris ing VCC voltage reaches the risi ng
POR voltage threshold (4.1Vtypical), the POR signal goes
high and the chip initiates s oft-start o perations. Should
thi s vo ltage dro p low er than 4 V (typica l), the POR d isables the chip.
Soft- Start
The APW8868Aintegrates digital soft-start circuits to ramp
up the output voltage of the converter to the programmed
regulation set point at a predictable slew rate. The slew
rate of outpu t voltage is inte rnally controlled to limi t the
inrush current through the output capacitors during softs ta rt p ro ce ss . The fig ure 1 s ho ws VDD Q s oft-start
sequence. When the S5 pin is pulled above the rising S5
threshold voltage, the device initiates a soft-start process
to ramp up the output voltage. The soft-start interval is 1.
2ms (typical) and inde pendent of the UGATE switching
frequency.
Constant-On-Time PWM Controller with Input Feed-Forward
The constant on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This architecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
a switching frequency control circuit in the on-time generator block. The switching frequency control circuit
senses the switching frequency of the high-side switch
and keeps regulating it at a constant frequency in PWM
mode. The design improves the frequency variation and
be more outstanding than a conventional constant ontime controller which has large switching frequency variation over input voltage, output current and temperature.
2ms
VCC and VPVCC
1.2ms
VOUT
S5
VPGOOD
Fig1. Soft-Start Sequence
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APW8868A
Function Description (cont.)
Soft- Start (cont.)
Over Voltage Protection (OVP)
During soft-start stage before the PGOOD pin is ready,
the under voltage protection is prohibited. The over voltage and current limit protection functions are enabled. If
the output capacitor has residue voltage before startup,
both low-side and high-side MOSFETs are in off-state
until the internal digital soft start voltage equal the internal feedback voltage. This will ensure the output voltage
starts from its existing voltage level.
The VTT LDO part monitors the output current, both sourcing and sinking current, and limits the maximum output
current to prevent damages during current overload or
short circuit (shorted from VTT to GND or VLDOIN)
conditions.
The VTT LDO provides a soft-start function, using the
constant current to charge the output capacitor that gives
a rapid and linear output voltage rise. If the load current is
above the current limit start-up, the VTT cannot start
successfully.
APW8868A has an independent counter for each output,
but the PGOOD signal indicates only the status of VDDQ
and does not indicate VTT power good externally.
The feedback voltage should increase over 125% of the
reference voltage due to the high-side MOSFET failure or
for other reasons, and the over voltage protection comparator designed with a 1.5 µs noise filter will force the
low-side MOSFET gate driver to be high. This action actively pulls down the output voltage and eventually attempts to blow the battery fuse.
When the OVP occurs, the PGOOD pin will pull down and
latch-off the converter. This OVP scheme only clamps the
voltage overshoot, and does not invert the output voltage
when otherwise activated with a continuously high output
from low-side MOSFET driver. It’s a common problem for
OVP schemes with a latch. Once an over-voltage fault
condition is set, toggling VCC power-on-reset signal can
only reset it.
PWM Converter Current Limit
The current-limit circuit employs a unique “valley” current
sensing algorithm (Figure 2). CS pin should be connected to VCC through the trip voltage-setting resistor,
RCS. CS terminal sinks 10uA current, ICS, and the current
limit threshold is set to the voltage across the R CS. The
voltage between or CS_GND pin and PHASE pin monitors the inductor current so that PHASE pin should be
connected to the drain terminal of the low side MOSFET.
PGND is used as the positive current sensing node so
that PGND should be connected to the proper current
sensing device, i.e. the sense resistor or the source terminal of the low side MOSFET.
If the magnitude of the current-sense signal is above the
current-limit threshold, the PWM is not allowed to initiate
a new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current- limit characteristic and maximum load capability are a function of
the sense resistance, inductor value, and input voltage.
The equation for the current limit threshold is as follows:
Power-Good Output (PGOOD)
PGOOD is an open-drain output and the PGOOD comparator continuously monitors the output voltage. PGOOD
is actively held low in shutdown, and standby. When PWM
converter’s output voltage is greater than 95% of its target value, the internal open-drain device will be pulled
low. After 63µs debounce time, the PGOOD goes high.
The PGOOD goes low if VVDDQ output is 10% below or
above its nominal regulation point.
Under Voltage Protection
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage
will fall out of the required regulation range. The undervoltage continually monitors the setting output voltage
after 2ms of PWM operations to ensure startup. If a load
step is strong enough to pull the output voltage lower
than the under voltage threshold (70% of normal output
voltage), APW8868A shuts down the output gradually and
latches off both high and low side MOSFETs.
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ILIMIT =
17
RCS×10uA ( VIN − VVDDQ) VVDDQ
+
×
RDS(ON)
2 ×L × fsw
VIN
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APW8868A
Function Description (cont.)
PWM Converter Current Limit(cont.)
S3, S5 Control
Where ILIMIT is the desired current limit threshold, R CS is
the value of the current sense resistor connected to VCC
and CS pin VCS is the voltage across the RCS resistor
IRIPPLE is inductor peak to peak current FSW is the PWM
switching frequency.
In a current limit condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. If the output voltage becomes
less than power good level, the VCS is cut into half and the
output voltage tends to be even lower. Eventually, it
crosses the under voltage protection threshold and
shutdown.
In the DDR2 and DDR3/DDR3L memory applications, it
is important to keep VDDQ always higher than VTT/
VTTREF including both start-up and shutdown. The S3
and S5 signals control the VDDQ, VTT, VTTREF states
and these pins should be connected to SLP_S3 and
SLP_S5 signals respectively. The table1 shows the truth
table of the S3 and S5 pins. When both S3 and S5 are
above the logic threshold voltage, the VDDQ, VTT and
VTTREF are turned on at S0 state. When S3 is low and
S5 is high, the VDDQ and VTTREF are kept on while the
VTT voltage is disabled and left high impedance in S3
state. When both S3 and S5 are low, the VDDQ, VTT and
VTTREF are turned off and discharged to the ground.
Table1. The Truth Table of S3 and S5 pins.
INDUCTOR CURRENT
IPEAK
STATE S3
ILIMIT
IVALLEY
0
S5
VDDQ
VTTREF
VTT
1
1
1
1
1
0 (high-Z)
S0
H
H
S3
L
H
S4/5
L
L
0 (discharge) 0 (discharge) 0 (discharge)
Time
Fig2. Current Limit Algorithm
VTT Sink/Source Regulator
The output voltage at VTT pin tracks the reference voltage
applied at VTTREF pin. Two internal N-channel MOSFETs
controlled by separate high bandwidth error amplifiers
regulate the output voltage by sourcing current from
VLDOIN pin or sinking current to GND pin. To prevent two
pass transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error
amplifiers. The VTT with fast response feedback loop
keeps tracking to the VTTREF within +40 mV at all conditions including fast load transient.
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APW8868A
Function Description (cont.)
Thermal Shutdown
A thermal shutdown circuit limits the junction temperature of APW8868A. When the junction temperature exceeds +160oC, PWM converter, VTTLDO and VTTREF are
shut off, allowing the device to cool down. The regulator
regulates the output again through initiation of a new softstart cycle after the junction temperature cools by 25oC ,
resulting in a pulsed output during continuous thermal
overload conditions. The thermal shutdown designed with
a 25oC hysteresis lowers the average junction temperature during continuous thermal overload conditions, extending life time of the device. For normal operation, device power dissipation should be externally limited so
that junction temperatures will not exceed +125oC.
Programming the On-Time Control and PWM Switching Frequency
The APW8868A does not use a clock signal to produce
PWM. The device uses the constant on-time control architecture to produce pseudo-fixed frequency with input
voltage feed-forward. The on-time pulse width is proportional to output voltage VDDQ and inverse proportional to
input voltage VIN. In PWM, the on-time calculation is written as below equation.
 2 × VVDDQ
T ON = 6 . 3 × 10 −1 2 × RTON ×  3
VIN






Where:
RTON is the resistor connected from TON pin to PHASE
pin. Furthermore, The approximate PWM switching frequency is written as:
TON =
D
V OUT / V IN
= FSW =
FSW
T ON
Where:
FSW is the PWM switching frequency
APW8868A doesn’t have VIN pin to calculate on-time
pulse width. Therefore, monitoring VPHASE voltage as input voltage to calculate on-time when the high-side
MOSFET is turned on. And then, use the relationship between on-time and duty cycle to obtain the switching
frequency.
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APW8868A
Application Information (cont.)
Output Voltage Selection
PWM can be also adjusted from 0.75V to 5.5V with a
resistor-driver at FB between VDDQSNS and GND. Using 1% or better resistors for the resistive divider is
recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.75V. Take
the example, the output voltage of PWM is determined by:


R
V OUT= 0.75 × 1 + TOP 
 R GND 
Where R TOP is the resistor connected from VOUT to FB and
RGND is the resistor connected from FB to GND.
Output Inductor Selection
The duty cycle of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
is fixed, it can be written as:
D=
The inductor value determines the inductor ripple current
and affects the load transient response. Higher inductor
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
Output voltage ripple and the transient voltage deviation
are factors that have to be taken into consideration when
selecting an output capacitor. Higher capacitor value and
lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low
ESR capacitors is intended for switching regulator
applications. In addition to high frequency noise related
MOSFET turn-on and turn-off, the output voltage ripple
includes the capacitance voltage drop and ESR voltage
drop caused by the AC peak-to-peak current. These two
voltages can be represented by:
IRIPPLE
8COUTFSW
∆VESR = IRIPPLE × RESR
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR
and suppress the voltage ripple to a tolerable level. A
small decoupling capacitor in parallel for bypassing the
noise is also recommended, and the voltage rating of the
output capacitors must also be considered.
To support a load transient that is faster than the switching frequency, more capacitors have to be used to reduce the voltage excursion during load step change. Another aspect of the capacitor selection is that the total AC
current going through the capacitors has to be less than
the rated RMS current specified on the capacitors to prevent the capacitor from over-heating.
VIN − VOUT VOUT
×
FSW × L
VIN
Where FSW is the switching frequ ency of the re gulator.
Alth ough increase the inductor valu e and frequency reduce th e rip ple curre nt an d vo ltage , th ere i s a trade off
betw een the inductor’s rippl e curre nt and the regul ator
load transient response time.
A s mall er i nductor w ill give the reg ulato r a faster l oad
transient response at the expense of higher ripple current.
Increasing the switching frequency (FSW ) a lso redu ces
th e ripp le curren t and vol tage , b ut it wil l i ncreas e the
switch ing loss o f the MOSFETs and th e power di ssipation of the converter. The maximum ripple current occurs
at the maximum input voltage. A good starting point is to
choose the ripple current to be approximately 30% of the
maximum output current. Once the inductance value has
been chosen, selecting an inductor is capable of carrying
the required peak current without going into saturation.
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Output Capacitor Selection
∆VCOUT =
VOUT
VIN
IRIPPLE =
In some types of inductors, especially core that is made
of ferrite, the ripple current will increase a bruptly when it
sa tura tes . Th is wil l be re sult in a l arg er outp ut ripp le
voltage.
20
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APW8868A
Application Information (cont.)
Input Capacitor Selection
Phigh-side = IOUT 2(1+TC)(RDS(ON))D+(0.5)(IOUT )(VIN)(tSW )FSW
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation,
select the capacitor voltage rating to be at least 1.3 times
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT /2,
where IOUT is the load current. During power up, the input
capacitors have to handle large amount of surge current.
In low-duty notebook applications, ceramic capacitors are
recommended. The capacitors must be connected between the drain of high-side MOSFET and the source of
low-side MOSFET with very low-impedance PCB layout.
MOSFET Selection
The application for a notebook battery with a maximum
voltage of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with
the R DS(ON) of the MOSFET:
- For the low-side MOSFET, before it is turned on, the
body diode has been conducted. The low-side MOSFET
driver will not charge the miller capacitor of this MOSFET.
- In the turning off process of the low-side MOSFET, the
load current will shift to the body diode first. The high dv/
dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the
low-side MOSFETs. The duty cycle is often very small in
high battery voltage applications, and the low-side
MOSFET will conduct most of the switching cycle;
therefore, the R DS(ON) of the low-side MOSFET, the less
the power loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFET
does not have this zero voltage switching condition, and
because it conducts for less time compared to the lowside MOSFET, the switching loss tends to be dominant.
Priority should be given to the MOSFETs with less gate
charge, so that both the gate driver loss and switching
loss will be minimized.
The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capacitance
(CRSS) and maximum output current requirement. The
losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and lowside MOSFETs, the losses are approximately given by
the following equations:
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Plow-side = IOUT 2(1+TC)(RDS(ON))D(1-D)
Where
I is the load current
TC is the temperature dependency of R DS(ON)
FSW is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transition
loss. The switching internal, t SW , is the function of the
reverse transfer capacitance C RSS. The (1+TC) term is to
factor in the temperature dependency of the R DS(ON) and
can be extracted from the “R DS(ON) vs Temperature” curve
of the power MOSFET.
Layout Consideration
In any high switching frequency converter, a correct layout is important to ensure proper operation of the
regulator. With power devices switching at higher
frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and
parasitic circuit elements. As an example, consider the
turn-off transition of the PWM MOSFET. Before turn-off
condition, the MOSFET is carrying the full load current.
During turn-off, current stops flowing in the MOSFET and
is freewheeling by the lower MOSFET and parasitic diode.
Any parasitic inductance of the circuit generates a large
voltage spike during the switching interval. In general,
using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of
voltage spike. And signal and power grounds are to be
kept separating and finally combined to use the ground
plane construction or single point grounding. The best
tie-point between the signal ground and the power ground
is at the negative side of the output capacitor on each
channel, where there is less noise. Noisy traces beneath
the IC are not recommended. Below is a checklist for
your layout:
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APW8868A
Application Information (cont.)
Layout Consideration
3mm
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0.5mm *
0.2mm
1.66 mm
- Keep the switching nodes (UGATE, LGATE, BOOT, and
PHASE) away from sensitive small signal nodes(VFB,
VTTREF, and CS) since these nodes are fast moving
signals. Therefore, keep traces to these nodes as short
as possible and there should be no other weak signal
traces in parallel with theses traces on any layer.
- The signals going through theses traces have both high
dv/dt and high di/dt, with high peak charging and discharging current. The traces from the gate drivers to the
MOSFETs (UGATE and LGATE) should be short and wide.
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
- Decoupling capacitor, the resistor dividers, boot
capacitors, and current limit stetting resistor should be
close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET
as close as possible. The bulk capacitors are also placed
near the drain).
- The input capacitor should be near the drain of the upper MOSFET; the high quality ceramic decoupling capacitor can be put close to the VCC and GND pins; the VTTREF
decoupling capacitor should be close to the VTTREF pin
and GND; the VDDQ and VTT output capacitors should
be located right across their output pin as close as possible to the part to minimize parasitic. The input capacitor
GND should be close to the output capacitor GND and
the lower MOSFET GND.
- The drain of the MOSFETs (VIN and PHASE nodes)
should be a large plane for heat sinking. And PHASE pin
traces are also the return path for UGATE. Connect this
pin to the converter’s upper MOSFET source.
- The APW8868A used ripple mode control. Build the resistor divider close to the VFB pin so that the high impedance trace is shorter. And the VFB pin traces can’t be
closed to the switching signal traces (UGATE, LGATE,
BOOT, and PHASE).
- The PGND trace should be a separate trace, and independently go to the source of the low-side MOSFETs for
current limit accuracy.
3mm
0.4mm
1.66 mm
0.17mm
0.5mm
TQFN 3x3-20
* Just Recommend
Figure3. Recommended Minimum Footprint
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APW8868A
Package Information
TQFN3x3-20
D
E
b
A
Pin 1
A1
A3
D2
NX
aaa C
L
K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TQFN3x3-20
MILLIMETERS
INCHES
MIN .
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.25
0.006
0.010
0.122
A3
b
0.20 REF
0.15
0.008 REF
D
2.90
3.10
0.114
D2
1.50
1.80
0.059
0.071
E
2.90
3.10
0.114
0.122
E2
1.50
1.80
0.059
0.071
0.50
0.012
e
0.40 BSC
L
0.30
K
0.20
0.016 BSC
0.008
0.08
aaa
0.020
0.003
Note : 1. Followed from JEDEC MO-220 WEEE
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APW8868A
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN3x3-20
A
H
T1
C
d
D
330±
2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±
0.20
3.30±
0.20
1.00±0.20
4.0±0.10
8.0±
0.10
W
E1
12.0±
0.30 1.75±0.10
F
5.5±0.05
(mm)
Devices Per Unit
Package Type
TQFN3x3-20
Unit
Tape & Reel
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Quantity
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APW8868A
Taping Direction Information
TQFN3x3-20
USER DIRECTION OF FEED
Classification Profile
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APW8868A
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
20** seconds
30** seconds
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin )
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (T L)
Time at liquidous (tL)
Peak package body Temperature
(Tp )*
Time (t P)** within 5 °C of the specified
classification temperature (Tc)
Average ramp-down rate (T p to Tsmax)
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp ) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
C opyright  ANPEC Electronics C orp.
Rev. A.2 - Sep., 2015
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
26
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150 °C
VHBM≧2KV
VMM ≧200V
10ms, 1 tr ≧100mA
www.anpec.com.tw
APW8868A
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
C opyright  ANPEC Electronics C orp.
Rev. A.2 - Sep., 2015
27
www.anpec.com.tw