PIC12F752/HV752 Flash Memory Programming Specification 1.0 DEVICE OVERVIEW 2.0 This document includes the programming specifications for the following devices: • PIC12F752 PROGRAMMING THE PIC12F752/HV752 DEVICES The PIC12F752/HV752 devices are programmed using a serial method. The Serial mode will allow these devices to be programmed while in the user’s system. These programming specifications apply to all of the above devices in all packages. • PIC12HV752 Note 1: All references to the PIC12F752 parts refer to the PIC12HV752 parts as well (unless otherwise specified). 2.1 Hardware Requirements These devices require one power supply for VDD, see Table 7-1 VDD, and one for VPP, see Table 7-1 VIHH. 2.2 Program/Verify Mode The Program/Verify mode for these devices allows programming of user program memory, user ID locations, Calibration Word and the Configuration Word. TABLE 2-1: Pin Name 8-PIN PROGRAMMING PIN DIAGRAM FOR PIC12F752/HV752 VDD 1 RA5 2 RA4 3 MCLR/VPP/RA3 4 PIC12F752/HV752 FIGURE 2-1: 8 VSS 7 RA0/ICSPDAT 6 RA1/ICSPCLK 5 RA2 PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE: PIC12F752/HV752 During Programming Function Pin Type RA1 ICSPCLK I RA0 ICSPDAT I/O Pin Description Clock input – Schmitt Trigger input Data input/output – Schmitt Trigger input Program/Verify mode P(1) VDD VDD P Power Supply VSS VSS P Ground MCLR Program Mode Select Legend: I = Input, O = Output, P = Power Note 1: In the PIC12F752/HV752, the programming high voltage is internally generated. To activate the Program/ Verify mode, voltage of VIHH and a current of IIHH (see Table 7-1) need to be applied to MCLR input. 2011-2012 Microchip Technology Inc. Advance Information DS41561C-page 1 PIC12F752/HV752 3.0 MEMORY DESCRIPTION 3.1 Program Memory Map The user memory space extends from 0x0000 to 0x1FFF. In Program/Verify mode, the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The Program Counter (PC) will increment from 0x0000 to 0x1FFF and wrap to 0x0000. If the PC is between 0x2000 to 0x3FFF it will wrap-around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a ‘1’, thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter Program/Verify mode as described in Section 4.0 “Program/Verify Mode”. 3.3 Calibration Words For all of the devices covered in this document, the 1/4/8 MHz Internal Oscillator (HFINTOSC) module and band gap are factory calibrated. This value is stored in the Calibration Words (0x2008 and 0x2009). See the applicable device data sheet for more information. The Calibration Words do not necessarily participate in the erase operation unless a specific procedure is executed. Therefore, the device can be erased without affecting the Calibration Words. This simplifies the erase procedure since these values do not need to be read and restored after the device is erased. For all of the devices covered in this document, the configuration memory space, 0x2000 to 0x2009, is physically implemented. However, only locations 0x2000 to 0x2003, 0x2007 to 0x2009 are available. Other locations are reserved. 3.2 User ID Locations A user may store identification information (user ID) in four designated locations. The user ID locations are mapped in 0x2000 to 0x2003. It is recommended that the user use only the seven Least Significant bits (LSbs) of each user ID location. The user ID locations read out normally, even after code protection is enabled. It is recommended that ID locations are written as ‘xx xxxx xbbb bbbb’ where ‘bbb bbbb’ is the user ID information. The 14 bits may be programmed, but only the 7 LSbs are read and displayed by MPLAB® IDE. DS41561C-page 2 Advance Information 2011-2012 Microchip Technology Inc. PIC12F752/HV752 FIGURE 3-1: PIC12F752/HV752 PROGRAM MEMORY MAPPING 1 KW Implemented 03FF Program Memory 2000 User ID Location 2001 User ID Location 2002 User ID Location 2003 User ID Location 2004 Reserved 2005 Reserved 2006 Device ID 2007 Configuration Word 2008 Calibration Word 2009 Calibration Word 200A-207F 2011-2012 Microchip Technology Inc. Maps to 0-7FF 1FFF 2000 Implemented 2080 Maps to 2000-203F Configuration Memory 2FFF Reserved Advance Information DS41561C-page 3 PIC12F752/HV752 4.0 PROGRAM/VERIFY MODE Two methods are available to enter Program/Verify mode. “VPP-first” is entered by holding ICSPDAT and ICSPCLK low while raising the MCLR pin from VIL to VIHH (high voltage), then applying VDD and data. This method can be used for any Configuration Word selection and must be used if the INTOSC and internal MCLR options are selected (FOSC<2:0> = 100 or 101 and MCLRE = 0). The VPP-first entry prevents the device from executing code prior to entering Program/ Verify mode. See the timing diagram in Figure 4-1. The second entry method, “VDD-first”, is entered by applying VDD, holding ICSPDAT and ICSPCLK low, then raising MCLR pin from VIL to VIHH (high voltage), followed by data. This method can be used for any Configuration Word selection except when INTOSC and internal MCLR options are selected (FOSC<2:0> = 100 or 101 and MCLRE = 0). This technique is useful when programming the device when VDD is already applied, for it is not necessary to disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 4-2. FIGURE 4-2: THLD0 To prevent a device configured with INTOSC and internal MCLR from executing after exiting Program/ Verify mode, VDD needs to power down before VPP. See Figure 4-3 for the timing. FIGURE 4-1: VPP-FIRST PROGRAM/ VERIFY MODE ENTRY TPPDP THLD0 VDD ICSPDAT ICSPCLK Note: FIGURE 4-3: This method of entry is valid if INTOSC and internal MCLR are not selected. PROGRAM/VERIFY MODE EXIT THLD0 VPP VDD ICSPDAT ICSPCLK 4.1 Program/Erase Algorithms The PIC12F752/HV752 program memory may be written in two ways. The fastest method writes four words at a time. However, one-word writes are also supported for backward compatibility with previous 8-pin and 14-pin Flash devices. The four-word algorithm is used to program the program memory only. The oneword algorithm can write any available memory location (i.e., program memory, configuration memory and calibration memory). After writing the array, the PC may be reset and read back to verify the write. It is not possible to verify immediately following the write because the PC can only increment, not decrement. VPP VDD ICSPDAT ICSPCLK Note: TPPDP VPP Once in Program/Verify mode, the program memory and configuration memory can be accessed and programmed in serial fashion. ICSPDAT and ICSPCLK are Schmitt Trigger inputs in this mode. RA4 is tri-state regardless of fuse setting. The sequence that enters the device into the Program/ Verify mode places all other logic into the Reset state (the MCLR pin was initially at VIL). Therefore, all I/Os are in the Reset state (high-impedance inputs) and the PC is cleared. VDD-FIRST PROGRAM/ VERIFY MODE ENTRY This method of entry is valid, regardless of Configuration Word selected. DS41561C-page 4 A device Reset will clear the PC and set the address to ‘0’. The Increment Address command will increment the PC. The Load Configuration command will set the PC to 0x2000. The available commands are shown in Table 4-1. Advance Information 2011-2012 Microchip Technology Inc. PIC12F752/HV752 4.1.1 FOUR-WORD PROGRAMMING The PIC12F752/HV752 program memory can be written four words at a time using the four-word algorithm. Configuration memory (addresses >0x2000) and non-aligned (addresses modulo 4 not equal to zero) starting addresses must use the one-word programming algorithm. This algorithm writes four sequential addresses in program memory. The four addresses must point to a four-word block which address modulo 4 of 0, 1, 2 and 3. For example, programming address 4 through 7 can be programmed together. Programming addresses 2 through 5 will create an unexpected result. 4.1.2 ERASE ALGORITHMS The PIC12F752/HV752 devices will erase different memory locations depending on the PC and CP. The following sequences can be used to erase noted memory locations. To erase the program memory and Configuration Word (0x2007), the following sequence must be performed. Note that the Calibration Words (0x2008 and 0x2009) and User ID (0x2000-0x2003) will not be erased. 1. 2. Do a Bulk Erase Program Memory command. Wait TERA to complete erase. The sequence for programming four words of program memory at a time is: To erase the User ID (0x2000-0x2003), Configuration Word (0x2007) and program memory, use the following sequence. Note that the Calibration Words (0x2008 and 0x2009) will not be erased. 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Load a word at the current program memory address using the Load Data For Program Memory command. This location must be address modulo 4 equal to 0. Issue an Increment Address command to point to the next address in the block. Load a word at the current program memory address using the Load Data For Program Memory command. Issue an Increment Address command to point to the next address in the block. Load a word at the current program memory address using the Load Data For Programming Memory command. Issue and Increment Address command to point to the next address in the book. Load a word at the current program memory address using the Load Data For Programming Memory command. Issue a Begin Programming command externally timed. Wait TPROG1. Issue End Programming. Wait TDIS. Issue an Increment Address command to point to the start of the next block of addresses. Repeat steps 1 through 12 as required to write the desired range of program memory. See Figure 4-12 for more information. 2. 3. Perform Load Configuration with dummy data to point the PC to 0x2000. Perform a Bulk Erase Program Memory command. Wait TERA to complete erase. 4.1.3 SERIAL PROGRAM/VERIFY OPERATION The ICSPCLK pin is used as a clock input and the ICSPDAT pin is used for entering command bits and data input/output during serial operation. To input a command, ICSPCLK is cycled six times. Each command bit is latched on the falling edge of the clock with the LSb of the command being input first. The data input onto the ICSPDAT pin is required to have a minimum setup and hold time (see Table 7-1), with respect to the falling edge of the clock. Commands that have data associated with them (Read and Load) are specified to have a minimum delay of 1 s between the command and the data. After this delay, the clock pin is cycled 16 times with the first cycle being a Start bit and the last cycle being a Stop bit. During a read operation, the LSb will be transmitted onto the ICSPDAT pin on the rising edge of the second cycle. For a load operation, the LSb will be latched on the falling edge of the second cycle. A minimum 1 s delay is also specified between consecutive commands, except for the End Programming command, which requires a 100 s (TDIS). All commands and data words are transmitted LSb first. Data is transmitted on the rising edge and latched on the falling edge of the ICSPCLK. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s (TDLY1) is required between a command and a data word. The commands that are available are described in Table 4-1. 2011-2012 Microchip Technology Inc. Advance Information DS41561C-page 5 PIC12F752/HV752 TABLE 4-1: COMMAND MAPPING FOR PIC12F752/HV752 Command Mapping (MSb … LSb) Load Configuration x x 0 0 Data 0 0, data (14), 0 0 Load Data for Program Memory x x 0 0 1 0 0, data (14), 0 Read Data from Program Memory x x 0 1 0 0 0, data (14), 0 Increment Address x x 0 1 1 0 Begin Programming x 1 1 0 0 0 End Programming x 0 1 0 1 0 Bulk Erase Program Memory x x 1 0 0 1 Internally Timed Row Erase Program Memory x 1 0 0 0 1 Internally Timed 4.1.3.1 Externally Timed Load Configuration The Load Configuration command is used to access the Configuration Word (0x2007), User ID (0x20000x2003) and Calibration Words (0x2008 and ox2009). This command sets the PC to address 0x2000 and loads the data latches with one word of data. To access the configuration memory, send the Load Configuration command. Individual words within the configuration memory can be accessed by sending Increment Address commands and using load or read data for program memory. After the 6-bit command is input, the ICSPCLK pin is cycled an additional 16 times for the Start bit, 14 bits of data and the Stop bit (see Figure 4-4). After the configuration memory is entered, the only way to get back to the program memory is to exit the Program/Verify mode by taking MCLR low (VIL). FIGURE 4-4: LOAD CONFIGURATION COMMAND TDLY3 1 2 3 4 5 0 0 X 6 1 2 3 4 5 15 16 ICSPCLK ICSPDAT 0 00 X strt_bit TDLY1 LSb MSb stp_bit TSET1 THLD1 DS41561C-page 6 Advance Information 2011-2012 Microchip Technology Inc. PIC12F752/HV752 4.1.3.2 Load Data For Program Memory After receiving this command, the chip will load in a 14-bit “data word” when 16 cycles are applied, as described in Section 4.1.3.1 “Load Configuration”. A timing diagram of this command is shown in Figure 4-5. FIGURE 4-5: LOAD DATA FOR PROGRAM MEMORY COMMAND 1 2 3 4 5 0 0 X 6 TDLY2 1 2 3 4 5 15 16 ICSPCLK 1 0 ICSPDAT TSET1 strt_bit X LSb MSb THLD1 4.1.3.3 stp_bit TSET1 TDLY1 THLD1 Read Data From Program Memory After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently accessed, starting with the second rising edge of the clock input. The data pin will go into Output mode on the second rising clock edge, and it will revert to Input mode (high-impedance) after the 16th rising edge. If the program memory is code-protected (CP = 0), the data is read as zeros. A timing diagram of this command is shown in Figure 4-6. FIGURE 4-6: READ DATA FROM PROGRAM MEMORY COMMAND TDLY3 1 2 3 4 5 1 0 6 1 2 3 ICSPCLK ICSPDAT 4 5 15 16 TDLY3 1 0 0 X X strt_bit TSET1 THLD1 stp_bit TDLY1 input 2011-2012 Microchip Technology Inc. MSb LSb output Advance Information input DS41561C-page 7 PIC12F752/HV752 4.1.3.4 Increment Address The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 4-7. It is not possible to decrement the address counter. To reset this counter, the user should exit and re-enter Program/Verify mode. FIGURE 4-7: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) TDLY2 1 2 3 4 5 Next Command 1 6 2 ICSPCLK 0 ICSPDAT 1 0 1 X X X 0 TSET1 THLD1 4.1.3.5 TDLY1 Begin Programming (Externally Timed) A Load command must be given before every Begin Programming command. Programming of the appropriate memory (program memory, configuration or calibration memory) will begin after this command is received and decoded. Programming requires (TPROG) time and is terminated using an End Programming command. A timing diagram for this command is shown in Figure 4-8. The addressed locations are not erased before programming. FIGURE 4-8: BEGIN PROGRAMMING (EXTERNALLY TIMED) VIHH TPROG MCLR End Programming Command 1 2 3 0 0 0 4 5 6 1 2 ICSPCLK ICSPDAT 1 1 X X 0 TSET1 THLD1 DS41561C-page 8 Advance Information 2011-2012 Microchip Technology Inc. PIC12F752/HV752 4.1.3.6 End Programming After this command is performed, the write procedure will stop. A timing diagram of this command is shown in Figure 4-9. FIGURE 4-9: END PROGRAMMING (SERIAL PROGRAM/VERIFY) VIHH MCLR Next Command 1 2 3 0 1 0 4 5 1 6 2 ICSPCLK ICSPDAT 1 0 X X TDIS 0 TSET1 THLD1 4.1.3.7 Bulk Erase Program Memory After this command is performed, the entire program memory and Configuration Word (0x2007) is erased. The user ID and calibration memory may also be erased, depending on the value of the PC. See Section 4.1.2 “Erase Algorithms” for erase sequences. A timing diagram for this command is shown in Figure 4-10. FIGURE 4-10: BULK ERASE PROGRAM MEMORY COMMAND TERA 1 2 3 0 0 4 5 6 Next Command 1 2 ICSPCLK 1 ICSPDAT X X X 0 TSET1 TSET1 THLD1 2011-2012 Microchip Technology Inc. 1 THLD1 Advance Information DS41561C-page 9 PIC12F752/HV752 4.1.3.8 Row Erase Program Memory This command erases the 16-word row of program memory pointed to by PC<11:4>. If the program memory array is protected (CP = 0) or the PC points to the configuration memory (>0x2000), the command is ignored. To perform a Row Erase Program Memory, the following sequence must be performed. 1. 2. Execute a Row Erase Program Memory command. Wait TERA to complete a row erase. FIGURE 4-11: ROW ERASE PROGRAM MEMORY COMMAND TERA 1 2 3 1 0 0 4 5 Next Command 1 6 2 ICSPCLK ICSPDAT DS41561C-page 10 0 1 Advance Information x x 0 2011-2012 Microchip Technology Inc. PIC12F752/HV752 FIGURE 4-12: FOUR-WORD PROGRAMMING FLOWCHART (PIC12F752/HV752) Program Cycle Load Data for Program Memory Increment Address Command Start Bulk Erase Program Memory(1,2) Increment Address Command No Load Data for Program Memory Four-word Program Cycle Increment Address Command All Locations Done? Load Data for Program Memory Yes Increment Address Command Program User ID/Config. bits Load Data for Program Memory Done Begin Programming Command (Externally timed) Wait TPROG End Programming Wait TDIS Note 1: 2: This step is optional if the device is erased or not previously programmed. If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 4-14. 2011-2012 Microchip Technology Inc. Advance Information DS41561C-page 11 PIC12F752/HV752 FIGURE 4-13: PROGRAM FLOWCHART – CONFIGURATION MEMORY Start PROGRAM CYCLE Load Configuration Load Data for Program Memory One-word Program Cycle (User ID) Begin Programming Command (Externally timed) Read Data From Program Memory Command Wait TPROG Data Correct? No Report Programming Failure End Programming Yes Increment Address Command Wait TDIS No Address = 0x2004? Yes Increment Address Command Increment Address Command Increment Address Command One-word Program Cycle (Config. bits) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Done DS41561C-page 12 Advance Information 2011-2012 Microchip Technology Inc. PIC12F752/HV752 FIGURE 4-14: PROGRAM FLOWCHART – ERASE FLASH DEVICE Start Load Configuration Bulk Erase(1) Program Memory Done Note 1: See Section 4.1.3.7 “Bulk Erase Program Memory” for more information on the Bulk Erase procedure. 2011-2012 Microchip Technology Inc. Advance Information DS41561C-page 13 PIC12F752/HV752 5.0 CONFIGURATION WORD The Configuration bits select various oscillator, reset, power and memory protection options. REGISTER 5-1: CONFIGURATION WORD FOR PIC12F752 R/P-1 R/P-1 DEBUG CLKOUTEN R/P-1 R/P-1 R/P-1 WRT<1:0> R/P-1 BOREN<1:0> bit 13 bit 8 U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 — CP MCLRE PWRTE WDTE — — bit 7 R/P-1 FOSC0 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 DEBUG: Debug Mode Enable bit(2) 1 = Background debugger is disabled 0 = Background debugger is enabled bit 12 CLKOUTEN: Clock Out Enable bit 1 = Clock out function disabled. CLKOUT pin acts as I/O pin 0 = Clock out function enabled. CLKOUT pin acts as CLKOUT bit 11-10 WRT<1:0>: Flash Program Memory Self Write Enable bit 11 = Write protection off 10 = 000h to FFh write-protected, 100h to 3FFh may be modified by PMCON1 control 01 = 000h to 1FFh write-protected, 200h to 3FFh may be modified by PMCON1 control 00 = 000h to 3FFh write-protected, entire program is write-protected bit 8-9 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 0x = BOR disabled bit 7 Unimplemented: Read as ‘1’. bit 6 CP: Code Protection bit 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: MCLR/VPP Pin Function Select bit 1 = MCLR pin is MCLR function and weak internal pull-up is enabled 0 = MCLR pin is input function, MCLR function is internally disabled bit 4 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-1 Unimplemented: Read as ‘1’. bit 0 FOSC0: Oscillator Selection bits 1 = EC oscillator selected: CLKIN on RA5/CLKIN 0 = Internal oscillator: I/O function on RA5/CLKIN Note 1: 2: Enabling Brown-out Reset does not automatically enable Power-up Timer. The DEBUG bit is managed automatically by the device development tools. DS41561C-page 14 Advance Information 2011-2012 Microchip Technology Inc. PIC12F752/HV752 5.1 Device ID Word The device ID word for the PIC12F752/HV752 is loaded at 2006h. This location can not be erased. TABLE 5-1: Device DEVICE ID VALUES Device ID Values Dev Rev PIC12F752 01 0101 000 x xxxx PIC12HV752 01 0101 001 x xxxx 2011-2012 Microchip Technology Inc. Advance Information DS41561C-page 15 PIC12F752/HV752 6.0 CODE PROTECTION 6.3 For the PIC12F752/HV752 devices, once the CP bit is programmed to ‘0’, all program memory locations read all ‘0’s. The user ID locations and the Configuration Word read out in an unprotected fashion. Further programming is disabled for the entire program memory. The user ID locations and the Configuration Word can be programmed regardless of the state of the CP bit. 6.1 Disabling Code Protection It is recommended to use the procedure in Figure 4-14 to disable code protection of the device. This sequence will erase the program memory, Configuration Word (0x2007) and user ID locations (0x2000-0x2003). The Calibration Words (0x2008 and 0x2009) will not be erased. 6.2 Embedding Configuration Word and User ID Information in the Hex File To allow portability of code, the programmer is required to read the Configuration Word and user ID locations from the hex file when loading the hex file. If Configuration Word information was not present in the hex file, a simple warning message may be issued. Similarly, while saving a hex file, Configuration Word and user ID information must be included. An option to not include this information may be provided. Microchip Technology Incorporated feels strongly that this feature is important for the benefit of the end customer. DS41561C-page 16 Checksum Computation 6.3.1 CHECKSUM Checksum is calculated by reading the contents of the program memory locations and adding up the opcodes up to the maximum user addressable location (e.g., 0x3FF for the PIC12F752). Any carry bits exceeding 16 bits are neglected. Finally, the Configuration Word (appropriately masked) is added to the checksum. The checksum computation for the PIC12F752/HV752 devices is shown in Example 6-1, Example 6-2 and Example 6-3. The checksum is calculated by summing the following: • The contents of all program memory locations • The Configuration Word, appropriately masked • Masked user ID locations (when applicable) The Least Significant 16 bits of this sum is the checksum. Example 6-1, Example 6-2 and Example 6-3 describe how to calculate the checksum for the PIC12F752 and PIC12HV752 devices. Note that the checksum calculation differs depending on the code-protect setting. Since the program memory locations read out zeroes when code-protected, the examples describe how to manipulate the actual program memory values to simulate values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The Configuration Word and user ID locations can always be read regardless of code-protect setting. Note: Advance Information Some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. 2011-2012 Microchip Technology Inc. PIC12F752/HV752 EXAMPLE 6-1: PIC12F752 CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED (CP = 1) PIC12F752, BLANK DEVICE Sum of Memory addresses 0000h-3FFh(1) FC00h (2) 3FFFh Configuration Word Configuration Word mask(3) Checksum 3F79h = FC00h + (3FFFh and 3F79h) = FC00h + 3F79h = 3B79h(4) Note 1: This value is obtained by taking the total number of program memory locations (0x000 to 0x03FF which is 400h) and multiplying it by the blank memory value of 0x3FFF to get the sum of FF FC00h. Then truncate to 16 bits, thus having a final value of FC00h. 2: This value is obtained by making all bits of the Configuration Word a ‘1’, then converting it to hex, thus having a value of 3FFFh. 3: This value is obtained by making all used bits of the Configuration Word a ‘1’, then converting it to hex, thus having a value of 3F79h. 4: This value is obtained by ANDing the Configuration Word value with the Configuration Word Mask value and adding it to the Sum of memory addresses (3FFFh and 3F79h) + FC00h = 1 3B79h. Then truncate to 16 bits, thus having a final value of 3B79h. EXAMPLE 6-2: PIC12F752 CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED (CP = 1) PIC12F752, 25E6h AT FIRST AND LAST ADDRESS Sum of Memory addresses 0000h-3FFh(1) C7CEh Configuration Word(2) 3FFFh Configuration Word mask Checksum (3) 3F79h = C7CEh + (3FFFh and 3F79h) = C7CEh + 3F79h = 0747h(4) Note 1: This value is obtained by taking the total number of program memory locations (0x000 to 0x03FF which is 400h) subtracting 2h which yields 3FEh, then multiply it by the blank memory value of 0x3FFF to get the sum of FF 7C02h. Then truncate to 16 bits value of 7C02h. Now add 4BCCh (25E6h + 25E6h) to 7C02h to get the final value of C7CEh. 2: This value is obtained by making all bits of the Configuration Word a ‘1’, then converting it to hex, thus having a value of 3FFFh. 3: This value is obtained by making all used bits of the Configuration Word a ‘1’, then converting it to hex, thus having a value of 3F79h. 4: This value is obtained by ANDing the Configuration Word value with the Configuration Word Mask value and adding it to the sum of memory addresses (3FFFh and 3F79h) + C7CEh = 0747h. 2011-2012 Microchip Technology Inc. Advance Information DS41561C-page 17 PIC12F752/HV752 EXAMPLE 6-3: PIC12F752 CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED (CP = 0) PIC12F752 Configuration Word 3F7Fh(1) Configuration Word mask 3F39h(2) User ID (2000h) 0005h(3) User ID (2001h) 0007h(3) User ID (2002h) 0003h(3) User ID (2003h) 0002h(3) Sum of User IDs = (0005h and 000Fh) << 12 + (0007h and 000Fh) << 8 + (0003h and 000Fh) << 4 + (0002h and 000Fh) = 5000h + 0700h + 0030h + 0002h = 5732h(4) Checksum = (3F7Fh and 3F39h) + Sum of User IDs = 3F39h + 5732h = 966Bh(5) Note 1: This value is obtained by making all bits of the Configuration Word a ‘1’ but the code-protect bit is ‘0’ (thus, enabled), then converting it to hex, thus having a value of 3F7Fh. 2: This value is obtained by making all used bits of the Configuration Word a ‘1’, but the code-protect bit is ‘0’ (thus, enabled), then converting it to hex, thus having a value of 3F39h. 3: These values are picked at random for this example, they could be any 16-bit value. 4: In order to calculate the sum of user IDs, take the 16-bit value of the first user ID location (0005h), AND it to the Least Significant nibble of the first user ID value (000Fh). This gives you the value 0005h, then shift left 12 bits giving you 5000h. Do the same procedure for 16-bit value of the second user ID location (0007h), except shift left 8 bits. Also, do the same for the third user ID location (0003h), except shift left 4 bits. For the fourth user ID location do not shift left at all. Finally, add up all four user ID values to get the final sum of user IDs of 5732h. 5: This value is obtained by ANDing the Configuration Word value with the Configuration Word mask value and adding it to the sum of user IDs (3F7Fh AND 3F39h) + 5732h = 966Bh. DS41561C-page 18 Advance Information 2011-2012 Microchip Technology Inc. PIC12F752/HV752 7.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 7-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C AC/DC CHARACTERISTICS Sym. Characteristics Min. Typ. Max. Units Conditions/Comments 2.0 — 5.5 V PIC12F752 2.0 — 4.7(1) V PIC12HV752 General VDD VDD level for read/write operations, program and data memory VDD level for Bulk Erase operations, program and data memory 2.0 — 5.25(2) V PIC12HV752 4.5 — 5.5 V PIC12F752 4.5 — 4.7(1) V PIC12HV752 4.5 — 5.25(2) V PIC12HV752 VIHH High voltage on MCLR for Program/Verify mode entry 10 — 13 V IIHH MCLR current during programming — 300 1000 A TVHHR MCLR rise time (VSS to VHH) for Program/Verify mode entry — — 1.0 s TPPDP Hold time after VPPchanges 5 — — s VIH1 (ICSPCLK, ICSPDAT) input high level 0.8 VDD — — V VIL1 (ICSPCLK, ICSPDAT) input low level 0.2 VDD — — V TSET0 ICSPCLK, ICSPDAT setup time before MCLR (Program/Verify mode selection pattern setup time) 100 — — ns THLD0 Hold time after VDD changes 5 — — s ns Serial Program/Verify TSET1 Data in setup time before clock 100 — — THLD1 Data in hold time after clock 100 — — ns TDLY1 Data input not driven to next clock input (delay required between command/data or command/ command) 1.0 — — s TDLY2 Delay between clockto clockof next command or data 1.0 — — s TDLY3 Clock to data out valid (during a Read Data command) — — 80 ns TERA Erase cycle time — 5 6 ms TPROG Programming cycle time 3 — — ms TDIS Time delay from program to compare (HV discharge time) 100 — — s Note 1: 2: 10°C TA +40°C Maximum VDD voltage when programming the device without a current limiting series resistor. Voltages above this level will cause the shunt regulator to draw excessive current and damage the device. Limiting the current through the shunt regulator to within max shunt current (device electrical characteristic SR02) with either a series resistor or with a current limited supply. 2011-2012 Microchip Technology Inc. Advance Information DS41561C-page 19 PIC12F752/HV752 APPENDIX A: REVISION HISTORY Revision A (01/2011) Original release of this document. Revision B (04/2011) Revised Figure 2-1 and Register 5-1; Other minor corrections. Revision C (01/2012) Updated Table 5-1; Updated Examples 6-1, 6-2 and 6-3. DS41561C-page 20 Advance Information 2011-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-961-8 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2011-2012 Microchip Technology Inc. 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