PHN210T Dual N-channel TrenchMOS intermediate level FET Rev. 02 — 15 December 2010 Product data sheet 1. Product profile 1.1 General description Dual intermediate level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Suitable for high frequency applications due to fast switching characteristics Suitable for logic level gate drive sources Suitable for low gate drive sources 1.3 Applications DC-to-DC converters Motor and relay drivers Logic level translators 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C; Repetitive peak drain-source voltage - - 30 V ID drain current Tsp = 25 °C; Single device [1] - - 3.4 A Ptot total power dissipation Tsp = 25 °C [2] - - 2 W VGS = 4.5 V; ID = 1 A; Tj = 25 °C - 120 200 mΩ VGS = 10 V; ID = 2.2 A; Tj = 25 °C - 80 100 mΩ gate-drain charge VGS = 10 V; ID = 2.3 A; VDS = 15 V; Tj = 25 °C - 0.7 - nC Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD [1] Surface mounted on FR4 board, t ≤ 10 sec. [2] Surface mounted on FR4, t ≤ 10 sec. PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D drain2 6 D drain2 7 D drain1 8 D drain1 Simplified outline Graphic symbol 8 5 1 4 SOT96-1 (SO8) D2 D2 D1 D1 S1 G1 S2 G2 mbk725 3. Ordering information Table 3. Ordering information Type number PHN210T PHN210T Product data sheet Package Name Description Version SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 2 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Continuous - 30 V Tj ≥ 25 °C; Tj ≤ 150 °C; Repetitive peak drain-source voltage - 30 V RGS = 20 kΩ - 30 V VDGR drain-gate voltage VGS gate-source voltage drain current ID peak drain current IDM -20 20 V Tsp = 70 °C; Dual device [1] - 1.9 A Tsp = 70 °C; Single device [1] - 2.8 A Tsp = 25 °C; Dual device [1] - 2.4 A Tsp = 25 °C; Single device [1] - 3.4 A - 14 A Tsp = 25 °C; pulsed Tsp = 25 °C [2] Ptot total power dissipation - 2 W Tstg storage temperature -65 150 °C Tj junction temperature -65 150 °C Source-drain diode IS source current Tsp = 25 °C - 2.2 A ISM peak source current Tsp = 25 °C; pulsed - 14 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 3.4 A; VDD ≤ 15 V; unclamped; RGS = 50 Ω; tp = 0.2 ms - 13 mJ IAS non-repetitive avalanche current Vsup ≤ 15 V; VGS = 10 V; Tj(init) = 25 °C; RGS = 50 Ω; unclamped - 3.4 A [1] Surface mounted on FR4 board, t ≤ 10 sec. [2] Surface mounted on FR4, t ≤ 10 sec. PHN210T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 3 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 003aaf065 120 Pder (%) lD (%) 80 80 40 40 0 0 0 Fig 1. 003aaf066 120 40 80 120 160 Tamb (°C) Normalized total power dissipation as a function of ambient temperature 102 IDM (A) 0 Fig 2. 003aaf067 RDS(on) = VDS / ID tp = 10 μs 10 100 μs 80 120 160 Tamb (°C) Normalized continuous drain current as a function of ambient temperature 003aaf080 10 25 °C IAS (A) Tj prior to avalanche = 125 °C 1 ms 1 40 1 10 ms VDS 100 ms 10−1 tp 10 s ID 10−2 10−1 1 102 10 10−1 10−6 10−5 10−4 Ta = 25 °C; IDM is single pulse Fig 3. Product data sheet 10−2 unclamped inductive load Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHN210T 10−3 tp (s) VDS (V) Fig 4. Single-shot avalanche rating; avalanche current as a function of avalanche period All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 4 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Rth(j-a) thermal resistance from junction to ambient Conditions Min Typ Max Unit Surface mounted; FR4 board - 150 - K/W Surface mounted; FR4 board; t ≤ 10 sec - - 62.5 K/W 003aaf068 102 Zth(j-a) (K/W) 10 δ = 0.5 0.2 0.1 0.05 1 10−1 0.02 δ= P single pulse t tp 10−2 10−6 Fig 5. tp T T 10−5 10−4 10−3 10−2 10−1 1 10 tp (s) Transient thermal impedance from junction to ambient as a function of pulse duration PHN210T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 5 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit 30 - - V Static characteristics V(BR)DSS drain-source breakdown voltage ID = 10 µA; VGS = 0 V; Tj = 25 °C ID = 10 µA; VGS = 0 V; Tj = -55 °C 27 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = -55 °C - - 3.2 V ID = 1 mA; VDS = VGS; Tj = 150 °C 0.4 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C 1 2 2.8 V VDS = 24 V; VGS = 0 V; Tj = 25 °C - 10 100 nA VDS = 24 V; VGS = 0 V; Tj = 150 °C - 0.6 10 µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA IDSS IGSS RDSon IDSon drain leakage current gate leakage current drain-source on-state resistance on-state drain current VGS = 4.5 V; ID = 1 A; Tj = 25 °C - 120 200 mΩ VGS = 10 V; ID = 2.2 A; Tj = 150 °C - - 170 mΩ VGS = 10 V; ID = 2.2 A; Tj = 25 °C - 80 100 mΩ VDS = 1 V; VGS = 10 V 3.5 - - A VDS = 5 V; VGS = 4.5 V 2 - - A ID = 2.3 A; VDS = 15 V; VGS = 10 V; Tj = 25 °C - 6 - nC - 0.7 - nC - 0.7 - nC VDS = 20 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C - 250 - pF - 88 - pF - 54 - pF - 6 - ns - 8 - ns - 21 - ns Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time tf fall time - 15 - ns gfs transfer conductance VDS = 20 V; ID = 2.2 A; Tj = 25 °C 2 4.5 - S LD internal drain inductance measured from drain lead to centre of die; Tj = 25 °C - 2.5 - nH LS internal source inductance measured from source lead to source bond pad; Tj = 25 °C - 5 - nH 0.82 1.2 V VDS = 20 V; RL = 18 Ω; VGS = 10 V; RG(ext) = 6 Ω; Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 1.25 A; VGS = 0 V; Tj = 25 °C - trr reverse recovery time 69 - ns recovered charge IS = 1.25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 25 V; Tj = 25 °C - Qr - 55 - nC PHN210T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 6 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 003aaf069 10 lD (A) 8 VGS (V) = 20 10 5 6 003aaf070 0.5 RDS(on) 3.2 3.4 3.6 3.8 (Ω) 0.4 4 4.2 0.3 4.2 4 4 0.2 VGS (V) = 5 3.8 3.6 3.4 3.2 2 20 0 0 0 0.4 0.8 1.2 1.6 2 VDS (V) 0 2 4 6 8 10 ID (A) Tj = 25 °C Fig 6. 10 0.1 Tj = 25 °C Output characteristics: drain current as a function of drain-source voltage; typical values Fig 7. 003aaf071 10 ID (A) 8 003aaf073 6 gfs (S) Tj = 25 °C Tj = 25 °C 4 Tj = 150 °C 6 Drain-source on-state resistance as a function of drain current; typical values Tj = 150 °C 4 2 2 0 0 0 2 4 0 6 2 4 6 8 VDS > ID x RDSon Fig 8. 10 lD (A) VGS (V) VDS > ID x RDSon Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aaf074 2 a Fig 9. Forward transconductance as a function of drain current; typical values 003aaf075 4 VGS(th) (V) 1.5 3 1 2 typical 0.5 1 minimum 0 −50 0 50 100 150 Tj (°C) maximum 0 −70 10 90 170 Tj (°C) ID = 1 mA; VDS = VGS Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature PHN210T Product data sheet Fig 11. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 7 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 003aaf076 1 ID (A) 10−2 003aaf077 103 C (pF) minimum 10−3 typical Ciss maximum 102 Coss 10−4 Crss 10−5 10−6 0 1 2 3 5 10 10−1 1 102 10 VDS (V) VGS (V) Tj = 25 °C; VDS = VGS VGS = 0 V; f = 1 MHz Fig 12. Sub-threshold drain current as a function of gate-source voltage 003aaf078 16 VGS (V) 12 Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aaf079 10 lF (A) 8 6 Tj = 150 °C 8 Tj = 25 °C 4 4 2 0 0 0 2 4 6 8 10 QG (nC) ID = 2.3 A; Tj = 25 °C; VDD = 15 V Product data sheet 0.4 0.8 1.2 1.6 VSDS (V) VGS = 0 V Fig 14. Gate-source voltage as a function of gate charge; typical values PHN210T 0 Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 8 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 7. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 16. Package outline SOT96-1 (SO8) PHN210T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 9 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHN210T v.2 20101215 Product data sheet - PHN210T v.1 Modifications: PHN210T v.1 PHN210T Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 19990301 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 - © NXP B.V. 2010. All rights reserved. 10 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective PHN210T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 11 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PHN210T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 15 December 2010 © NXP B.V. 2010. All rights reserved. 12 of 13 PHN210T NXP Semiconductors Dual N-channel TrenchMOS intermediate level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 December 2010 Document identifier: PHN210T