CSD87381P www.ti.com SLPS405B – MARCH 2013 – REVISED MAY 2013 Synchronous Buck NexFET™ Power Block II FEATURES DESCRIPTION • • • • • • • • • • • • The CSD87381P NexFET™ power block II is a highly optimized design for synchronous buck applications offering high current and high efficiency capability in a small 3-mm × 2.5-mm outline. Optimized for 5V gate drive applications, this product offers an efficient and flexible solution capable of providing a high density power supply when paired with any 5V gate driver from an external controller/driver. 1 2 Half-Bridge Power Block 90% system Efficiency at 10A Up To 15A Operation High Density – 3.0 x 2.5mm LGA Footprint Double Side Cooling Capability Ultra Low Profile – 0.48-mm MAX Optimized for 5V Gate Drive Low Switching Losses Low Inductance Package RoHS Compliant Halogen Free Pb-Free Terminal Plating TEXT ADDED FOR SPACING ORDERING INFORMATION Device CSD87381P Package Media 3.0 x 2.5 LGA 13-Inch Reel Qty Ship 2500 Tape and Reel TEXT ADDED FOR SPACING APPLICATIONS 1 • • • Synchronous Buck Converters – High Current, Low Duty Cycle Applications Multiphase Synchronous Buck Converters POL DC-DC Converters VIN TG PGND BG VSW TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TYPICAL POWER BLOCK EFFICIENCY and POWER LOSS TYPICAL CIRCUIT VIN VDD VDD 100 7 90 6 BOOT VIN DRVH VSW ENABLE PWM ENABLE PWM VOUT LL BG DRVL PGND Driver IC VGS = 5V VIN = 12V VOUT = 1.3V LOUT = 0.95µH fSW = 500kHz TA = 25ºC 80 Efficiency (%) GND 70 60 5 4 3 50 2 40 1 Power Loss (W) TG CSD87381P 30 0 3 6 9 Output Current (A) 12 15 0 G001 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated CSD87381P SLPS405B – MARCH 2013 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS TA = 25°C (unless otherwise noted) (1) Parameter Conditions VALUE VIN to PGND UNIT MIN MAX -0.8 30 VSW to PGND Voltage range 30 VSW to PGND (10 ns) 32 TG to VSW -8 10 BG to PGND -8 10 Pulsed Current Rating, IDM (2) 40 A 4 W Power Dissipation, PD (3) Avalanche Energy EAS Sync FET, ID = 27, L = 0.1mH 36 Control FET, ID = 20, L = 0.1mH 20 Operating Junction and Storage Temperature Range, TJ, TSTG (1) (2) (3) -55 V mJ 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. Pulse Duration ≤50 µS. Duty cycle ≤0.01. Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu. RECOMMENDED OPERATING CONDITIONS TA = 25° (unless otherwise noted) Parameter Conditions Gate Drive Voltage, VGS MIN MAX 4.5 8 V 24 V Input Supply Voltage, VIN 200 1500 UNIT Switching Frequency, fSW CBST = 0.1μF (min) Operating Current No Airflow 15 A With Airflow (200 LFM) 20 A With Airflow + Heat Sink 25 A 125 °C MAX UNIT Operating Temperature, TJ kHz POWER BLOCK PERFORMANCE TA = 25° (unless otherwise noted) Parameter Power Loss, PLOSS (1) VIN Quiescent Current, IQVIN (1) 2 Conditions MIN TYP VIN = 12V, VGS = 5V, VOUT = 1.3V, IOUT = 8A, fSW = 500kHz, LOUT = 0.3µH, TJ = 25ºC 1.0 W TG to TGR = 0V BG to PGND = 0V 10 µA Measurement made with six 10µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5V driver IC. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated CSD87381P www.ti.com SLPS405B – MARCH 2013 – REVISED MAY 2013 THERMAL INFORMATION TA = 25°C (unless otherwise stated) THERMAL METRIC RθJA RθJC (1) (2) Junction to ambient thermal resistance (Min Cu) Junction to ambient thermal resistance (Max Cu) (1) TYP MAX UNIT 184 (2) (1) Junction to case thermal resistance (Top of package) Junction to case thermal resistance (PGND Pin) MIN (1) 84 (1) 4.9 °C/W 1.65 RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 CSD87381P SLPS405B – MARCH 2013 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS Q1 Control FET MIN TYP Q2 Sync FET MAX MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, IDS = 250μA IDSS Drain to Source Leakage Current 30 30 VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = 10 VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250μA RDS(on) Drain to Source On Resistance VGS = 4.5V, IDS = 8A 15.7 18.9 7.0 8.4 VGS = 8V, IDS = 8A 13.6 16.3 6.3 7.6 gfs Transconductance VDS = 10V, IDS = 8A 1.1 V 1 1 μA 100 100 nA 1.7 V 1.9 40 1.0 89 mΩ S Dynamic Characteristics CISS Input Capacitance (1) (1) COSS Output Capacitance CRSS Reverse Transfer Capacitance (1) RG Series Gate Resistance VGS = 0V, VDS = 15V, f = 1MHz (1) Gate Charge Total (4.5V) Qg (1) Qgd Gate Charge - Gate to Drain Qgs Gate Charge - Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VDS = 15V, IDS = 8A VDD = 12V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 8A, RG = 2Ω 434 564 1020 1320 pF 225 293 308 400 pF 9.1 11.8 40 52 pF 5.0 6.4 1.25 2.5 Ω 3.9 5.0 8.9 11.5 nC 0.9 2.5 nC 1.2 2.0 nC 0.7 1.3 nC 4.9 8.5 nC 6.7 7.9 ns 19.3 16.3 ns 10.6 16.8 ns 3.0 2.9 ns Diode Characteristics VSD Diode Forward Voltage IDS = 8A, VGS = 0V 0.85 0.79 V Qrr Reverse Recovery Charge 16.0 nC Reverse Recovery Time Vdd = 15V, IF = 8A, di/dt = 300A/μs 8.0 trr 13 17 ns (1) Specified by design Max RθJA = 84°C/W when mounted on 1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick) Cu. 4 Submit Documentation Feedback Max RθJA = 184°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. Copyright © 2013, Texas Instruments Incorporated CSD87381P www.ti.com SLPS405B – MARCH 2013 – REVISED MAY 2013 TYPICAL POWER BLOCK DEVICE CHARACTERISTICS TJ = 125°C, unless stated otherwise. 1.1 5 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.95µH Power Loss (W) 4 3.5 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.95µH 1 Power Loss, Normalized 4.5 3 2.5 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0 1 2 3 4 5 0.5 −50 6 7 8 9 10 11 12 13 14 15 Output Current (A) G001 20 20 15 15 10 400LFM 200LFM 100LFM Nat Conv 5 0 0 10 20 80 0 90 0 20 150 G001 120 140 G001 Figure 4. Typical Safe Operating Area(1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0” (W) × 3.5” (L) x 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section for detailed explanation. 4.5 1.3 3.3 1.2 2.2 1.1 1.1 1 VIN = 12V VGS = 5V VOUT = 1.3V LOUT = 0.95µH IOUT = 15A 0.9 0.8 0 200 400 600 800 1000 1200 Switching Frequency (kHz) 1400 0.0 −1.1 −2.2 −3.3 1600 2.3 1.15 1.7 1.1 1.1 1.05 0.6 G001 VGS = 5V VOUT = 1.3V LOUT = 0.95µH fSW = 500kHz IOUT = 15A 1 0.95 0.9 Figure 5. Normalized Power Loss vs Switching Frequency Copyright © 2013, Texas Instruments Incorporated 1.2 0 2 4 6 8 10 12 14 16 Input Voltage (V) 18 20 22 24 0.0 −0.6 SOA Temperature Adj (ºC) 1.4 Power Loss, Normalized TEXT ADDED FOR SPACING 5.6 SOA Temperature Adj (ºC) TEXT ADDED FOR SPACING Power Loss, Normalized 40 60 80 100 Board Temperature (ºC) G001 1.5 0.7 125 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.95µH Figure 3. Safe Operating Area – PCB Horizontal Mount (1) (1) 25 50 75 100 Junction Temperature (ºC) 10 5 30 40 50 60 70 Ambient Temperature (ºC) 0 Figure 2. Normalized Power Loss vs Temperature Output Current (A) Output Current (A) Figure 1. Power Loss vs Output Current −25 −1.1 G001 Figure 6. Normalized Power Loss vs Input Voltage Submit Documentation Feedback 5 CSD87381P SLPS405B – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued) TJ = 125°C, unless stated otherwise. TEXT ADDED FOR SPACING 4.5 4 1.35 1.3 3.4 1.25 2.8 1.2 2.3 1.15 1.7 1.1 VIN = 12V VGS = 5V fSW = 500kHz LOUT = 0.95µH IOUT = 15A 1.05 1 0.95 0.9 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 Output Voltage (V) 4.3 4.8 1.1 0.6 0 Submit Documentation Feedback 1.25 1.2 2.81 2.25 1.15 1.68 1.1 1.12 1.05 0.56 0 1 −0.6 −1.1 5.3 Figure 7. Normalized Power Loss vs. Output Voltage 6 3.37 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz IOUT = 15A SOA Temperature Adj (ºC) 1.4 1.3 Power Loss, Normalized 5.1 SOA Temperature Adj (ºC) Power Loss, Normalized TEXT ADDED FOR SPACING 1.45 0.95 G001 0 −0.56 100 200 300 400 500 600 700 800 900 1000 1100 Output Inductance (nH) G001 Figure 8. Normalized Power Loss vs. Output Inductance Copyright © 2013, Texas Instruments Incorporated CSD87381P www.ti.com SLPS405B – MARCH 2013 – REVISED MAY 2013 TYPICAL POWER BLOCK MOSFET CHARACTERISTICS TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING 100 18 90 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) TEXT ADDED FOR SPACING 20 16 14 12 10 8 6 VGS = 8.0V VGS = 4.5V VGS = 4.0V 4 2 0 0 0.2 0.4 0.6 0.8 VDS - Drain-to-Source Voltage (V) 80 70 60 50 40 30 10 0 1 VGS = 8.0V VGS = 4.5V VGS = 4.0V 20 0 0.2 G001 Figure 9. Control MOSFET Saturation TEXT ADDED FOR SPACING IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) G001 TEXT ADDED FOR SPACING VDS = 5V 0.1 0.01 0.001 TC = 125°C TC = 25°C TC = −55°C 0.0001 0 0.5 1 1.5 2 2.5 VGS - Gate-to-Source Voltage (V) 3 VDS = 5V 10 1 0.1 0.01 0.001 TC = 125°C TC = 25°C TC = −55°C 0.0001 0.00001 0 0.5 G001 Figure 11. Control MOSFET Transfer 1 1.5 2 2.5 VGS - Gate-to-Source Voltage (V) 3 G001 Figure 12. Sync MOSFET Transfer TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 10 10 ID = 8A VDS =15V 9 VGS - Gate-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) 1.2 100 1 8 7 6 5 4 3 2 1 0 1 Figure 10. Sync MOSFET Saturation 10 0.00001 0.4 0.6 0.8 VDS - Drain-to-Source Voltage (V) 0 1 2 3 4 5 Qg - Gate Charge (nC) 6 7 Figure 13. Control MOSFET Gate Charge Copyright © 2013, Texas Instruments Incorporated 8 G001 ID = 8A VDS = 15V 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 Qg - Gate Charge - nC (nC) 16 18 20 G001 Figure 14. Sync MOSFET Gate Charge Submit Documentation Feedback 7 CSD87381P SLPS405B – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued) TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 10000 10000 1000 C − Capacitance (nF) C − Capacitance (nF) Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 100 10 1 0 5 10 15 20 25 VDS - Drain-to-Source Voltage (V) 1000 100 10 1 30 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 0 5 Figure 15. Control MOSFET Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING VGS(th) - Threshold Voltage (V) VGS(th) - Threshold Voltage (V) ID = 250µA 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 ID = 250µA 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.9 −75 −25 25 75 125 TC - Case Temperature (ºC) 0.6 −75 175 −25 G001 Figure 17. Control MOSFET VGS(th) 25 75 125 TC - Case Temperature (ºC) 175 G001 Figure 18. Sync MOSFET VGS(th) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 40 20 ID = 8A 36 RDS(on) - On-State Resistance (mΩ) RDS(on) - On-State Resistance (mΩ) G001 1.6 1 32 28 24 20 16 12 8 TC = 25°C TC = 125ºC 4 0 1 2 3 4 5 6 7 8 VGS - Gate-to- Source Voltage (V) 9 Figure 19. Control MOSFET RDS(on) vs VGS 8 30 Figure 16. Sync MOSFET Capacitance 1.9 0 10 15 20 25 VDS - Drain-to-Source Voltage (V) G001 Submit Documentation Feedback 10 G001 ID = 8A 18 16 14 12 10 8 6 4 TC = 25°C TC = 125ºC 2 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to- Source Voltage (V) 9 10 G001 Figure 20. Sync MOSFET RDS(on) vs VGS Copyright © 2013, Texas Instruments Incorporated CSD87381P www.ti.com SLPS405B – MARCH 2013 – REVISED MAY 2013 TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued) TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.6 Normalized On-State Resistance Normalized On-State Resistance ID = 8A VGS = 8V 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 −75 1.8 ID = 8A 1.7 VGS = 8V 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 −75 −25 −25 25 75 125 TC - Case Temperature (ºC) 175 G001 Figure 21. Control MOSFET Normalized RDS(on) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING ISD − Source-to-Drain Current (A) ISD − Source-to-Drain Current (A) G001 100 10 1 0.1 0.01 0.001 TC = 25°C TC = 125°C 0 0.2 0.4 0.6 0.8 1 VSD − Source-to-Drain Voltage (V) 1.2 10 1 0.1 0.01 0.001 0.0001 TC = 25°C TC = 125°C 0 G001 Figure 23. Control MOSFET Body Diode TEXT ADDED FOR SPACING 1 G001 TEXT ADDED FOR SPACING I(AV) - Peak Avalanche Current (A) 100 10 TC = 25°C TC = 125°C 1 0.01 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) Figure 24. Sync MOSFET Body Diode 100 I(AV) - Peak Avalanche Current (A) 175 Figure 22. Sync MOSFET Normalized RDS(on) 100 0.0001 25 75 125 TC - Case Temperature (ºC) 0.1 t(AV) - Time in Avalanche (ms) 1 G001 Figure 25. Control MOSFET Unclamped Inductive Switching Copyright © 2013, Texas Instruments Incorporated 10 TC = 25°C TC = 125°C 1 0.01 0.1 t(AV) - Time in Avalanche (ms) 1 G001 Figure 26. Sync MOSFET Unclamped Inductive Switching Submit Documentation Feedback 9 CSD87381P SLPS405B – MARCH 2013 – REVISED MAY 2013 www.ti.com The CSD87381P NexFET™ power block is an optimized design for synchronous buck applications using 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems centric environment. System level performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application. Power Loss Curves MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87381P as a function of load current. This curve is measured by configuring and running the CSD87381P as it would be in the final application (see Figure 27).The measured power loss is the CSD87381P loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve. (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT) = Power Loss (1) The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions. Safe Operating Curves (SOA) The SOA curves in the CSD87381P data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) x 3.5” (L) x 0.062” (T) and 6 copper layers of 1 oz. copper thickness. Normalized Curves The normalized curves in the CSD87381P data sheet provides guidance on the Power Loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve. Input Current (IIN) A VDD A VDD V VIN Gate Drive V Voltage (VDD) VIN BOOT DRVH ENABLE Input Voltage (VIN) TG Output Current (IOUT) VSW LL PWM PWM DRVL GND Driver IC A VOUT BG PGND CSD87381P Averaging Circuit Averaged Switch V Node Voltage (VSW_AVG) Figure 27. Typical Application 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated CSD87381P www.ti.com SLPS405B – MARCH 2013 – REVISED MAY 2013 Calculating Power Loss and SOA The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure will outline the steps the user should take to predict product performance for any set of system conditions. Design Example Operating Conditions: • Output Current = 8A • Input Voltage = 4V • Output Voltage = 1V • Switching Frequency = 800kHz • Inductor = 0.2µH Calculating Power Loss • • • • • • Power Loss at 8A = 1.44W (Figure 1) Normalized Power Loss for input voltage ≈ 1.06 (Figure 6) Normalized Power Loss for output voltage ≈ 0.97 (Figure 7) Normalized Power Loss for switching frequency ≈ 1.11(Figure 5) Normalized Power Loss for output inductor ≈ 1.13 (Figure 8) Final calculated Power Loss = 1.44W x 1.06 x 0.97 x 1.11 x 1.13 ≈ 1.86W Calculating SOA Adjustments • • • • • SOA adjustment for input voltage ≈ 0.7ºC (Figure 6) SOA adjustment for output voltage ≈ -0.3ºC (Figure 7) SOA adjustment for switching frequency ≈ 1.03ºC (Figure 5) SOA adjustment for output inductor ≈ 1.5ºC (Figure 8) Final calculated SOA adjustment = 0.7 + (-0.3) + 1.3 + 1.5 ≈ 2.2ºC In the design example above, the estimated power loss of the CSD87381P would increase to 1.86W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 2.2ºC. Figure 28 graphically shows how the SOA curve would be adjusted accordingly. 1. Start by drawing a horizontal line from the application current to the SOA curve. 2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature. 3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value. In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 2.2ºC. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature. Figure 28. Power Block SOA Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11 CSD87381P SLPS405B – MARCH 2013 – REVISED MAY 2013 www.ti.com RECOMMENDED PCB DESIGN OVERVIEW There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief description on how to address each parameter is provided. Electrical Performance The CSD87381P has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, inductor, and output capacitors. • The placement of the input capacitors relative to VIN and PGND pins of CSD87381P device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 5). The example in Figure 5 uses 1x10nF 0402 25V and 4 x 10μF 1206 25V ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Stage C21, C5, C8, C19, and C18 should follow in order. • The switching node of the output inductor should be placed relatively close to the Power Block II CSD87381P VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level.see Figure 29 (1) (1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla Thermal Performance The CSD87381P has the ability to utilize the PGND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel: • Intentionally space out the vias from each other to avoid a cluster of holes in a given area. • Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole and a 16 mil capture pad. • Tent the opposite side of the via with solder-mask. In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities. Figure 29. Recommended PCB Layout (Top Down View) 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated CSD87381P www.ti.com SLPS405B – MARCH 2013 – REVISED MAY 2013 MECHANICAL DATA CSD87381P Package Dimensions Table 1. Pin Configuration Position Copyright © 2013, Texas Instruments Incorporated Designation Pin 1 TG Pin 2 VIN Pin 3 PGND Pin 4 BG Pin 5 VSW Submit Documentation Feedback 13 CSD87381P SLPS405B – MARCH 2013 – REVISED MAY 2013 www.ti.com 1.500 PKG REF 0.717 1.118 1.500 PKG REF Land Pattern Recommendation 1.250 PKG REF 1.250 0.663 2 0.000 0.043 0.343 0.663 5 3 1 4 Text For Spacing Stencil Recommendation (100 µm) 1.250 1.500 0.879 0.559 0.033 0.000 0.259 0.758 PACKAGE OUTLINE 1.250 1.078 1.250 PKG REF PICO (MPC) SMD PCB Text For Spacing . Text For Spacing 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated CSD87381P www.ti.com SLPS405B – MARCH 2013 – REVISED MAY 2013 Stencil Recommendation (125 µm) Text For Spacing For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Text For Spacing Pin Drawing 87381P TI YMS LLLL Text For Spacing Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 15 CSD87381P SLPS405B – MARCH 2013 – REVISED MAY 2013 www.ti.com CSD87381P Embossed Carrier Tape Dimensions (1) Pin 1 will be oriented in the top left quadrant of the tape enclosure (closest to the carrier tape sprocket holes). spacer REVISION HISTORY Changes from Original (March 2013) to Revision A • Page Changes to a Product Preview device .................................................................................................................................. 1 Changes from Revision A (March 2013) to Revision B Page • Changed RθJC-PCB To: RθJC in the THERMAL INFORMATION table ..................................................................................... 3 • Changed Figure 16 ............................................................................................................................................................... 7 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 16-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) CSD87381P ACTIVE Package Type Package Pins Package Drawing Qty PTAB MPC 5 2500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-1-260C-UNLIM (4/5) -55 to 150 87381P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD87381P Package Package Pins Type Drawing PTAB MPC 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 2.7 B0 (mm) K0 (mm) P1 (mm) 3.2 0.55 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD87381P PTAB MPC 5 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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