CSD86350Q5D www.ti.com SLPS223A – MAY 2010 – REVISED MAY 2010 Synchronous Buck NexFET™ Power Block FEATURES DESCRIPTION • • • • • • • • • • • The CSD86350Q5D NexFET™ power block is an optimized design for synchronous buck applications offering high current, high efficiency, and high frequency capability in a small 5-mm × 6-mm outline. Optimized for 5V gate drive applications, this product offers a flexible solution capable of offering a high density power supply when paired with any 5V gate drive from an external controller/driver. 1 2 Half-Bridge Power Block 90% system Efficiency at 25A Up To 40A Operation High Frequency Operation (Up To 1.5MHz) High Density – SON 5-mm × 6-mm Footprint Optimized for 5V Gate Drive Low Switching Losses Ultra Low Inductance Package RoHS Compliant Halogen Free Pb-Free Terminal Plating TEXT ADDED FOR SPACING Top View APPLICATIONS • • • • Synchronous Buck Converters – High Frequency Applications – High Current, Low Duty Cycle Applications Multiphase Synchronous Buck Converters POL DC-DC Converters IMVP, VRM, and VRD Applications 8 VSW 7 VSW 3 6 VSW 4 5 VIN 1 VIN 2 TG TGR PGND (Pin 9) BG P0116-01 TEXT ADDED FOR SPACING ORDERING INFORMATION Device Package Media CSD86350Q5D SON 5-mm × 6-mm Plastic Package 13-Inch Reel Qty Ship 2500 Tape and Reel TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING CSD86350Q5D VDD ENABLE ENABLE VIN BST DRVH PWM LL GND DRVL TG Control FET TGR VSW PWM BG VI VO Sync FET PGND Efficiency (%) Driver IC VDD 100 6 90 5 VGS = 5V VIN = 12V VOUT = 1.3V LOUT = 0.3µH fSW = 500kHz T A = 25°C 80 70 4 3 60 2 50 1 Power Loss (W) TYPICAL POWER BLOCK EFFICIENCY and POWER LOSS TYPICAL CIRCUIT S0474-01 40 0 5 10 15 Output Current (A) 20 0 25 G029 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CSD86350Q5D SLPS223A – MAY 2010 – REVISED MAY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS TA = 25°C (unless otherwise noted) (1) Parameter Conditions VALUE UNIT -0.8 to 25 V TG to TGR -8 to 10 V BG to PGND -8 to 10 V VIN to PGND Voltage range Pulsed Current Rating, IDM 120 A Power Dissipation, PD 13 W Avalanche Energy EAS Sync FET, ID = 100A, L = 0.1mH 500 Control FET, ID = 58A, L = 0.1mH 168 Operating Junction and Storage Temperature Range, TJ, TSTG (1) mJ -55 to 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS TA = 25° (unless otherwise noted) Parameter Conditions Gate Drive Voltage, VGS MIN MAX 4.5 8 Input Supply Voltage, VIN Switching Frequency, fSW UNIT V 22 CBST = 0.1mF (min) 200 V 1500 Operating Current Operating Temperature, TJ kHz 40 A 125 °C MAX UNIT POWER BLOCK PERFORMANCE TA = 25° (unless otherwise noted) Parameter Power Loss, PLOSS (1) VIN Quiescent Current, IQVIN (1) Conditions MIN TYP VIN = 12V, VGS = 5V, VOUT = 1.3V, IOUT = 25A, fSW = 500kHz, LOUT = 0.3µH, TJ = 25ºC 2.8 W TG to TGR = 0V BG to PGND = 0V 10 µA Measurement made with six 10µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5V driver IC. THERMAL INFORMATION TA = 25°C (unless otherwise stated) THERMAL METRIC RqJA RqJC (1) (2) 2 Junction to ambient thermal resistance (Min Cu) Junction to ambient thermal resistance (Max Cu) 2 (2) TYP MAX UNIT 102 (1) (2) Junction to case thermal resistance (Top of package) Junction to case thermal resistance (PGND Pin) MIN (1) (2) 50 (2) 20 °C/W 2 (6.45-cm2) 2 Device mounted on FR4 material with 1-inch Cu. RqJC is determined with the device mounted on a 1-inch (6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RqJC is specified by design while RqJA is determined by the user’s board design. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated CSD86350Q5D www.ti.com SLPS223A – MAY 2010 – REVISED MAY 2010 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise stated) PARAMETER Q1 Control FET TEST CONDITIONS MIN TYP Q2 Sync FET MAX MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, IDS = 250mA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 20V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10 / -8 VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250mA RDS(on) Drain to Source On Resistance VGS = 4.5V, IDS = 20A gfs Transconductance 25 25 0.9 V 1 1 mA 100 100 nA 1.1 1.6 V 2 2.7 mΩ 1.8 2.5 mΩ 1.4 2.1 5 6.6 VGS = 8V, IDS = 20A 4.5 6 VDS = 10V, IDS = 20A 103 0.9 132 S Dynamic Characteristics (1) CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance (1) RG Series Gate Resistance (1) 1440 1870 3080 4000 pF 645 840 1550 2015 pF 22 29 45 59 pF 1.4 2.8 1.4 2.8 Ω 8.2 10.7 19.4 25 nC VGS = 0V, VDS = 12.5V, f = 1MHz (1) Gate Charge Total (4.5V) Qg (1) Qgd Gate Charge - Gate to Drain Qgs Gate Charge - Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VDS = 12.5V, IDS = 20A VDS = 12V, VGS = 0V VDS = 12.5V, VGS = 4.5V, IDS = 20A, RG = 2Ω 1 2.5 nC 3.2 5.1 nC 1.9 2.8 nC 9.9 28 nC 8 9 ns 21 23 ns 9 24 ns 2.3 21 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time (1) IDS = 20A, VGS = 0V 0.85 Vdd = 12V, IF = 20A, di/dt = 300A/ms 16 1 0.77 40 1 nC V 22 32 ns Specified by design HD LD HD LG HG HS LS 86350 5x6 QFN TTA MIN Rev1 86350 5x6 QFN TTA MIN Rev1 Max RqJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Max RqJA = 102°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. LG HG M0189-01 Copyright © 2010, Texas Instruments Incorporated LD HS LS M0190-01 Submit Documentation Feedback 3 CSD86350Q5D SLPS223A – MAY 2010 – REVISED MAY 2010 www.ti.com TYPICAL POWER BLOCK DEVICE CHARACTERISTICS TJ = 125°C, unless stated otherwise. 1.2 10 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH Power Loss (W) 8 7 1.1 Power Loss, Normalized 9 6 5 4 3 1 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 0.9 0.8 0.7 2 0.6 1 0 0 5 10 15 20 25 Output Current (A) 30 35 0.5 -50 40 -25 50 50 45 45 40 40 35 35 30 25 20 400LFM 200LFM 100LFM Nat Conv VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 10 5 25 50 75 100 Junction Temperature ( °C) 125 150 G002 Figure 2. Power Loss vs Temperature Output Current (A) Output Current (A) Figure 1. Power Loss vs Output Current 15 0 G001 30 25 20 10 5 0 400LFM 200LFM 100LFM Nat Conv VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 15 0 0 10 20 30 40 50 60 Ambient Temperature (°C) 70 80 90 0 10 20 G003 (1) Figure 3. Safe Operating Area – PCB Vertical Mount 30 40 50 60 Ambient Temperature (°C) 70 80 90 G004 Figure 4. Safe Operating Area – PCB Horizontal Mount(1) 50 45 Output Current (A) 40 35 30 25 20 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 15 10 5 0 0 20 40 60 80 100 Board Temperature (°C) 120 140 G005 Figure 5. Typical Safe Operating Area(1) (1) 4 The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0” (W) × 3.5” (L) x 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section for detailed explanation. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated CSD86350Q5D www.ti.com SLPS223A – MAY 2010 – REVISED MAY 2010 TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued) TJ = 125°C, unless stated otherwise. TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.4 1.2 5.3 1.1 2.7 1 0.1 0.9 -2.5 0.8 -5.1 0.7 -7.7 200 400 600 800 1000 1200 Switching Frequency (kHz) 1400 -10.3 1600 15.7 VGS = 5V VOUT = 1.3V LOUT = 0.3µH fSW = 500kHz IO = 40A 1.3 13.1 10.5 7.9 1.2 5.3 1.1 2.7 1 0.1 0.9 -2.5 0.8 -5.1 0.7 -7.7 0.6 -10.3 3 5 7 9 G006 11 13 15 Input Voltage (V) 17 19 21 23 G007 Figure 6. Normalized Power Loss vs Switching Frequency Figure 7. Normalized Power Loss vs Input Voltage TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING VGS = 5V VIN = 12V LOUT = 0.3µH fSW = 500kHz IO = 40A 1.7 1.6 1.5 20.8 1.6 18.2 1.5 15.6 1.4 13 1.4 10.4 1.3 7.8 1.2 5.2 1.1 2.6 0 1 Power Loss, Normalized 1.8 2.7 1 0.1 0.9 -2.5 0.8 -5.1 -7.7 -5.2 0.6 2 2.5 3 3.5 Output Voltage (V) 4 4.5 5 5.5 Figure 8. Normalized Power Loss vs. Output Voltage Copyright © 2010, Texas Instruments Incorporated -10.3 0 G008 7.9 5.3 0.8 1.5 10.5 1.1 0.7 1 13.1 1.2 -2.6 0.5 15.7 VGS = 5V VIN = 12V VOUT = 1.3V fSW = 500kHz IO = 40A 1.3 0.9 SOA Temperature Adj (°C) 10.5 7.9 0.6 Power Loss, Normalized 1.5 SOA Temperature Adj (°C) 1.3 1.6 13.1 SOA Temperature Adj (°C) Power Loss, Normalized 1.4 15.7 Power Loss, Normalized VGS = 5V VIN = 12V VOUT = 1.3V LOUT = 0.3µH IO = 40A SOA Temperature Adj (°C) 1.6 1.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Output Inductance (µH) 0.9 1 1.1 G009 Figure 9. Normalized Power Loss vs. Output Inductance Submit Documentation Feedback 5 CSD86350Q5D SLPS223A – MAY 2010 – REVISED MAY 2010 www.ti.com TYPICAL POWER BLOCK MOSFET CHARACTERISTICS TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING 80 70 70 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A TEXT ADDED FOR SPACING 80 60 VGS = 8V 50 VGS = 4.5V 40 30 VGS = 4V 20 10 60 VGS = 8V 50 VGS = 4.5V 40 30 VGS = 4V 20 10 0 0 0 0.2 0.4 0.6 0.8 VDS - Drain-to-Source Voltage - V 1 0 0.1 G010 Figure 10. Control MOSFET Saturation TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING VDS = 5V IDS - Drain-to-Source Current - A VDS = 5V IDS - Drain-to-Source Current - A G011 100 10 1 T C = 125°C 0.1 T C = 25°C 0.01 T C = -55°C 0.001 10 T C = 125°C 1 T C = 25°C 0.1 0.01 T C = -55°C 0.001 0.0001 0.0001 0 0.5 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage - V 3.5 0 4 0.5 G012 Figure 12. Control MOSFET Transfer 1 1.5 2 VGS - Gate-to-Source Voltage - V 2.5 G013 Figure 13. Sync MOSFET Transfer TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 8 8 ID = 20A VDS = 12.5V 7 VGS - Gate-to-Source Voltage - V VGS - Gate-to-Source Voltage - V 0.5 Figure 11. Sync MOSFET Saturation 100 6 5 4 3 2 1 0 ID = 20A VDS = 12.5V 7 6 5 4 3 2 1 0 0 2 4 6 8 10 Qg - Gate Charge - nC 12 Figure 14. Control MOSFET Gate Charge 6 0.2 0.3 0.4 VDS - Drain-to-Source Voltage - V Submit Documentation Feedback 14 G014 0 5 10 15 20 Qg - Gate Charge - nC 25 30 G015 Figure 15. Sync MOSFET Gate Charge Copyright © 2010, Texas Instruments Incorporated CSD86350Q5D www.ti.com SLPS223A – MAY 2010 – REVISED MAY 2010 TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued) TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 10 10 Ciss = Cgd + Cgs C C -- Capacitance Capacitance -- nF nF C C -- Capacitance Capacitance -- nF nF f = 1MHz VGS = 0V 1 Coss = Cds + Cgd 0.1 Crss = Cgd 1 Coss = Cds + Cgd Ciss = Cgd + Cgs Crss = Cgd 0.1 f = 1MHz VGS = 0V 0.01 0.01 0 5 10 15 20 VDS - Drain-to-Source Voltage - V 25 0 5 G016 Figure 16. Control MOSFET Capacitance TEXT ADDED FOR SPACING G017 TEXT ADDED FOR SPACING 1.8 ID = 250µA ID = 250µA 1.6 VGS(th) - Threshold Voltage - V 1.6 VGS(th) - Threshold Voltage - V 25 Figure 17. Sync MOSFET Capacitance 1.8 1.4 1.2 1 0.8 0.6 0.4 0.2 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -75 -25 25 75 T C - Case Temperature - °C 125 0 -75 175 -25 G018 Figure 18. Control MOSFET VGS(th) 25 75 T C - Case Temperature - °C 125 175 G019 Figure 19. Sync MOSFET VGS(th) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 12 12 ID = 20A RDS(on) - On-State Resistance - mΩ RDS(on) - On-State Resistance - mΩ 10 15 20 VDS - Drain-to-Source Voltage - V 10 T C = 125°C 8 6 4 T C = 25°C 2 0 ID = 20A 10 8 6 T C = 125°C 4 2 T C = 25°C 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 Figure 20. Control MOSFET RDS(on) vs VGS Copyright © 2010, Texas Instruments Incorporated 10 G020 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G021 Figure 21. Sync MOSFET RDS(on) vs VGS Submit Documentation Feedback 7 CSD86350Q5D SLPS223A – MAY 2010 – REVISED MAY 2010 www.ti.com TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued) TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.6 ID = 20A VGS = 8V 1.4 Normalized On-State Resistance Normalized On-State Resistance 1.6 1.2 1 0.8 0.6 0.4 0.2 0 -75 -25 25 75 T C - Case Temperature - °C 125 ID = 20A VGS = 8V 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -75 175 -25 G022 Figure 22. Control MOSFET Normalized RDS(on) TEXT ADDED FOR SPACING G023 TEXT ADDED FOR SPACING ISD - Source-to-Drain Current - A ISD - Source-to-Drain Current - A 175 100 10 T C = 125°C 1 0.1 T C = 25°C 0.01 0.001 0.0001 10 1 T C = 125°C 0.1 T C = 25°C 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD - Source-to-Drain Voltage - V 1 1.2 0 0.2 G024 Figure 24. Control MOSFET Body Diode 0.4 0.6 0.8 VSD - Source-to-Drain Voltage - V 1 1.2 G025 Figure 25. Sync MOSFET Body Diode TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1k 1k 100 I(AV) = t(AV) ÷ (0.021 × L) I(AV) - Peak Avalanche Current - A I(AV) = t(AV) ÷ (0.021 × L) I(AV) - Peak Avalanche Current - A 125 Figure 23. Sync MOSFET Normalized RDS(on) 100 T C = 25°C 10 T C = 125°C 1 0.01 0.1 1 t(AV) - Time in Avalanche - ms 10 Figure 26. Control MOSFET Unclamped Inductive Switching 8 25 75 T C - Case Temperature - °C Submit Documentation Feedback G026 T C = 25°C 100 T C = 125°C 10 1 0.01 0.1 1 t(AV) - Time in Avalanche - ms 10 G027 Figure 27. Sync MOSFET Unclamped Inductive Switching Copyright © 2010, Texas Instruments Incorporated CSD86350Q5D www.ti.com SLPS223A – MAY 2010 – REVISED MAY 2010 APPLICATION INFORMATION The CSD86350Q5D NexFET™ power block is an optimized design for synchronous buck applications using 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems centric environment. System level performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application. Power Loss Curves MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD86350Q5D as a function of load current. This curve is measured by configuring and running the CSD86350Q5D as it would be in the final application (see Figure 28).The measured power loss is the CSD86350Q5D loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve. (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT) = Power Loss (1) The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions. Safe Operating Curves (SOA) The SOA curves in the CSD86350Q5D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) x 3.5” (L) x 0.062” (T) and 6 copper layers of 1 oz. copper thicknes Normalized Curves The normalized curves in the CSD86350Q5D data sheet provides guidance on the Power Loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve. Input Current (IIN) Gate Drive Current (IDD) VDD A Gate Drive V Voltage (VDD) VDD ENABLE VI CSD86350Q5D Driver IC DRVH PWM LL GND DRVL PWM A VIN BST TG TGR BG Control FET V Input Voltage (VIN) Output Current (IOUT) VO VSW A Sync FET PGND Averaging Circuit V Averaged Switched Node Voltage (VSW_AVG) S0475-01 Figure 28. Typical Application Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9 CSD86350Q5D SLPS223A – MAY 2010 – REVISED MAY 2010 www.ti.com Calculating Power Loss and SOA The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure will outline the steps the user should take to predict product performance for any set of system conditions. Design Example Operating Conditions: • Output Current = 25A • Input Voltage = 7V • Output Voltage = 1V • Switching Frequency = 800kHz • Inductor = 0.2µH Calculating Power Loss • • • • • • Power Loss at 25A = 3.5W (Figure 1) Normalized Power Loss for input voltage ≈ 1.07 (Figure 7) Normalized Power Loss for output voltage ≈ 0.95 (Figure 8) Normalized Power Loss for switching frequency ≈ 1.11 (Figure 6) Normalized Power Loss for output inductor ≈ 1.07 (Figure 9) Final calculated Power Loss = 3.5W x 1.07 x 0.95 x 1.11 x 1.07 ≈ 4.23W Calculating SOA Adjustments • • • • • SOA adjustment for input voltage ≈ 2ºC (Figure 7) SOA adjustment for output voltage ≈ -1.3ºC (Figure 8) SOA adjustment for switching frequency ≈ 2.8ºC (Figure 6) SOA adjustment for output inductor ≈ 1.6ºC (Figure 9) Final calculated SOA adjustment = 2 + (-1.3) + 2.8 + 1.6 ≈ 5.1ºC In the design example above, the estimated power loss of the CSD86350Q5D would increase to 4.23W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.1ºC. Figure 29 graphically shows how the SOA curve would be adjusted accordingly. 1. Start by drawing a horizontal line from the application current to the SOA curve. 2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature. 3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value. In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 5.1ºC. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature. 50 45 Output Current (A) 40 35 30 1 25 20 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3 µH 15 10 5 2 3 0 0 20 40 60 80 100 Board Temperature (°C) 120 140 G028 Figure 29. Power Block SOA 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated CSD86350Q5D www.ti.com SLPS223A – MAY 2010 – REVISED MAY 2010 RECOMMENDED PCB DESIGN OVERIEW There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief description on how to address each parameter is provided. Electrical Performance The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor. • The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 30). The example in Figure 30 uses 6x10µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8 should follow in order. • The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for the Driver IC will also connect to this pin. • The switching node of the output inductor should be placed relatively close to the Power Block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. (1) Thermal Performance The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel: • Intentionally space out the vias from each other to avoid a cluster of holes in a given area. • Use the smallest drill size allowed in your design. The example in Figure 30 uses vias with a 10 mil drill hole and a 16 mil capture pad. • Tent the opposite side of the via with solder-mask. In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities. K001 Figure 30. Recommended PCB Layout (Top Down View) (1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11 CSD86350Q5D SLPS223A – MAY 2010 – REVISED MAY 2010 www.ti.com MECHANICAL DATA Q5D Package Dimensions E2 K d2 5 4 4 6 3 3 D2 7 e d 2 8 2 7 1 E D1 9 1 8 d3 q L d1 L 5 b c1 6 E1 f Top View Bottom View Side View Pinout Exposed Tie Bar May Vary Position a q c E1 Front View Pin 1 Designation VIN Pin 2 VIN Pin 3 TG Pin 4 TGR Pin 5 BG Pin 6 VSW Pin 7 VSW Pin 8 VSW Pin 9 PGND M0187-01 DIM MILLIMETERS MIN MIN MAX a 1.40 1.55 0.055 0.061 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 d 1.630 1.730 0.064 0.068 d1 0.280 0.380 0.011 0.015 d2 0.200 0.300 0.008 0.012 d3 0.291 0.391 0.012 0.015 D1 4.900 5.100 0.193 0.201 D2 4.269 4.369 0.168 0.172 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.106 3.206 0.122 0.126 e 1.27 TYP 0.050 f 0.396 0.496 0.016 0.020 L 0.510 0.710 0.020 0.028 q 0.00 -- -- -- K 12 INCHES MAX Submit Documentation Feedback 0.812 0.032 Copyright © 2010, Texas Instruments Incorporated CSD86350Q5D www.ti.com SLPS223A – MAY 2010 – REVISED MAY 2010 Land Pattern Recommendation 3.480 0.415 0.530 0.345 0.650 5 4 0.650 0.620 0.620 4.460 4.460 1.920 8 1 1.270 0.400 0.850 0.850 6.240 M0188-01 NOTE: All dimensions are in mm, unless otherwise specified. For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5D Tape and Reel Information 5.50 ±0.05 B0 R 0.20 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30 TYP A0 = 5.30 ±0.10 B0 = 6.50 ±0.10 K0 = 1.90 ±0.10 M0191-01 NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified. 5. Thickness: 0.30 ±0.05mm 6. MSL1 260°C (IR and convection) PbF reflow compatible Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13 CSD86350Q5D SLPS223A – MAY 2010 – REVISED MAY 2010 www.ti.com REVISION HISTORY Changes from Original (May 2010) to Revision A Page • Changed graph title From: TYPICAL EFFICIENCY vs POWER LOSS To: TYPICAL POWER BLOCK EFFICIENCY and POWER LOSS ............................................................................................................................................................... 1 • Updated the Land Pattern Recommendation illustration .................................................................................................... 13 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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