RT8886A

®
RT8886A
2-Phase Controller with Dual Integrated Drivers for VR12.5
and VR12.6 Mobile CPU Core Power Supply
General Description
The RT8886A is a two phase CPU power controller with
dual integrated drivers for VR12.5 and VR12.6 compliant.
The RT8886A adopts the G-NAVPTM (Green Native AVP)
which is Richtek's proprietary topology derived from finite
DC gain of EA amplifier with current mode control, making
it easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning). Based on the GNAVPTM topology, the RT8886A also features a quick
response mechanism for optimized AVP performance
during load transient. The RT8886A supports mode
transition function with various operating states. A Serial
VID (SVID) interface is built in the RT8886A to
communicate with Intel VR12.5 and VR12.6 compliant
CPU. The RT8886A supports VID on-the-fly function with
different slew rates. By utilizing the G-NAVPTM topology,
the operating frequency of the RT8886A varies with VID,
load current and input voltage to further enhance the
efficiency even in CCM. Besides the G-NAVPTM, the
CCRCOT (Constant Current Ripple Constant On Time)
technology provides superior output voltage ripple over
the entire input/output range. The built-in high accuracy
DAC converts the SVID code ranging from 0.5V to 3.04V
with 10mV per step. The RT8886A integrates a high
accuracy ADC for platform setting functions, such as noload offset and over-current protection level. The RT8886A
provides VR ready output signals. It also features complete
fault protection functions including Over-Voltage (OV),
Under-Voltage (UV), Negative-Voltage (NV), Over-Current
(OC) and Under-Voltage Lockout (UVLO). The RT8886A
is available in the WQFN-32L 4x4 small foot print package.
Features


















Intel VR12.5 and VR12.6 Serial VID Interface
Compatible Power Management States
2/1 Phase PWM Controller with Dual Integrated
Drivers
G-NAVPTM Topology
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
Accurate Current Balance
System Thermal Compensated AVP
Diode Emulation Mode at Light Load Condition for
Single Phase
Fast transient Response
VR Ready Indicator
Thermal Throttling
Current Monitor Output
OVP, UVP, OCP, UVLO
Programmable DVID Slew Rate
DVID Enhancement
Small 32-Lead WQFN Package
RoHS Compliant and Halogen Free
Simplified Application Circuit
To PCH
To CPU
RT8886A
VR_RDY
PHASE1
VR_HOT
MOSFET
VCORE
VCLK
VDIO
PHASE2
MOSFET
ALERT
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8886A
Applications



Marking Information
VR12.5 and VR12.6 Intel Core Supply
Notebook Multi-phase CPU Core Supply
AVP Step-Down Converter
15= : Product Code
15=YM
DNN
YMDNN : Date Code
Ordering Information
Pin Configurations
RT8886A
(TOP VIEW)
PHASE2
LGATE2
PVCC
LGATE1
PHASE1
UGATE1
BOOT1
VR_RDY
Package Type
QW : WQFN-32L 4x4 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
32 31 30 29 28 27 26 25
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
UGATE2
BOOT2
EN
ISEN2P
ISEN2N
ISEN1N
ISEN1P
IMON
1
24
2
23
3
22
4
21
GND
5
6
20
33
7
19
18
8
17
TONSET
VCLK
ALERT
VDIO
VR_HOT
TSEN
IBIAS
SET3
VREF
COMP
FB
VSEN
RGND
VCC
SET1
SET2
9 10 11 12 13 14 15 16
WQFN-32L 4x4
Functional Pin Description
Pin No.
3
Pin Name
Pin Function
EN
VR Enable Control Input.
6, 5
ISEN [1:2] N
Negative Current Sense Inputs of Channel 1 and 2.
7, 4
ISEN [1:2] P
Positive Current Sense Inputs of Channel 1 and 2.
8
IMON
CPU CORE Current Monitor Output. This pin outputs a voltage proportional to
the output current. Don’t connect a bypass capacitor from this pin to GND or the
VREF pin.
9
VREF
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the
output voltage of the IMON pin.
10
COMP
CORE VR Compensation Node. This pin is error amplifier output pin.
11
FB
12
VSEN
13
RGND
Return Ground for VR. This pin is the negative node of the differential remote
voltage sensing.
14
VCC
Supply Voltage Input. Connect this pin to 5V and place a decoupling capacitor
2.2F at least. The decoupling capacitor should be placed as close to the PWM
controller as possible.
15
SET1
1 Platform Setting. Platform can use this pin to set DVID compensation time,
RSET, DVID compensation width and OCS.
Negative Input of the Error Amplifier. This pin is for output voltage feedback to
controller.
VR Voltage Sense Input. This pin is connected to the terminal of VR output
voltage.
st
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Pin No.
Pin Name
Pin Function
nd
SET2
2 Platform Setting. Platform can use this pin to set ICCMAX, QRTH and
QRWIDTH.
SET3
3 Platform Setting. Platform can use this to set Anti-ov ershoot function, zero
load-line, DVID slew rate, RSET selection at PS1, Anti-Overshoot enhancem ent
and ZCD threshold.
18
IBIAS
Internal Bias Current Setting. Connect a 100k resistor from this pin tied to
GND to set the internal current. Don’t connect a bypass pass capacitor from this
pin to GND.
19
TSEN
Thermal Sense Input for CORE VR.
20
VR_HOT
Thermal Monitor Output. (Active Low)
21
VDIO
VR and CPU Data Transmission Interface.
22
SVID Alert. (Active Low).
23
ALERT
VCLK
24
TONSET
On-time Setting. An on-time setting resistor is connected from this pin to input
voltage.
25
VR_RDY
VR Ready Indicator.
30
PVCC
Driver Power. Connect this pin to GND by a minimum 2.2F ceramic capacitor.
26, 2
BOOT [1:2]
Bootstrap Supply for High-Side Gate Driver.
27, 1
UGATE [1:2]
High-Side Gate Drive Output. Connect the pin to the Gate of high-side MOSFET.
28, 32
PHASE [1:2]
Switch Node of High-Side Driver. Connect the pin to high-side MOSFET Source
with the low-side MOSFET Drain and the inductor.
29, 31
LGATE [1:2]
Low-Side Gate Drive Output. This pin drives the Gate of low-side MOSFET.
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
16
rd
17
33
(Exposed Pad)
Synchronous Clock from the CPU.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8886A
VR_RDY
VCC
VSEN
EN
VR_HOT
ALERT
VDIO
IMONI
VCLK
TSEN
SET3
SET2
SET1
Function Block Diagram
UVLO
MUX
IBIAS
GND
VCC
ADC
From Control Logic
RGND
DAC
QR,
QRWIDTH,
OCP_TDC,
RSET
DAC
Soft-Start & Slew
Rate Control
VSET
FB
SVID Interface
Configuration
Registers Control
Logic
ERROR
AMP
+
-
TON
Load Line
Current Balance
Offset
Cancellation
ISEN2P
+
-
1/4
IB1
Ai
Current mirror
ISEN2N
-
IB2
PWM
CMP
IMONI
IMONI
+
OCS_TDC
OC
Current Balance
To Protection Logic
Dual
Phase
Driver
TON
GEN
-
RSET
IMON Filter
PWM1
QR
QRWIDTH
TON
Current mirror
+
TONSET
+
+
COMP
ISEN1P
ISEN1N
Loop Control
Protection Logic
PWM2
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
Current Balance
x100%
x100%
IB1
IB2
-
VSEN
OV/UV/NV
IMON VREF
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Operation
The RT8886A adopts the G-NAVPTM (Green Native AVP)
which is Richtek's proprietary topology derived from finite
DC gain of EA amplifier with current mode control, making
it easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
Loop Control Protection Logic
The G-NAVPTM controller is one type of current mode
constant on-time control with DC offset cancellation. The
approach can not only improve DC offset problem for
increasing system accuracy but also have fast transient
response. When current feedback signal reaches COMP
signal, the RT8886A generates an on-time width to achieve
PWM modulation.
Each phase current sense signal is sent to the current
balance circuit which adjusts the on-time of each phase
to optimize current sharing.
TON GEN
Generate the PWM signal sequentially according to the
phase control signal from the Loop Control Protection
Logic.
It controls the power on sequence, and the protection
behavior, and the operational phase number.
Current Balance
Offset Cancellation
Cancel the current/voltage ripple issue to get the accurate
VSEN.
UVLO
Detect the PVCC and VCC voltage and issue POR signal
as they are high enough.
DAC
SVID Interface/Configuration Registers/Control
Logic
Generate an analog signal according to the digital code
generated by Control Logic.
The interface that receives the SVID signal from CPU and
sends the relative signals to Loop Control Protection Logic
to execute the action by CPU.
Soft-Start & Slew Rate Control
Control the Dynamic VID slew rate of VSET according to
the SetVID fast or SetVID slow.
The registers save the pin setting data from ADC output.
The Control Logic controls the ADC timing and generates
the digital code of the VID that is relative to VSEN.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8886A
Table 1. VR12.5 and VR12.6 VID Code Table
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
0
0
0
0
0
0
1
01
0.500
0
0
0
0
0
0
1
0
02
0.510
0
0
0
0
0
0
1
1
03
0.520
0
0
0
0
0
1
0
0
04
0.530
0
0
0
0
0
1
0
1
05
0.540
0
0
0
0
0
1
1
0
06
0.550
0
0
0
0
0
1
1
1
07
0.560
0
0
0
0
1
0
0
0
08
0.570
0
0
0
0
1
0
0
1
09
0.580
0
0
0
0
1
0
1
0
0A
0.590
0
0
0
0
1
0
1
1
0B
0.600
0
0
0
0
1
1
0
0
0C
0.610
0
0
0
0
1
1
0
1
0D
0.620
0
0
0
0
1
1
1
0
0E
0.630
0
0
0
0
1
1
1
1
0F
0.640
0
0
0
1
0
0
0
0
10
0.650
0
0
0
1
0
0
0
1
11
0.660
0
0
0
1
0
0
1
0
12
0.670
0
0
0
1
0
0
1
1
13
0.680
0
0
0
1
0
1
0
0
14
0.690
0
0
0
1
0
1
0
1
15
0.700
0
0
0
1
0
1
1
0
16
0.710
0
0
0
1
0
1
1
1
17
0.720
0
0
0
1
1
0
0
0
18
0.730
0
0
0
1
1
0
0
1
19
0.740
0
0
0
1
1
0
1
0
1A
0.750
0
0
0
1
1
0
1
1
1B
0.760
0
0
0
1
1
1
0
0
1C
0.770
0
0
0
1
1
1
0
1
1D
0.780
0
0
0
1
1
1
1
0
1E
0.790
0
0
0
1
1
1
1
1
1F
0.800
0
0
1
0
0
0
0
0
20
0.810
0
0
1
0
0
0
0
1
21
0.820
0
0
1
0
0
0
1
0
22
0.830
0
0
1
0
0
0
1
1
23
0.840
0
0
1
0
0
1
0
0
24
0.850
0
0
1
0
0
1
0
1
25
0.860
0
0
1
0
0
1
1
0
26
0.870
0
0
1
0
0
1
1
1
27
0.880
0
0
1
0
1
0
0
0
28
0.890
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is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
0
1
0
1
0
0
1
29
0.900
0
0
1
0
1
0
1
0
2A
0.910
0
0
1
0
1
0
1
1
2B
0.920
0
0
1
0
1
1
0
0
2C
0.930
0
0
1
0
1
1
0
1
2D
0.940
0
0
1
0
1
1
1
0
2E
0.950
0
0
1
0
1
1
1
1
2F
0.960
0
0
1
1
0
0
0
0
30
0.970
0
0
1
1
0
0
0
1
31
0.980
0
0
1
1
0
0
1
0
32
0.990
0
0
1
1
0
0
1
1
33
1.000
0
0
1
1
0
1
0
0
34
1.010
0
0
1
1
0
1
0
1
35
1.020
0
0
1
1
0
1
1
0
36
1.030
0
0
1
1
0
1
1
1
37
1.040
0
0
1
1
1
0
0
0
38
1.050
0
0
1
1
1
0
0
1
39
1.060
0
0
1
1
1
0
1
0
3A
1.070
0
0
1
1
1
0
1
1
3B
1.080
0
0
1
1
1
1
0
0
3C
1.090
0
0
1
1
1
1
0
1
3D
1.100
0
0
1
1
1
1
1
0
3E
1.110
0
0
1
1
1
1
1
1
3F
1.120
0
1
0
0
0
0
0
0
40
1.130
0
1
0
0
0
0
0
1
41
1.140
0
1
0
0
0
0
1
0
42
1.150
0
1
0
0
0
0
1
1
43
1.160
0
1
0
0
0
1
0
0
44
1.170
0
1
0
0
0
1
0
1
45
1.180
0
1
0
0
0
1
1
0
46
1.190
0
1
0
0
0
1
1
1
47
1.200
0
1
0
0
1
0
0
0
48
1.210
0
1
0
0
1
0
0
1
49
1.220
0
1
0
0
1
0
1
0
4A
1.230
0
1
0
0
1
0
1
1
4B
1.240
0
1
0
0
1
1
0
0
4C
1.250
0
1
0
0
1
1
0
1
4D
1.260
0
1
0
0
1
1
1
0
4E
1.270
0
1
0
0
1
1
1
1
4F
1.280
0
1
0
1
0
0
0
0
50
1.290
0
1
0
1
0
0
0
1
51
1.300
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8886A
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
1
0
1
0
0
1
0
52
1.310
0
1
0
1
0
0
1
1
53
1.320
0
1
0
1
0
1
0
0
54
1.330
0
1
0
1
0
1
0
1
55
1.340
0
1
0
1
0
1
1
0
56
1.350
0
1
0
1
0
1
1
1
57
1.360
0
1
0
1
1
0
0
0
58
1.370
0
1
0
1
1
0
0
1
59
1.380
0
1
0
1
1
0
1
0
5A
1.390
0
1
0
1
1
0
1
1
5B
1.400
0
1
0
1
1
1
0
0
5C
1.410
0
1
0
1
1
1
0
1
5D
1.420
0
1
0
1
1
1
1
0
5E
1.430
0
1
0
1
1
1
1
1
5F
1.440
0
1
1
0
0
0
0
0
60
1.450
0
1
1
0
0
0
0
1
61
1.460
0
1
1
0
0
0
1
0
62
1.470
0
1
1
0
0
0
1
1
63
1.480
0
1
1
0
0
1
0
0
64
1.490
0
1
1
0
0
1
0
1
65
1.500
0
1
1
0
0
1
1
0
66
1.510
0
1
1
0
0
1
1
1
67
1.520
0
1
1
0
1
0
0
0
68
1.530
0
1
1
0
1
0
0
1
69
1.540
0
1
1
0
1
0
1
0
6A
1.550
0
1
1
0
1
0
1
1
6B
1.560
0
1
1
0
1
1
0
0
6C
1.570
0
1
1
0
1
1
0
1
6D
1.580
0
1
1
0
1
1
1
0
6E
1.590
0
1
1
0
1
1
1
1
6F
1.600
0
1
1
1
0
0
0
0
70
1.610
0
1
1
1
0
0
0
1
71
1.620
0
1
1
1
0
0
1
0
72
1.630
0
1
1
1
0
0
1
1
73
1.640
0
1
1
1
0
1
0
0
74
1.650
0
1
1
1
0
1
0
1
75
1.660
0
1
1
1
0
1
1
0
76
1.670
0
1
1
1
0
1
1
1
77
1.680
0
1
1
1
1
0
0
0
78
1.690
0
1
1
1
1
0
0
1
79
1.700
0
1
1
1
1
0
1
0
7A
1.710
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
1
1
1
1
0
1
1
7B
1.720
0
1
1
1
1
1
0
0
7C
1.730
0
1
1
1
1
1
0
1
7D
1.740
0
1
1
1
1
1
1
0
7E
1.750
0
1
1
1
1
1
1
1
7F
1.760
1
0
0
0
0
0
0
0
80
1.770
1
0
0
0
0
0
0
1
81
1.780
1
0
0
0
0
0
1
0
82
1.790
1
0
0
0
0
0
1
1
83
1.800
1
0
0
0
0
1
0
0
84
1.810
1
0
0
0
0
1
0
1
85
1.820
1
0
0
0
0
1
1
0
86
1.830
1
0
0
0
0
1
1
1
87
1.840
1
0
0
0
1
0
0
0
88
1.850
1
0
0
0
1
0
0
1
89
1.860
1
0
0
0
1
0
1
0
8A
1.870
1
0
0
0
1
0
1
1
8B
1.880
1
0
0
0
1
1
0
0
8C
1.890
1
0
0
0
1
1
0
1
8D
1.900
1
0
0
0
1
1
1
0
8E
1.910
1
0
0
0
1
1
1
1
8F
1.920
1
0
0
1
0
0
0
0
90
1.930
1
0
0
1
0
0
0
1
91
1.940
1
0
0
1
0
0
1
0
92
1.950
1
0
0
1
0
0
1
1
93
1.960
1
0
0
1
0
1
0
0
94
1.970
1
0
0
1
0
1
0
1
95
1.980
1
0
0
1
0
1
1
0
96
1.990
1
0
0
1
0
1
1
1
97
2.000
1
0
0
1
1
0
0
0
98
2.010
1
0
0
1
1
0
0
1
99
2.020
1
0
0
1
1
0
1
0
9A
2.030
1
0
0
1
1
0
1
1
9B
2.040
1
0
0
1
1
1
0
0
9C
2.050
1
0
0
1
1
1
0
1
9D
2.060
1
0
0
1
1
1
1
0
9E
2.070
1
0
0
1
1
1
1
1
9F
2.080
1
0
1
0
0
0
0
0
A0
2.090
1
0
1
0
0
0
0
1
A1
2.100
1
0
1
0
0
0
1
0
A2
2.110
1
0
1
0
0
0
1
1
A3
2.120
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8886A
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
0
1
0
0
1
0
0
A4
2.130
1
0
1
0
0
1
0
1
A5
2.140
1
0
1
0
0
1
1
0
A6
2.150
1
0
1
0
0
1
1
1
A7
2.160
1
0
1
0
1
0
0
0
A8
2.170
1
0
1
0
1
0
0
1
A9
2.180
1
0
1
0
1
0
1
0
AA
2.190
1
0
1
0
1
0
1
1
AB
2.200
1
0
1
0
1
1
0
0
AC
2.210
1
0
1
0
1
1
0
1
AD
2.220
1
0
1
0
1
1
1
0
AE
2.230
1
0
1
0
1
1
1
1
AF
2.240
1
0
1
1
0
0
0
0
B0
2.250
1
0
1
1
0
0
0
1
B1
2.260
1
0
1
1
0
0
1
0
B2
2.270
1
0
1
1
0
0
1
1
B3
2.280
1
0
1
1
0
1
0
0
B4
2.290
1
0
1
1
0
1
0
1
B5
2.300
1
0
1
1
0
1
1
0
B6
2.310
1
0
1
1
0
1
1
1
B7
2.320
1
0
1
1
1
0
0
0
B8
2.330
1
0
1
1
1
0
0
1
B9
2.340
1
0
1
1
1
0
1
0
BA
2.350
1
0
1
1
1
0
1
1
BB
2.360
1
0
1
1
1
1
0
0
BC
2.370
1
0
1
1
1
1
0
1
BD
2.380
1
0
1
1
1
1
1
0
BE
2.390
1
0
1
1
1
1
1
1
BF
2.400
1
1
0
0
0
0
0
0
C0
2.410
1
1
0
0
0
0
0
1
C1
2.420
1
1
0
0
0
0
1
0
C2
2.430
1
1
0
0
0
0
1
1
C3
2.440
1
1
0
0
0
1
0
0
C4
2.450
1
1
0
0
0
1
0
1
C5
2.460
1
1
0
0
0
1
1
0
C6
2.470
1
1
0
0
0
1
1
1
C7
2.480
1
1
0
0
1
0
0
0
C8
2.490
1
1
0
0
1
0
0
1
C9
2.500
1
1
0
0
1
0
1
0
CA
2.510
1
1
0
0
1
0
1
1
CB
2.520
1
1
0
0
1
1
0
0
CC
2.530
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10
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
1
0
0
1
1
0
1
CD
2.540
1
1
0
0
1
1
1
0
CE
2.550
1
1
0
0
1
1
1
1
CF
2.560
1
1
0
1
0
0
0
0
D0
2.570
1
1
0
1
0
0
0
1
D1
2.580
1
1
0
1
0
0
1
0
D2
2.590
1
1
0
1
0
0
1
1
D3
2.600
1
1
0
1
0
1
0
0
D4
2.610
1
1
0
1
0
1
0
1
D5
2.620
1
1
0
1
0
1
1
0
D6
2.630
1
1
0
1
0
1
1
1
D7
2.640
1
1
0
1
1
0
0
0
D8
2.650
1
1
0
1
1
0
0
1
D9
2.660
1
1
0
1
1
0
1
0
DA
2.670
1
1
0
1
1
0
1
1
DB
2.680
1
1
0
1
1
1
0
0
DC
2.690
1
1
0
1
1
1
0
1
DD
2.700
1
1
0
1
1
1
1
0
DE
2.710
1
1
0
1
1
1
1
1
DF
2.720
1
1
1
0
0
0
0
0
E0
2.730
1
1
1
0
0
0
0
1
E1
2.740
1
1
1
0
0
0
1
0
E2
2.750
1
1
1
0
0
0
1
1
E3
2.760
1
1
1
0
0
1
0
0
E4
2.770
1
1
1
0
0
1
0
1
E5
2.780
1
1
1
0
0
1
1
0
E6
2.790
1
1
1
0
0
1
1
1
E7
2.800
1
1
1
0
1
0
0
0
E8
2.810
1
1
1
0
1
0
0
1
E9
2.820
1
1
1
0
1
0
1
0
EA
2.830
1
1
1
0
1
0
1
1
EB
2.840
1
1
1
0
1
1
0
0
EC
2.850
1
1
1
0
1
1
0
1
ED
2.860
1
1
1
0
1
1
1
0
EE
2.870
1
1
1
0
1
1
1
1
EF
2.880
1
1
1
1
0
0
0
0
F0
2.890
1
1
1
1
0
0
0
1
F1
2.900
1
1
1
1
0
0
1
0
F2
2.910
1
1
1
1
0
0
1
1
F3
2.920
1
1
1
1
0
1
0
0
F4
2.930
1
1
1
1
0
1
0
1
F5
2.940
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8886A
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
1
1
1
0
1
1
0
F6
2.950
1
1
1
1
0
1
1
1
F7
2.960
1
1
1
1
1
0
0
0
F8
2.970
1
1
1
1
1
0
0
1
F9
2.980
1
1
1
1
1
0
1
0
FA
2.990
1
1
1
1
1
0
1
1
FB
3.000
1
1
1
1
1
1
0
0
FC
3.010
1
1
1
1
1
1
0
1
FD
3.020
1
1
1
1
1
1
1
0
FE
3.030
1
1
1
1
1
1
1
1
FF
3.040
Code
Commands
00h
not supported
Table 2. Standard Serial VID Commands
Master
Slave
Payload
Payload
Description
Contents
Contents
N/A
N/A
N/A
01h
SetVID_Fast
VID code
02h
03h
SetVID_Slow
SetVID_Decay
04h
SetPS
05h
SetRegADR
06h
SetReg DAT
07h
GetReg
08h to
1Fh
not supported
VID code
VID code
Byte
indicating
power states
Pointer of
registers in
data table
New data
register
content
N/A
1. Set new target VID code, VR jumps to new VID target
with slew rate set by SET3 pin.
2. Set VR_Settled when VR reaches target VID voltage.
N/A
1. Set new target VID code, VR jumps to new VID target
with programmable slew rate through register 2Ah as a
fraction of the fast slew rate.
2. Set VR_Settled when VR reaches target VID voltage.
N/A
1. Set new target VID code, VR jumps to new VID target,
but does not control the slew rate. The output voltage
decays at a rate proportional to the load current.
2. Low side MOSFET is not allowed to sync current.
3. ACK 11b when target higher than current VOUT voltage.
4. ACK 10b when target lower than current VOUT voltage.
N/A
1. Set power state.
2. ACK 11b when not support.
3. ACK 10b even slave not change configuration.
4. ACK 11b for still running SetVID command.
5. VR remains in lower state when receiving SetVID
(decay).
N/A
1. Set the pointer of the data register.
2. ACK 11b for address outside of support.
3. NAK 01b for SetADR (all call).
N/A
1. Write the contents to the data register.
2. NAK 01b for SetReg (all call).
Specified
Register
Contents
N/A
N/A
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12
1. Slave returns the contents of the specified register as the
payload.
2. ACK 11b for non support address.
3. NAK 01b for GetReg (all call).
N/A
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Table3. SVID Data and Configuration Register
Index
Register Name
Description
Access
Default
00h
Vendor ID
Vendor ID
RO, Vendor
1Eh
01h
Product ID
Product ID
RO, Vendor
84h
02h
Product Revision
Product Revision
RO, Vendor
00h
05h
Protocol ID
SVID Protocol ID
RO, Vendor
02h
06h
Capability
Bit mapped register, identifies the SVID VR Capabilities
and which of the optional telemetry register is supported.
RO, Vendor
81h
10h
Status_1
Data register containing the status of VR.
R-M, W-PWM
00h
11h
Status_2
Data register containing the status of transmission.
R-M, W-PWM
00h
12h
Temperature
Zone
Data register showing temperature zone that has been
R-M, W-PWM
entered.
00h
15h
IOUT
At PS0 to PS2, IOUT report data from ADC sense IMON
voltage. When power state at PS3, the IOUT report data R-M, W-PWM
is fix to 04h.
00h
1Ch
Status_2_lastread
The register contains a copy of the status_2.
R-M, W-PWM
00h
21h
ICC Max
Data register containing the ICC max the platform
supports. Binary format in A IE 64h = 100A.
RO, Platform
7Dh
22h
Temp Max
Data register containing the temperature max the
platform supports.
Binary format in C IE 64h = 100C.
RO, Platform
64h
24h
SR-fast
Data register containing the capability of fast slew rate the
platform can sustain. Binary format in mV/S IE 0Ch =
12mV/s.
RO
0Ch
25h
SR-slow
Data register containing the capability of slow slew rate.
Binary format in mV/S IE 03h = 3mV/S.
RO
03h
2Ah
Slow Slew Rate
Selector
The register is programmed by master and set the slow
slew rate.
RW, Master
02h
2Bh
PS4 Exit Latency
Data register containing the latency of exiting PS4.
RO
7Fh
2Ch
PS3 Exit Latency
Data register containing the latency of exiting PS3.
RO
3Fh
2Dh
Enable to Ready
for SVID
Data register containing the latency from Enable
assertion to the VR being ready to accept an SVID
command.
RO
BFh
30h
VOUT Max
The register is programmed by master and sets the
maximum VID.
RW, Master
D5h
31h
VID Setting
Data register containing currently programmed VID.
RW, Master
00h
32h
Power State
Register containing the current programmed power state.
RW, Master
00h
33h
Offset
Set offset in VID steps.
RW, Master
00h
34h
Multi VR
Configuration
Bit mapped data register which configures multiple VRs
behavior on the same bus.
RW, Master
00h
35h
Pointer
Scratch pad register for temporary storage of the
SetRegADR pointer register.
RW, Master
30h
Notes :
W-PWM = Write by PWM Only
RO = Read Only
Vendor = Hard Coded by VR Vendor
RW = Read/Write
Platform = Programmed by the Master
R-M = Read by Master
PWM = Programmed by the VR Control IC
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
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13
RT8886A
Absolute Maximum Ratings














(Note 1)
VCC, PVCC to GND -------------------------------------------------------------------------------- −0.3V to 6V
RGND to GND ---------------------------------------------------------------------------------------- −0.3V to 0.3V
TONSET to GND ------------------------------------------------------------------------------------- −0.3V to 28V
BOOTx to PHASEx --------------------------------------------------------------------------------- −0.3V to 6.5V
PHASEx to GND
DC ------------------------------------------------------------------------------------------------------- −0.3V to 32V
< 20ns ------------------------------------------------------------------------------------------------- −8V to 38V
LGATEx to GND
DC ------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (PVCC + 0.3V)
< 20ns ------------------------------------------------------------------------------------------------- (GND − 5V) to (PVCC + 5V)
UGATEx to GND
DC ------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 20ns ------------------------------------------------------------------------------------------------- (VPHASE − 5V) to (VBOOT + 5V)
Other Pins --------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
Power Dissipation, PD @ TA = 25°C
WQFN-32L 4x4 -------------------------------------------------------------------------------------- 3.59W
Package Thermal Resistance (Note 2)
WQFN-32L 4x4, θJA --------------------------------------------------------------------------------- 27.8°C/W
WQFN-32L 4x4, θJC -------------------------------------------------------------------------------- 7°C/W
Junction Temperature ------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------- 260°C
Storage Temperature Range ---------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------ 2kV
Recommended Operating Conditions



(Note 4)
Supply Voltage, PVCC ----------------------------------------------------------------------------- 4.5V to 5.5V
Junction Temperature Range ---------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
5
5.5
V
Supply Input
Supply Voltage
VCC
Supply Current
IVCC
VEN = H, No switching
--
4.1
--
mA
Supply Current at PS3
IVCC_PS3
VEN = H, No switching
--
2.7
--
mA
Supply Current at PS4
IVCC_PS4
VEN = H, No switching
--
--
200
A
Power Supply Voltage
PVCC
4.5
--
5.5
V
Power Supply Current
IPVCC
--
150
--
A
Shutdown Current
ISHDN
--
--
5
A
VEN = 0V
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is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VDAC = 1.5V 2.3V
0.5
0
0.5
% of
VID
VDAC = 1V 1.49V
8
0
8
10
0
10
Reference and DAC
DAC Accuracy
VFB
VDAC = 0.5V 0.99V
mV
PVCC Power On Reset (POR)
POR Threshold
POR Hysteresis
VPOR_r
PVCC Rising
--
3.85
4.1
VPOR_f
PVCC Falling
3.4
3.65
--
--
0.2
--
SetVID slow pin, setting SR = 00
3
3.3
3.75
SetVID slow pin, setting SR = 01
6
6.6
7.5
SetVID slow pin, setting SR = 10
9
9.9
11.25
SetVID slow pin, setting SR = 11
12
13.2
15
SetVID fast pin, setting SR = 00
12
13.2
15
SetVID fast pin, setting SR = 01
24
26.4
30
SetVID fast pin, setting SR = 10
36
39.6
45
SetVID fast pin, setting SR = 11
48
52.8
60
VPOR_HYS
V
V
Slew Rate
Dynamic VID Slew Rate
SR
mV/s
EA Amplifier
DC Gain
ADC
RL = 47k
70
--
--
dB
Gain-Bandwidth Product
GBW
4
5
--
MHz
Slew Rate
SREA
CLOAD = 5pF
CLOAD = 10pF (Gain = 4, RF = 47k,
VOUT = 0.5V to 3V)
RL = 47k
5
--
--
V/s
0.5
--
3.6
V
VCOMP = 2V
--
5
--
mA
Output Voltage Range
VCOMP
Maximum Source/Sink
IOUTEA
Current
Load Line Current Gain Amplifier
Input Offset Voltage
VILOFS
VIMON = 1V
5
--
5
mV
Current Gain
AILGAIN
VIMON VVREF = 1V,
VFB = VCOMP = 1.75V
--
1/4
--
A/A
0.8
--
0.8
mV
1
--
--
M
0.97
1
1.03
A/A
9
--
150
mV
Current Sensing Amplifier
Input Offset Voltage
VOSCS
Impedance at Positive Input RISENxP
Current Mirror Gain
AMIRROR
Current Sensing Voltage
VCS
IIMON / I SENxN
TON Setting
TONSET Pin Voltage
VTON
IRTON = 20A, VDAC = 1.7V
1.6
1.7
1.8
V
On-Time Setting
TON
IRTON = 20A, VDAC = 1.7V
450
500
550
ns
Input Current Range
IRTON
VDAC = 1.7V
6
--
100
A
Minimum Off time
TOFF
VDAC = 1.7V
--
250
--
ns
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT8886A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
1.85
2
--
V
4.1
4.3
4.45
V
200
VID
+ 350
1850
-VID
+ 400
1900
mV
VID lower than 1.5V
-VID
+ 300
1800
Respect to VID voltage
400
350
300
mV
VNV
100
70
--
mV
Logic-High
VIH
0.7
--
--
Logic-Low
VIL
--
--
0.3
1
--
1
A
IBIAS
IBIAS Pin Voltage
VIBIAS
RIBIAS = 100k
Protections
Under Voltage Lockout
Threshold
Over Voltage Protection
Threshold
Under Voltage Protection
Threshold
Negative Voltage Protection
Threshold
EN and VR_RDY
EN Input
Voltage
VUVLO
VUVLO
VOV
VUV
Falling edge hysteresis
VID higher than 1.5V
Leakage Current of EN
mV
V
VR_RDY Delay
TVR_RDY
VSEN = VBoot to VR_RDY High
3
4.5
6
s
VR_RDY Pull Low Voltage
VPGOOD
IVR_RDY = 10mA
--
--
0.13
V
VIH
Respect to INTEL Spec. with 50mV
hysteresis
0.65
--
--
VIL
--
--
0.45
ILEAK_IN
1
--
1
A
--
--
0.13
V
0.55
0.6
0.65
V
VBOOT Voltage set to 1.7V
1.692
1.7
1.708
V
VIMON VIMON_INI = 1.6V
252
255
258
VIMON VIMON_INI = 0.8V
125
128
131
0
0
3
--
200
--
s
Serial VID and VR_HOT
VCLK, VDIO
Leakage Current of VCLK,
VDIO, ALERT and VR_HOT
V
IVDIO = 10mA
VDIO, ALERT and VR_HOT
IALERT = 10mA
Pull Low Voltage
IVR_HOT = 10mA
VREF and VBOOT
VREF Voltage
VREF
VBOOT Voltage
VBOOT
ADC
Digital IMON Set
VIMON
VIMON VIMON_INI = 0V
Decimal
Update Period of IMON
TIMON
TSEN Threshold for
Tmp_Zone [7] transition
VTSEN
100C
--
1.887
--
V
TSEN Threshold for
Tmp_Zone [6] transition
VTSEN
97C
--
1.837
--
V
TSEN Threshold for
Tmp_Zone [5] transition
VTSEN
94C
--
1.784
--
V
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16
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
TSEN Threshold for
Tmp_Zone [4] transition
VTSEN
91C
--
1.729
--
V
TSEN Threshold for
Tmp_Zone [3] transition
VTSEN
88C
--
1.672
--
V
TSEN Threshold for
Tmp_Zone [2] transition
VTSEN
85C
--
1.612
--
V
TSEN Threshold for
Tmp_Zone [1] transition
VTSEN
82C
--
1.551
--
V
TSEN Threshold for
Tmp_Zone [0] transition
VTSEN
75C
--
1.402
--
V
Update Period of TSEN
tTSEN
--
50
--
s
CICCMAX1
VICCMAX = 0.403V
58
64
70
CICCMAX2
VICCMAX = 0.806V
122
128
134
CICCMAX3
VICCMAX = 1.6V
248
256
260
UGATEx Rise Time
tUGATEr
3nF load
--
8
--
ns
UGATEx Fall Time
tUGATEf
3nF load
--
8
--
ns
LGATEx Rise Time
tLGATEr
3nF load
--
8
--
ns
LGATEx Fall Time
tLGATEf
3nF load
--
4
--
ns
tPDHU
Outputs Unloaded
--
20
--
ns
tPDHL
Outputs Unloaded
--
20
--
ns
RUGATEsr
100mA Source Current
--
1
--

RUGATEsk
100mA Sink Current
--
1
--

RLGATEsr
100mA Source Current
--
1
--

RLGATEsk
100mA Sink Current
--
0.5
--

Digital Code of ICCMAX
Decimal
Switching Time
UGATEx Turn-On
Propagation Delay
LGATEx Turn-On
Propagation Delay
Output
UGATEx Driver Source
Resistance
UGATEx Driver Sink
Resistance
LGATEx Driver Source
Resistance
LGATEx Driver Sink
Resistance
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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18
VCC
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
To CPU
VIN
R10
5.6k
R22
150
C18
0.47µF
R21
130
R14
100k
Enable
R19
75
100k
ß = 4485
R18
10k
R15
RNTC2 16.24k
R20
130
VCCIO
9.34k
R17
R4
11.85k
C2
2.2µF
VCC
TSEN
ALERT
VDIO
VCLK
VR_HOT
VR_RDY
IMON
VREF
IBIAS
3 EN
22
21
23
20
25
8
9
18
GND
PVCC
11
10
12
5
4
31
32
1
2
6
7
29
28
27
26
30
RGND 13
FB
COMP
VSEN
ISENN2
ISENP2
LGATE2
PHASE2
UGATE2
BOOT2
ISENN1
ISENP1
LGATE1
PHASE1
UGATE1
BOOT1
RT8886A
24 TONSET
19
16 SET2
15 SET1
17 SET3
14
33 (Exposed Pad)
R6
25.37k
R16
17.2k
C3
0.1µF
R13
270k
R11 R8
6.2k 20.82k
R12
1
R7 242.7k
R5 84.87k
R3 20.15k
RNTC1
100k
ß = 4485
R9
100k
VREF
5V
R2
2.2
R37
10k
C14
82pF
C17
R26
240
Optional
R27
C7 1µF
R34
240
C16
Optional
C15
Optional
C11
R33
VSS_SENSE
VCC_SENSE
Optional
R35
C12 1µF
L2
Optional 220nH / 0.875m
C10
22µF
C6
R25
R36 680
Q2
Q1
VIN
C5
22µF
C8
22µFx23
R28
100
VCC_SENSE
L1
Optional 220nH / 0.875m
R30 680
Q2
Q1
VIN
5V
Optional
R38
50k
C13
10pF
R32
0
C9
R31 0.1µF
2.2
R24
0
C4
R23 0.1µF
2.2
C1
2.2µF
R1
1
LOAD
VCORE_OUT
R29
100
VSS_SENSE
RT8886A
Typical Application Circuit
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DS8886A-00 November 2013
RT8886A
Typical Operating Characteristics
CORE VR Power Off from EN
CORE VR Power On from EN
V CORE
(1V/Div)
V CORE
(1V/Div)
EN
(2V/Div)
EN
(2V/Div)
VR_RDY
(2V/Div)
UGATE1
(50V/Div)
VR_RDY
(2V/Div)
UGATE1
(50V/Div)
VIN = 19V, No Load, Boot VID 1.7V
Time (200μs/Div)
Time (200μs/Div)
CORE VR OCP
CORE VR OVP
V CORE
(1V/Div)
I LOAD
(50A/Div)
V CORE
(1V/Div)
VR_RDY
(2V/Div)
VR_RDY
(1V/Div)
UGATE1
(50V/Div)
UGATE1
(20V/Div)
LGATE1
(20V/Div)
VIN = 19V, Boot VID 1.7V
VIN = 19V, Boot VID 1.7V
Time (100μs/Div)
Time (20μs/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Down
V CORE
V CORE
VCLK
(1V/Div)
V CORE
(500mV/Div)
V CORE
(500mV/Div)
VDIO
(1V/Div)
VDIO
(1V/Div)
ALERT
(2V/Div)
VIN = 19V, No Load, Boot VID 1.7V
VCLK
(1V/Div)
VIN = 19V, VID = 1.6V to 1.8V, Slew Rate = Slow
Time (10μs/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
ALERT
(2V/Div)
VIN = 19V, VID = 1.8V to 1.6V, Slew Rate = Slow
Time (10μs/Div)
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19
RT8886A
CORE VR Dynamic VID Down
CORE VR Dynamic VID Up
V CORE
V CORE
VCLK
(1V/Div)
V CORE
(500mV/Div)
V CORE
(500mV/Div)
VDIO
(1V/Div)
VDIO
(1V/Div)
ALERT
(2V/Div)
VCLK
(1V/Div)
VIN = 19V, VID = 1.6V to 1.8V, Slew Rate = Fast
ALERT
(2V/Div)
VIN = 19V, VID = 1.8V to 1.6V, Slew Rate = Fast
Time (5μs/Div)
Time (5μs/Div)
CORE VR Mode Transient
CORE VR Mode Transient
VCORE 1.7V
VCORE 1.7V
VCLK
(1V/Div)
VCLK
(1V/Div)
UGATE1
(50V/Div)
UGATE1
(50V/Div)
LGATE1
(10V/Div)
LGATE1
(10V/Div)
VIN = 19V, VID = 1.7V, PS0 to PS2, ILOAD = 1A
VIN = 19V, VID = 1.7V, PS2 to PS0, ILOAD = 1A
Time (50μs/Div)
Time (50μs/Div)
CORE VR Thermal Monitoring
VIMON vs. Load Current
2.5
VIMON (V)
2.0
VR_HOT
(1V/Div)
TSEN
(500mV/Div)
1.5
1.0
0.5
VIN = 12V, TSEN Sweep from 1.7V to 2.1V
0.0
Time (10ms/Div)
0
10
20
30
40
50
Load Current (A)
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is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Applications information
The RT8886A is a 2/1 multiphase synchronous Buck
controller designed to meet Intel VR12.5 and VR12.6
compatible CPU specification with a serial SVID control
interface. The controller uses an ADC to implement all
kinds of settings to save a total number of pins for easily
using and increasing PCB space utilization.
G-NAVPTM Control Mode
The RT8886A adopts the G-NAVPTM controller, which is a
current mode constant on-time control with DC offset
cancellation. The approach can not only improve DC offset
problem for increasing system accuracy but also provide
fast transient response. For the RT8886A, when current
feedback signal reaches comp signal to generate an ontime width to achieve PWM modulation. Figure 1 shows
the basic G-NAVPTM behavior waveforms in continuous
conduct mode (CCM).
Current feedback signal
Comp signal
PWM1
Diode Emulation Mode (DEM)
As well-known, the dominate power loss is switching
related loss during light load, hence VR needs to be
operated in asynchronous mode (or called discontinuous
conduct mode, DCM) to reduce switching related loss
since switching frequency is dependent on loading in the
asynchronous mode. The RT8886A can operate in Diode
Emulation Mode (DEM) in order to improve light load
efficiency. In DEM operation, the behavior of the low-side
MOSFET(s) needs to work like a diode, that is, the lowside MOSFET(s) will be turned on when the phase voltage
is a negative value, i.e. the inductor current follows from
Source to Drain of low-side MOSFET(s). The low-side
MOSFET(s) will be turned off when phase voltage is a
positive value, i.e. reversed current is not allowed. The
positive voltage threshold (ZCD threshold) of low-side
MOSFET(s) turn off is set by the SET3 pin in Table 9.
Figure 2 shows the control behavior in DEM. Figure 3
shows the G-NAVPTM operation in DEM to illustrate the
control behaviors. When the load decreases, the discharge
time of output capacitors increases during UGATE and
LGATE are turned off. Hence, the switching frequency
and switching losses will be reduced to improve efficiency
in light load condition.
PWM2
Inductor current
PWM3
Figure 1 (a). G-NAVPTM Behavior Waveforms in CCM in
Steady State
Phase node
Current feedback signal
UGATE
Comp signal
LGATE
Figure 2. Diode Emulation Mode (DEM) in Steady State
PWM1
PWM2
PWM3
Figure 1 (b). G-NAVPTM Behavior Waveforms in CCM in
Load Transient
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21
RT8886A
Inductor
current signal
Output capacitor
discharge slope
COMP signal
UGATE
LGATE
(a) Lighter Load Condition in DEM.
Capacitor discharge slope is lower than Figure 3 (b).
Inductor
current signal
Output capacitor
discharge slope
COMP signal
UGATE
LGATE
(b) Load Increased Condition in DEM.
Capacitor discharge slope is Higher than Figure 3 (a).
Figure 3. G-NAVPTM Operation in DEM.
Phase Interleaving Function
The RT8886A is a multiphase controller, which has a phase
interleaving function, 180 degree phase shift for 2-phase
operation which can help reduce output voltage ripple and
EMI problem.
Where C = 18.2pF. By using the relationship between
TON and fSW, the switching frequency fSW is :

  VDAC(MAX) 
1
fSW(MAX) = 
   VIN(MAX) 
T
ON(MAX)

 

Where
FSW(MAX) is the maximum switching frequency.
Switching Frequency (TON) Setting
The RT8886A is one kind of constant on-time control. The
patented CCRCOT (Constant Current Ripple COT)
technology can generate an adaptive on-time with input
voltage and VID code to obtain a constant current ripple.
So that the output voltage ripple can be controlled nearly
like a constant as different input and output voltage change.
Connect a resistor RTON between input terminal and the
TONSET pin to set the on-time width.
TON =
RTON  C  0.55
VIN  VDAC
TON =
RTON  C  VDAC / 4
VIN  VDAC
 VDAC
< 2.2V 
 VDAC
 2.2V 
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22
VDAC(MAX) is the maximum VDAC of application.
VIN(MAX) is the maximum application input voltage.
TON(MAX) is derived from TON equation with maximum
parameters (VIN(MAX), VDAC(MAX)).
When load increases, on-time keeps constant. The
off-time width will be reduced so that loading can load
more power from input terminal to regulate output voltage.
Hence, the loading current increases in case the switching
frequency also increases. Higher switching frequency
operation can reduce power components' size and PCB
space, trading off the whole efficiency since switching
related loss increases, vice versa.
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DS8886A-00 November 2013
RT8886A
Per Phase Current Sense
Total Current Sense
In the RT8886A, the current signal is used for load-line
setting and OC (Over Current) protection. The inductor
current sense method adopts the lossless current sensing
for allowing high efficiency as illustrated in the Figure 4.
When inductance and DCR time constant is equal to RXCX
filter network time constant, a voltage ILX x DCR will drop
on CX to generate inductor current signal. According to
the Figure 4, the ISENxN is as follows :
Total current sense method is a patented topology, unlike
conventional current sense method requiring a NTC resistor
in per phase current loop for thermal compensation. The
RT8886A adopts the total current sense method requiring
only one NTC resistor for thermal compensation, and NTC
resistor cost can be saved by using this method. Figure 6
shows the total current sense method which connects
the resistor network between the IMON and VREF pins to
set a part of current loop gain for load-line (droop) setting
and set accurate over current protection.
VIMON  VREF = DCR  REQ  (IL1 + IL2 )
RCS
ISENxN =
ILX  DCR
RCSx
Where LX / DCR = RXCX is held. The method can get high
efficiency performance, but DCR value will be drifted by
temperature, a NTC resistor should add in the resistor
network in the IMON pin to achieve DCR thermal
compensation.
REQ includes a NTC resistor to compensate DCR thermal
drifting for high accuracy load-line (droop).
IL1
If 3 x ICCMAX x DCR is larger than 150mV, the current
sense method II is recommended to prevent current sense
amplifier from being saturated. According to Figure 5, the
RX is as follows : RX = RX1 // RX2
IMON
VCORE
LX
+
-
ISENxN
VCORE
LX
DCR
RX1
CX
RX2
ISENxP
RCSx
Figure 5. Lossless Current Sense Method II
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
RCS
ISEN1N
L
DCR
R
C
+
-
ISEN2P
ISEN2N
RCS
VREF
ISENxN
ISENxN
ISEN1P
RCSx
ILx
-
C
REQ
CX
Figure 4. Lossless Current Sense Method
+
R
IL2
ISEN2N
ISENxP
DCR
RNTC
DCR
RX
ISENxN
+
-
The resistance accuracy of RCSx is recommended to be
1% or higher.
ILx
ISEN1N
L
Figure 6. Total Current Sense Method
Load-Line (Droop) Setting
The G-NAVPTM topology can set load-line (droop) via the
current loop and the voltage loop, the load-line is a slope
between load current ICC and output voltage VCORE as
shown in Figure 7. Figure 8 shows the voltage control and
current loop. By using both loops, the load-line (droop)
can easily be set. The load-line set equation is :
1 DCR

 REQ
4 RCS
AI
RLL =
=
(m )
R2
AV
R1
The load-line can be set to zero by SET3 pin.
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23
RT8886A
C2
VCORE
C1
R2
Load line slope = -RLL
-
RLL x ICC
R1
+
VID
Figure 9. Type I Compensator
ICC
Figure 7. Load-Line (Droop)
VCORE
Multi-Function Pin Setting Mechanism
R2
Voltage Loop
TON Generator
-
R1
+
+
-
IL1.2
VID
1/4
-
L
+
DCR
R
C
ISEN1N + ISEN2N
ISEN[1:2]P
RNTC
+
RCS
IMON
-
VREF
ISEN[1:2]N
REQ
Figure 8. Voltage Loop and Current Loop
Compensator Design
The compensator of the RT8886A doesn't need a complex
type II or type III compensator to optimize control loop
performance. It can adopt a simple type I compensator
(one pole, one zero) in the G-NAVPTM topology to achieve
constant output impedance design for Intel VR12.5 and
VR12.6 ACLL specification. The one pole one zero
compensator is shown as Figure 9, the transfer function
of compensator should be designed as the following
transfer function to achieve constant output impedance,
i.e. Zo(s) = load-line slope in the entire frequency range :
s
1+
AI
  fsw
GCON (s) 

RLL 1 + s
For reducing total pin number of package, the SET[1:3]
pins adopt the multi-function pin setting mechanism in
the RT8886A. Figure 10 illustrates this operating
mechanism. The voltage at VREF pin will be pulled up to
3.2V after power ready (POR). First, external voltage
divider is to set the function1 and then internal current
source 80μA is to set the function2. The setting voltage of
function1 and function2 can be represented as follows :
R2
 3.2V
R1 + R2
R1 R2
VFUNCTION2 = 80 A 
R1 + R2
VFUNCTION1 =
All function setting will be done within 500μs after power
ready (POR), and the voltage at VREF pin will fix to 0.6V
after all function setting over.
If VFUNCTION1 and VFUNCTION2 are determined, R1 and R2
can be calculated as follows :
R1 =
3.2V  VFUNCTION2
80 A  VFUNCTION1
R2 =
R1 VFUNCTION1
3.2V  VFUNCTION1
In addition, Richtek provides a Microsoft Excel-based
spreadsheet to help design the SETx resistor network for
the RT8886A.
ESR
Where AI is current loop gain, RLL is load-line, fSW is
switching frequency and ωESR is a pole that should be
located at 1 / (COUT x ESR). Then, the C1 and C2 should
be designed as follows :
1
C1 =
R1   fSW
C2 =
COUT  ESR
R2
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is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Function 2 Function 1
<5:0>
<5:0>
Function 2 Function 1
<5:0>
<5:0>
80µA
ADC
ADC
VREF
Function 1
Register
R1
SET[1:3]
R3
R2
Function 2
Register
R2
Function 2
Register
80µA
ADC
Figure 11. Multi-Function Pin Setting Mechanism with a
R3 resistor to fine tune the set voltage of function 2
VREF
Function 1
Register
R1
SET[1:3]
R2
Function 2
Register
Figure 10. Multi-Function Pin Setting Mechanism
Connecting a R3 resistor from the SET[1:3] pin to the
middle node of voltage divider can help to fine tune the set
voltage of function 2, which does not affect the set voltage
of function 1. The Figure 11 shows the setting method
and the set voltage of function 1 and function 2 can be
represented as :
R2
VFUNCTION1 =
 3.2V
R1 + R2
R1 R2 

VFUNCTION2 = 80 A   R3 +

R1 + R2 

Function 2 Function 1
<5:0>
<5:0>
VREF
Function 1
Register
R1
SET[1:3]
Function 2 Function 1
<5:0>
<5:0>
80µA
Quick Response (QR) Mechanism
When the transient load step-up becomes quite large, it
is difficult for loop response to meet the energy transfer.
Hence, the output voltage generate undershoot to fail
specification. The RT8886A has Quick Response (QR)
mechanism being able to improve this issue. It adopts a
nonlinear control mechanism which can disable
interleaving function and simultaneously turn on all UGATE
one pulse at instantaneous step-up transient load to
restrain the output voltage drooping, Figure 12 shows the
QR behavior.
QR Width
VCORE
QR Threshold
80µA
PWM1
ADC
VREF
PWM2
Function 1
Register
R1
SET[1:3]
Function 2
Register
R3
R2
Load
Figure 12. Quick Response Mechanism
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RT8886A
The output voltage signal behavior needs to be detected
so that QR mechanism can be trigged. The output voltage
signal is via a remote sense line to connect at the VSEN
pin that is shown in Figure 13. The QR mechanism needs
to set QR width and QR threshold. Both definitions are
shown in Figure 10. A proper QR mechanism set can meet
different applications. The SET2 pin is a multi-function
pin which can set QR threshold, QR width and ICCMAX.
Current Mirror
QR trigger
VID
IMirror
VCC_SENSE
+
-
RQR VSEN
Figure 13. Simplified QR Trigger Schematic
An internal current source 80μA is used in multi-function
pin setting mechanism. For example, 20mV QR threshold
and 1.33 x TON QR width are set. According to Table 4,
the set voltage should be between 0.4504V and 0.4723V.
Please note that a high accuracy resistor is needed for
this setting accuracy, <1% error tolerance is
recommended.
In the Table 4, there are some “No Use” marks at
QRWIDTH section. It means that user should not use it
to avoid the possibility of shift digital code due to tolerance
concern.
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DS8886A-00 November 2013
RT8886A
Table 4. SET2 Pin Setting for QR Threshold and QR Width
VQR_SET = 80  A 
R1 R2
R1  R2
QR_TH
<2:0>
QR
Threshold
QR Width
(%TON)
Min
Typical
Max
unit
0.000
10.948
21.896
mV
QRWIDTH
<2:0>
000
25.024
35.973
46.921
mV
001
155%
50.049
75.073
100.098
125.122
60.997
86.022
111.046
136.070
71.945
96.970
121.994
147.019
mV
mV
mV
mV
010
011
100
101
133%
111%
89%
67%
150.147
175.171
200.196
225.220
250.244
161.095
186.119
211.144
236.168
261.193
172.043
197.067
222.092
247.116
272.141
mV
mV
mV
mV
mV
275.269
300.293
325.318
350.342
375.367
286.217
311.241
336.266
361.290
386.315
297.165
322.190
347.214
372.239
397.263
mV
mV
mV
mV
mV
400.391
425.415
450.440
475.464
411.339
436.364
461.388
486.413
422.287
447.312
472.336
497.361
mV
mV
mV
mV
500.489
525.513
550.538
575.562
600.587
511.437
536.461
561.486
586.510
611.535
522.385
547.410
572.434
597.458
622.483
mV
mV
mV
mV
mV
625.611
650.635
675.660
700.684
725.709
636.559
661.584
686.608
711.632
736.657
647.507
672.532
697.556
722.581
747.605
mV
mV
mV
mV
mV
750.733
775.758
800.782
825.806
761.681
786.706
811.730
836.755
772.630
797.654
822.678
847.703
mV
mV
mV
mV
110
111
000
001
44%
No Use
No Use
155%
850.831
875.855
900.880
925.904
950.929
861.779
886.804
911.828
936.852
961.877
872.727
897.752
922.776
947.801
972.825
mV
mV
mV
mV
mV
010
011
100
101
110
133%
111%
89%
67%
44%
975.953
986.901
997.849
mV
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
000
No Use
Disable
110
111
000
001
010
001
010
011
100
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
111
44%
No Use
No Use
155%
133%
15mV
20mV
25mV
30mV
111%
89%
67%
44%
No Use
No Use
155%
133%
111%
89%
67%
44%
No Use
No Use
155%
133%
111%
89%
67%
No Use
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
27
RT8886A
VQR_SET = 80  A 
R1 R2
R1  R2
QR
Threshold
QR Width
(%TON)
Typical
Max
unit
1000.978
1011.926
1022.874
mV
QRWIDTH
<2:0>
000
1026.002
1036.950
1047.898
mV
001
155%
1051.026
1076.051
1101.075
1126.100
1061.975
1086.999
1112.023
1137.048
1072.923
1097.947
1122.972
1147.996
mV
mV
mV
mV
010
011
100
101
133%
111%
89%
67%
1151.124
1176.149
1201.173
1226.197
1251.222
1162.072
1187.097
1212.121
1237.146
1262.170
1173.021
1198.045
1223.069
1248.094
1273.118
mV
mV
mV
mV
mV
1276.246
1301.271
1326.295
1351.320
1376.344
1287.195
1312.219
1337.243
1362.268
1387.292
1298.143
1323.167
1348.192
1373.216
1398.240
mV
mV
mV
mV
mV
1401.369
1426.393
1451.417
1476.442
1412.317
1437.341
1462.366
1487.390
1423.265
1448.289
1473.314
1498.338
mV
mV
mV
mV
1501.466
1526.491
1551.515
1576.540
1512.414
1537.439
1562.463
1587.488
1523.363
1548.387
1573.412
1598.436
mV
mV
mV
mV
Min
Dynamic VID (DVID) Compensation
When VID transition event occurs, a charge current will
be generated in the loop to cause that DVID performance
is deteriorated by this induced charge current, the
phenomenon is called droop effect. The droop effect is
shown in Figure 14. When VID up transition occurs, the
output capacitor will be charged by inductor current. Since
current signal is sensed in inductor, an induced charge
current will appear in control loop. The induced charge
current will produce a voltage drop in R1 to cause output
voltage to have a droop effect. Due to this, VID transition
performance will be deteriorated.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
28
QR_TH
<2:0>
101
No Use
35mV
110
111
000
001
010
110
111
011
100
101
110
111
000
001
010
011
100
101
110
111
44%
No Use
No Use
155%
133%
40mV
45mV
111%
89%
67%
44%
No Use
No Use
155%
133%
111%
89%
67%
44%
No Use
The RT8886A provides a DVID compensation function. A
virtual charge current signal can be established by the
SET1 pin to cancel the real induced charge current signal
and the virtual charge current signal is defined in Figure
16. Figure 15 shows the operation of cancelling droop
effect. A virtual charge current signal is established first
and then VID signal plus virtual charge current signal is
generated in FB pin. Hence, an induced charge current
signal flows to R1 and is cancelled to reduce droop effect.
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Charge current
L
VIN
Q1
CO1
Q2
Gate
Driver
CO2
RESR
CPU
Ai
Induced charge
current signal
C2
C1
R2
CCRCOT
COMP -
VIN
VID
Output voltage
R1
EA
+
+
tON
IDROOP
VID
VID Transition
Figure 14. Droop Effect in VID Transition
The RT8886A also provides a programmable DVID slew
rate function. The DVID slew rate can be set by SET3 pin.
Table 8 shows the DVID_Slew Rate setting in SET3 pin.
Charge current
For example, 13.2mV/μs is designed (Disable AntiOvershoot and zero load-line function). The DVID_Slew
Rate setting is set by external voltage divider. According
to Table 8, the DVID_Slew Rate set voltage should be
between 0.125V and 0.172V.
L
VIN
Q1
Gate
Driver
CO1
Q2
CO2
RESR
Ai
Induced charge
current signal
Table 5 and Table 6 show the DVID_Threshold and
DVID_Width settings in SET1 pin. For example, 25mV
DVID_Threshold and 72μs DVID_Width are designed (OCP
sets as 100% ICCMAX, and RSET sets as 100% Ramp
current). The DVID_Threshold is set by an external voltage
divider to set and the DVID_Width is set by an internal
current source 80μA by the multi-function pin setting
mechanism. According to the Table 5 and Table 6, the
DVID_Threshold set voltage should be between 0.225V
and 0.247V and the DVID_Width set voltage should be
between 0.125V and 0.147V. Please note that a high
accuracy resistor is needed for this setting, <1% error
tolerance is recommended.
Output voltage
CPU
C2
R2
C1
CCRCOT
COMP -
VIN
VID
+
tON
IDROOP
R1
EA
+
Virtual Charge Current
+
DVID Event
Slew Rate
Control
VID
Virtual Charge
Current
Generator
VID
Transition
SET1
Figure 15. DVID Compensation
DVID_Width
DVID_Threshold
Figure 16. Definition of Virtual Charge Current Signal
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
29
RT8886A
0.000
25.024
50.049
75.073
100.098
Table 5. SET1 Pin Setting for DVID_Threshold
R1 R2
VDVID_Threshold = 80 A 
R1 R2
DVID_Threshold
DVID_TH
OCS
Typical
Max
unit
<2:0>
<2:0>
10.948
21.896
mV
000
35.973
46.921
mV
001
60.997
71.945
mV
010
86.022
96.970
mV
011
000
85mV
111.046
121.994
mV
100
125.122
150.147
175.171
200.196
225.220
250.244
275.269
300.293
325.318
350.342
375.367
400.391
425.415
450.440
136.070
161.095
186.119
211.144
236.168
261.193
286.217
311.241
336.266
361.290
386.315
411.339
436.364
461.388
147.019
172.043
197.067
222.092
247.116
272.141
297.165
322.190
347.214
372.239
397.263
422.287
447.312
472.336
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
475.464
500.489
486.413
511.437
497.361
522.385
mV
mV
525.513
550.538
575.562
600.587
625.611
650.635
675.660
700.684
725.709
750.733
775.758
800.782
825.806
850.831
536.461
561.486
586.510
611.535
636.559
661.584
686.608
711.632
736.657
761.681
786.706
811.730
836.755
861.779
547.410
572.434
597.458
622.483
647.507
672.532
697.556
722.581
747.605
772.630
797.654
822.678
847.703
872.727
875.855
900.880
886.804
911.828
925.904
950.929
975.953
936.852
961.877
986.901
Min
No Use
100%
110%
120%
130%
001
101
110
111
000
001
010
011
100
101
110
111
000
001
010
75mV
140%
150%
No Use
No Use
100%
110%
120%
130%
140%
150%
No Use
No Use
100%
110%
010
011
100
65mV
120%
130%
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
011
101
110
111
000
001
010
011
100
101
110
111
000
001
010
55mV
140%
150%
No Use
No Use
100%
110%
120%
130%
140%
150%
No Use
No Use
100%
110%
897.752
922.776
mV
mV
100
011
100
45mV
120%
130%
947.801
972.825
997.849
mV
mV
mV
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
30
OCP = %ICCMAX
101
110
111
140%
150%
No Use
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Min
Typical
Max
1000.978
1026.002
1051.026
1076.051
1101.075
1011.926
1036.950
1061.975
1086.999
1112.023
1022.874
1047.898
1072.923
1097.947
1122.972
R1 R2
R1 R2
DVID_TH
unit
<2:0>
mV
mV
mV
mV
101
mV
1126.100
1151.124
1176.149
1201.173
1226.197
1251.222
1276.246
1301.271
1326.295
1351.320
1376.344
1401.369
1426.393
1451.417
1137.048
1162.072
1187.097
1212.121
1237.146
1262.170
1287.195
1312.219
1337.243
1362.268
1387.292
1412.317
1437.341
1462.366
1147.996
1173.021
1198.045
1223.069
1248.094
1273.118
1298.143
1323.167
1348.192
1373.216
1398.240
1423.265
1448.289
1473.314
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
1476.442
1501.466
1487.390
1512.414
1498.338
1523.363
mV
mV
1526.491
1551.515
1576.540
1537.439
1562.463
1587.488
1548.387
1573.412
1598.436
mV
mV
mV
VDVID_Threshold = 80 A 
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
OCS
<2:0>
000
001
010
011
100
DVID_Threshold OCP = %ICCMAX
35mV
No Use
100%
110%
120%
130%
110
101
110
111
000
001
010
011
100
101
110
111
000
001
010
25mV
140%
150%
No Use
No Use
100%
110%
120%
130%
140%
150%
No Use
No Use
100%
110%
111
011
100
15mV
120%
130%
101
110
111
140%
150%
No Use
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
31
RT8886A
VDVID_Width
Table 6. SET1 Pin Setting for DVID_Width
R2
=
 3.2V
R1  R2
RSET % 543k RTON
RSET
DVID_WTH
unit
<3:0>
<1:0>
mV
00
mV
01
0000
83%
mV
10
Min
Typical
Max
0.000
25.024
50.049
10.948
35.973
60.997
21.896
46.921
71.945
75.073
100.098
125.122
150.147
86.022
111.046
136.070
161.095
96.970
121.994
147.019
172.043
mV
mV
mV
mV
175.171
200.196
225.220
250.244
275.269
186.119
211.144
236.168
261.193
286.217
197.067
222.092
247.116
272.141
297.165
mV
mV
mV
mV
mV
300.293
325.318
350.342
375.367
400.391
311.241
336.266
361.290
386.315
411.339
322.190
347.214
372.239
397.263
422.287
mV
mV
mV
mV
mV
425.415
450.440
475.464
500.489
436.364
461.388
486.413
511.437
447.312
472.336
497.361
522.385
mV
mV
mV
mV
525.513
550.538
575.562
600.587
625.611
536.461
561.486
586.510
611.535
636.559
547.410
572.434
597.458
622.483
647.507
mV
mV
mV
mV
mV
650.635
675.660
700.684
725.709
750.733
661.584
686.608
711.632
736.657
761.681
672.532
697.556
722.581
747.605
772.630
mV
mV
mV
mV
mV
775.758
800.782
825.806
850.831
786.706
811.730
836.755
861.779
797.654
822.678
847.703
872.727
mV
mV
mV
mV
875.855
900.880
925.904
950.929
975.953
886.804
911.828
936.852
961.877
986.901
897.752
922.776
947.801
972.825
997.849
mV
mV
mV
mV
mV
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
32
0001
0010
0011
0100
0101
0110
0111
1000
1001
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
100%
117%
133%
150%
167%
183%
200%
217%
233%
DVID_Width
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
VDVID_Width =
R2
 3.2V
R1  R2
RSET
unit
<3:0>
mV
mV
1010
mV
Min
Typical
Max
1000.978
1026.002
1051.026
1011.926
1036.950
1061.975
1022.874
1047.898
1072.923
1076.051
1101.075
1126.100
1151.124
1086.999
1112.023
1137.048
1162.072
1097.947
1122.972
1147.996
1173.021
mV
mV
mV
mV
1176.149
1201.173
1226.197
1251.222
1276.246
1187.097
1212.121
1237.146
1262.170
1287.195
1198.045
1223.069
1248.094
1273.118
1298.143
mV
mV
mV
mV
mV
1301.271
1326.295
1351.320
1376.344
1401.369
1312.219
1337.243
1362.268
1387.292
1412.317
1323.167
1348.192
1373.216
1398.240
1423.265
mV
mV
mV
mV
mV
1426.393
1451.417
1476.442
1501.466
1437.341
1462.366
1487.390
1512.414
1448.289
1473.314
1498.338
1523.363
mV
mV
mV
mV
1526.491
1551.515
1576.540
1537.439
1562.463
1587.488
1548.387
1573.412
1598.436
mV
mV
mV
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
1011
1100
1101
1110
1111
DVID_WTH
<1:0>
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
RSET % 543k RTON
250%
267%
283%
300%
317%
333%
DVID_Width
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
33
RT8886A
Ramp Compensation
Current Monitor, IMON
The G-NAVPTM topology is one type of ripple based control
that has fast transient response, no beat frequency issue
in high repetitive load frequency operation and low BOM
cost. Hence, ripple based control usually has no good
noise immunity. The RT8886A provides a ramp
compensation to increase noise immunity and reduce jitter
at the switching node. Figure 17 shows the ramp
compensation.
The RT8886A includes a current monitor (IMON) function
which can be used to detect over current protection and
the maximum processor current ICCMAX, and also sets
a part of current gain in the load-line setting. It produces
an analog voltage proportional to output current between
the IMON pin and VREF pins.
Noise Margin
w/o ramp compensation
IMON-VREF
VCOMP
The calculation for IMON-VREF voltage is shown as
below :
DCR
VIMON  VREF =
 REQ  IL1 + IL2 
RCS
Where IL1 + IL2 are output current and for the definitions of
DCR, RCS and REQ, can refer to Figure 7.
Maximum Processor Current Setting, ICCMAX
Noise Margin
w/ ramp compensation
IMON-VREF
VCOMP
The maximum processor current ICCMAX can be set by
the SET2 pin. ICCMAX register is set by an external voltage
divider by the multi-function mechanism. The Table 7
shows the ICCMAX setting in the SET2 pin. For example,
ICCMAX = 32A, the VICCMAX needs to be set as 0.203
typically. Additionally, VIMON − VREF needs to be set as
1.6V when IL1 + IL2 = 32A. The ICCMAX alert signal will be
pulled to low level if VIMON − VREF = 1.6V.
Figure 17. Ramp Compensation
For the RT8886A, the ramp compensation also needs to
be considered during mode transition from PS0/1 to PS2.
For achieving smooth mode transition into PS2, a proper
ramp compensation design is necessary. Since the ramp
compensation needs to be proportional to the on-time, in
others words, the ramp compensation is dependent on
RTON design. The Table 6 shows the relationship between
R TON and ramp compensation. For example, when
designed RTON is 271kΩ, the RAMP is set as
543k
 100% .
271k
The ramp compensation can be selected for VR12.5 or
VR12.6 application at PS1 by SET3 pin. For VR12.5
application, the ramp compensation value is 1/3 of VR12.6
application at PS1.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
34
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Table 7. SET2 Pin Setting for ICCMAX
Min
0.000
R2
 3.2V
R1  R2
Typical
Max
Unit
3.128
6.256
mV
0
A
12.512
25.024
37.537
15.640
28.152
40.665
18.768
31.281
43.793
mV
mV
mV
2
4
6
A
A
A
50.049
62.561
75.073
87.586
100.098
112.610
125.122
137.634
150.147
162.659
175.171
187.683
200.196
212.708
53.177
65.689
78.201
90.714
103.226
115.738
128.250
140.762
153.275
165.787
178.299
190.811
203.324
215.836
56.305
68.817
81.329
93.842
106.354
118.866
131.378
143.891
156.403
168.915
181.427
193.939
206.452
218.964
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
8
10
12
14
16
18
20
22
24
26
28
30
32
34
A
A
A
A
A
A
A
A
A
A
A
A
A
A
225.220 228.348 231.476
237.732 240.860 243.988
mV
mV
36
38
A
A
250.244
262.757
275.269
287.781
300.293
312.805
325.318
337.830
350.342
362.854
375.367
387.879
400.391
412.903
253.372
265.885
278.397
290.909
303.421
315.934
328.446
340.958
353.470
365.982
378.495
391.007
403.519
416.031
256.500
269.013
281.525
294.037
306.549
319.062
331.574
344.086
356.598
369.110
381.623
394.135
406.647
419.159
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
40
42
44
46
48
50
52
54
56
58
60
62
64
66
A
A
A
A
A
A
A
A
A
A
A
A
A
A
425.415
437.928
450.440
462.952
475.464
487.977
500.489
428.543
441.056
453.568
466.080
478.592
491.105
503.617
431.672
444.184
456.696
469.208
481.720
494.233
506.745
mV
mV
mV
mV
mV
mV
mV
68
70
72
74
76
78
80
A
A
A
A
A
A
A
VICCMAX =
ICCMAX
Unit
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
Min
513.001
R2
 3.2V
ICCMAX Unit
R1  R2
Typical
Max
Unit
516.129 519.257 mV
82
A
525.513
538.025
528.641
541.153
531.769
544.282
mV
mV
84
86
A
A
550.538
563.050
575.562
588.074
600.587
613.099
625.611
638.123
650.635
663.148
675.660
688.172
700.684
713.196
553.666
566.178
578.690
591.202
603.715
616.227
628.739
641.251
653.763
666.276
678.788
691.300
703.812
716.325
556.794
569.306
581.818
594.330
606.843
619.355
631.867
644.379
656.891
669.404
681.916
694.428
706.940
719.453
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
88
90
92
94
96
98
100
102
104
106
108
110
112
114
A
A
A
A
A
A
A
A
A
A
A
A
A
A
725.709
738.221
750.733
763.245
775.758
788.270
800.782
813.294
825.806
838.319
850.831
863.343
875.855
888.368
900.880
913.392
728.837
741.349
753.861
766.373
778.886
791.398
803.910
816.422
828.935
841.447
853.959
866.471
878.983
891.496
904.008
916.520
731.965
744.477
756.989
769.501
782.014
794.526
807.038
819.550
832.063
844.575
857.087
869.599
882.111
894.624
907.136
919.648
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
925.904
938.416
950.929
963.441
975.953
988.465
1000.978
1013.490
929.032
941.544
954.057
966.569
979.081
991.593
1004.106
1016.618
932.160
944.673
957.185
969.697
982.209
994.721
1007.234
1019.746
mV
mV
mV
mV
mV
mV
mV
mV
148
150
152
154
156
158
160
162
A
A
A
A
A
A
A
A
VICCMAX =
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
35
RT8886A
R2
 3.2V
ICCMAX Unit
R1 R2
Min
Typical
Max
Unit
1026.002 1029.13 1032.258 mV
164
A
R2
 3.2V
ICCMAX Unit
R1  R2
Min
Typical
Max
Unit
1313.783 1316.911 1320.039 mV
210
A
1038.514 1041.642 1044.770 mV
1051.026 1054.154 1057.283 mV
1063.539 1066.667 1069.795 mV
166
168
170
A
A
A
1076.051
1088.563
1101.075
1113.587
1126.100
1138.612
1151.124
1163.636
1176.149
1188.661
1201.173
1213.685
1226.197
1238.710
1251.222
1263.734
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1326.295
1338.807
1351.320
1363.832
1376.344
1388.856
1401.369
1329.423
1341.935
1354.448
1366.960
1379.472
1391.984
1404.497
1332.551
1345.064
1357.576
1370.088
1382.600
1395.112
1407.625
mV
mV
mV
mV
mV
mV
mV
212
214
216
218
220
222
224
A
A
A
A
A
A
A
1413.881
1426.393
1438.905
1451.417
1463.930
1417.009
1429.521
1442.033
1454.545
1467.058
1420.137
1432.649
1445.161
1457.674
1470.186
mV
mV
mV
mV
mV
226
228
230
232
234
A
A
A
A
A
1476.442
1488.954
1501.466
1513.978
1526.491
1539.003
1551.515
1479.570
1492.082
1504.594
1517.107
1529.619
1542.131
1554.643
1482.698
1495.210
1507.722
1520.235
1532.747
1545.259
1557.771
mV
mV
mV
mV
mV
mV
mV
236
238
240
242
244
246
248
A
A
A
A
A
A
A
1276.246 1279.374 1282.502 mV
1288.759 1291.887 1295.015 mV
204
206
A
A
1301.271 1304.399 1307.527 mV
208
A
1564.027 1567.155 1570.283 mV
1576.540 1579.668 1582.796 mV
1589.052 1592.180 1595.308 mV
250
252
254
A
A
A
VICCMAX =
1079.179
1091.691
1104.203
1116.716
1129.228
1141.740
1154.252
1166.764
1179.277
1191.789
1204.301
1216.813
1229.326
1241.838
1254.350
1266.862
1082.307
1094.819
1107.331
1119.844
1132.356
1144.868
1157.380
1169.892
1182.405
1194.917
1207.429
1219.941
1232.454
1244.966
1257.478
1269.990
VICCMAX =
Anti-Overshoot Function
When DVID slew rate increases or the transient load stepdown become quite large, loop response is difficult to meet
energy transfer so that output voltage generates overshoot
to fail specification. The RT8886A has Anti-Overshoot
function being able to help improve this issue. The VR
will turn off all low side MOSFETs when output voltage
ramps up to the target VID (ALERT signal be pulled low)
or when output voltage overshoot is quite large. This
function can be enabled/disabled by SET3 pin, and
enabled when DVID slew rate is set beyond 26.4mV/μs.
The RT8886A also has Anti-Overshoot enhancement
function to improve the transient performance. When this
function is enable, the UG signal will be masked when
Anti-Overshoot is triggered to reduce the overshoot during
the transient load step-down.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
36
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Table 8. SET3 Pin Setting for DVID Slew Rate
VDVID_Slew Rate =
R1
 3.2V
R1  R2
Max
Anti-Overshoot
Min
Typical
25.024
125.122
225.220
325.318
35.973
136.070
236.168
336.266
46.921
147.019
247.116
347.214
mV
mV
mV
mV
425.415
525.513
625.611
436.364
536.461
636.559
447.312
547.410
647.507
mV
mV
mV
725.709
825.806
925.904
1026.002
736.657
836.755
936.852
1036.950
747.605
847.703
947.801
1047.898
mV
mV
mV
mV
1126.100
1226.197
1326.295
1137.048
1237.146
1337.243
1147.996
1248.094
1348.192
mV
mV
mV
1426.393
1526.491
1437.341
1537.439
1448.289
1548.387
mV
mV
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
Zero Load Line
DVID_Slew Rate
Disable
13.2mV/s
26.4mV/s
39.6mV/s
52.8mV/s
unit
Disable
Enable
Disable
Enable
Enable
13.2mV/s
26.4mV/s
39.6mV/s
52.8mV/s
13.2mV/s
26.4mV/s
39.6mV/s
52.8mV/s
13.2mV/s
26.4mV/s
39.6mV/s
52.8mV/s
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
37
RT8886A
Table 9. SET3 Pin Setting for ZCD_Threshold
R1 R2
R1 R2
Max
VZCD_Threshold = 80  A 
Min
Typical
unit
0.000
50.049
100.098
150.147
10.948
60.997
111.046
161.095
21.896
71.945
121.994
172.043
mV
mV
mV
mV
200.196
250.244
300.293
350.342
211.144
261.193
311.241
361.290
222.092
272.141
322.190
372.239
mV
mV
mV
mV
400.391
450.440
500.489
550.538
411.339
461.388
511.437
561.486
422.287
472.336
522.385
572.434
mV
mV
mV
mV
600.587
650.635
700.684
750.733
611.535
661.584
711.632
761.681
622.483
672.532
722.581
772.630
mV
mV
mV
mV
800.782
850.831
900.880
950.929
811.730
861.779
911.828
961.877
822.678
872.727
922.776
972.825
mV
mV
mV
mV
1000.978
1051.026
1101.075
1011.926
1061.975
1112.023
1022.874
1072.923
1122.972
mV
mV
mV
1151.124
1201.173
1251.222
1301.271
1162.072
1212.121
1262.170
1312.219
1173.021
1223.069
1273.118
1323.167
mV
mV
mV
mV
1351.320
1401.369
1451.417
1501.466
1362.268
1412.317
1462.366
1512.414
1373.216
1423.265
1473.314
1523.363
mV
mV
mV
mV
1551.515
1562.463
1573.412
mV
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
38
RSET
Application
Anti-Overshoot
Enhancement
Disable
VR12.6
Enable
Disable
ZCD_TH
0.75mV
1.5mV
2.25mV
3mV
3.75mV
4.5mV
5.25mV
6mV
0.75mV
1.5mV
2.25mV
3mV
3.75mV
4.5mV
5.25mV
6mV
0.75mV
1.5mV
2.25mV
3mV
3.75mV
4.5mV
5.25mV
6mV
0.75mV
1.5mV
2.25mV
VR12.5
Enable
3mV
3.75mV
4.5mV
5.25mV
6mV
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Over-Current Protection
Under-Voltage Lockout (UVLO)
RT8886A provides Over-Current Protection (OCP) which
is set by SET1 pin. The OCP threshold setting can refer
to ICCMAX current in Table 7. For example, if ICCMAX is
set as 32A, users can set voltage by using the external
voltage divider in the SET1 pin as 0.486V typically if
DVID_Threshold = 35mV, then 38.4A OCP (120% x
ICCMAX) threshold will be set. When output current is
higher than the OCP threshold, OCP is latched with a
40μs delay time to prevent false trigger. Besides, the OCP
function is masked when dynamic VID transient occurs.
After dynamic VID transition, OCP is masked for 80μs.
During normal operation, if the voltage at the VCC pin
drops below POR threshold 4.1V (min), the VR will trigger
UVLO. The UVLO protection forces all high-side
MOSFETs and low-side MOSFETs off by shutting down
internal PWM logic drivers.
Output Over-Voltage Protection
An OVP condition is detected when the VSEN pin is
350mV more than VID. When OVP is detected, the upper
gate voltage UGATEx is pulled-low and the lower gate
voltage LGATEx is pulled high, OVP is latched with a
0.5μs delay time to prevent false trigger.
Negative Voltage Protection
Since the OVP latch continuously turns on all low-side
MOSFETs of the VR, the VR will suffer negative output
voltage. When the VSEN detects a voltage below −0.05V
after triggering OVP, the VR will trigger NVP to turn off all
low-side MOSFETs of the VR while the high-side
MOSFETs remains off. After triggering NVP, if the output
voltage rises above 0V, the OVP latch will restart to turn
on all low-side MOSFETs. Therefore, the output voltage
may bounce between 0V and −0.05V due to OVP latch
and NVP triggering. The NVP function will be active only
after OVP is triggered.
Power Ready (POR) Detection
During start-up, the RT8886A will detect the voltage at
the voltage input pins : VCC ,EN and PVCC. When VCC >
4.1V and PVCC > 4V, the RT8886A will recognize the
power state of system to be ready (POR = high) and wait
for enable command at the EN pin. After POR = high and
VEN > 0.7V, the RT8886A will enter start-up sequence. If
the voltage at any voltage pin drops below low threshold
(POR = low), the RT8886A will enter power down sequence
and all functions will be disabled. Normally, connecting
system voltage V TT (1.05V) to the EN pin is
recommended.1ms (max) after the chip has been enabled,
the SVID circuitry will be ready. All protection latches (OVP,
OCP, UVP) will be cleared only by VCC. The condition of
VEN = low will not clear these latches. Figure 18 and Figure
19 show the POR detection and the timing chart for POR
process, respectively.
5V
VCC
4.1V
PVCC
CP
-
POR
DRIVER
Chip EN
VTT
1.05V
EN
+
0.7V
CP
-
Figure 18. POR Detection
Under-Voltage Protection
When the VSEN pin voltage is 350mV less than VID, a
UVP will be latched. When UVP latched, both the UGATEx
and LGATEx will be pulled-low. A 3μs delay is used in
UVP detection circuit to prevent false trigger. Besides,
the UVP function is masked when dynamic VID transient
occurs. After dynamic VID transition, UVP is masked for
80μs.
+
VCC
PVCC
POR
EN
1ms
SVID Invalid
Valid
Invalid
Figure 19. Timing Chart for POR Process
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
39
RT8886A
Precise Reference Current Generation, IBIAS
Analog circuits need very precise reference voltage/current
to drive/set these analog devices. The RT8886A provides
a 2V voltage source at the IBIAS pin, and a 100kΩ resistor
is required to be connected between the IBIAS pin and
analog ground to generate a very precise reference current.
Through this connection, the RT8886A will generate a
20μA current from the IBIAS pin to analog ground, and
this 20μA current will be mirrored inside the RT8886A for
internal use. The IBIAS pin can only be connected with a
100kΩ resistor to GND for internal analog circuit use. The
resistance accuracy of this resistor is recommended to
be 1% or higher. Figure 20 shows the IBIAS setting circuit.
Current Mirror
2V
+
20µA
-
IBIAS
100k
VDDIO
VR_HOT
VCC
R1
+
NTC
TSEN
-
R2
1.887V
Figure 21. VR_HOT Circuit
Differential Remote Sense Setting
The VR provides differential remote-sense inputs to
eliminate the effects of voltage drops along the PC board
traces, CPU internal power routes and socket contacts.
The CPU contains on-die sense pins, VCC_SENSE and
VSS_SENSE. Connecting RGND to VSS_SENSE and connect
FB to VCC_SENSE with a resistor to build the negative input
path of the error amplifier. The VDAC and the precision
voltage reference are referred to RGND for accurate remote
sensing.
Figure 20. IBIAS Setting Circuit
CPU VCC_SENSE
VOUT
The VR_HOT signal is an open-drain signal which is used
for VR thermal protection. When the sensed voltage in
the TSEN pin exceeds 1.887V, the VR_HOT signal will
be pulled low to notify CPU that the thermal protection
needs to work. According to Intel VR definition, VR_HOT
signal needs acting if VR power chain temperature
exceeds 100°C. Placing an NTC thermistor at the hottest
area in the VR power chain and its connection is shown
in Figure 21, to design the voltage divider elements (R1,
R2 and NTC) so that VTSEN = 1.887V at 100°C. The
resistance accuracy of TSEN network is recommended to
be 1% or higher.
VTSEN = VCC 
R2
R2 + R1//RNTC(100C) 
= 1.887V
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
40
EA
+
VID
R1
FB
COUT
+
TSEN and VR_HOT
R2
RGND
CPU VSS_SENSE
Figure 22. Remote Sensing Circuit
Phase Disable (Before POR)
The number of active phases is determined by the internal
circuitry that monitors the ISENxN voltages during startup. Normally, the VR operates as a 2-phase PWM
controller. Pulling ISEN2N to VCC programs a 1-phase
operation. Before POR, VR detects whether the voltages
of ISEN2N are higher than “VCC − 1V” respectively to
decide how many phases should be active. Phase
selection is only active during POR. When POR = high,
the number of active phases is determined and latched.
The unused ISENxP pins are recommended to be
connected to VCC and unused PWM pins can be left
floating.
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Current Loop Design in Details
IL1
VREF
REQ
RNTC
IMON ISEN1N
+
-
VCORE
L1
DCR1
R1
C1
ISEN1P
ISEN1N
680
IL2
COMP
1/4
L2
DCR2
-
R2
C2
+
0.6V
+
ISEN2N
+
+
-
ISEN2P
ISEN2N
680
Figure 23. Current Loop Structure
Figure 23 shows the whole current loop structure. The
current loop plays an important role in RT8886A that can
decide ACLL performance, DCLL accuracy and ICCMAX
accuracy. For ACLL performance, the correct compensator
design is assumed, if RC network time constant matches
inductor time constant LX / DCRX, an expected load
transient waveform can be designed. If RXCX network time
constant is larger than inductor time constant LX / DCRX,
VCORE waveform has a sluggish droop during load transient.
If RXCX network is smaller than inductor time constant
LX / DCRX, a worst VCORE waveform will sag to create an
undershoot to fail the specification. Figure 24 shows the
variety of RXCX constant corresponding to the output
waveforms.
R x  Cx =
VCORE
Lx
DCR x
IOUT x RLL
IOUT
IOUT
Expected load transient waveform
R x  Cx <
VCORE
Lx
DCR x
IOUT x RLL
IOUT
IOUT
Undershoot created in VCORE
VCORE
R x  Cx >
Lx
DCR x
IOUT x RLL
IOUT
IOUT
Sluggish droop
Figure 24. All Kind of RXCX Constants
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
41
RT8886A
For DCLL performance and ICCMAX accuracy, since the
copper wire of inductor has a positive temperature
coefficient, when temperature goes high in the heavy load
condition then DCR value goes large simultaneously. A
resistor network with NTC thermistor compensation
connecting between the IMON and REF pins is necessary
to compensate the positive temperature coefficient of
inductor DCR. The design flow is as follows:
Where :
α TH =
K TH  K TR
R NTCTH  R NTCTR
α TL =
K TL  K TR
RNTCTL  RNTCTR
KR3 =
(α TH / α TL )RNTCTH  RNTCTL
1  (α TH / α TL )
K TL =
1.6
GCS(TL)  ICC-MAX
Step2 : Three equations can be listed as
K TR =
DCR (TL ) 4
  iLi  REQ (TL ) = 1.6
680
i=1
1.6
GCS(TR)  ICC-MAX
K TH =
1.6
GCS(TH)  ICC-MAX
Step1 : Given the three system temperature TL, TR and
TH, at which are compensated.
DCR (TR ) 4
  iLi  REQ (TR ) = 1.6
680
i=1
Design Step :
DCR (TH ) 4
  iLi  REQ (TH ) = 1.6
680
i=1
Where :
(1) The relationship between DCR and temperature is as
follows :
DCR (T) = DCR (25C)  1+ 0.00393 (T - 25)
(2) REQ(T) is the equivalent resistor of the resistor network
with a NTC thermistor


REQ (T) = RIMON1 + RIMON2 / / RIMON3 + RNTC (T)
And the relationship between NTC and temperature is as
follows :
RNTC (T) = RNTC
1
1
β(
)

(25C)  e T+273 298
β is in the NTC thermistor datasheet.
Step3 : Three equations and three unknowns, RIMON1,
RIMON2 and RIMON3 can be found out unique solution.
RIMON1 = K TR 
RIMON2 =
2
[KR3
RIMON2  (RNTCTR +RIMON3 )
RIMON2 +RNTCTR +RIMON3
+KR3 (RNTCTL +RNTCTR )
+RNTCTLRNTCTR ]α TL
RIMON3 = -RIMON2 +KR3
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42
The RT8886A Excel based design tool is available. Users
can contact your Richtek representative to get the
spreadsheet. Three main design procedures for RT8886A
design, first step is initial settings, second step is loop
design and the last step is protection settings. The
following design example is to explain the RT8886A design
procedure :
Input Voltage
No. of Phases
VBoot
VCORE Specification
19V
2
1.7V
VDAC(MAX)
1.8V
ICCMAX
ICC-DY
40A
32A
ICC-TDC
Load Line
Fast Slew Rate
Max Switching
Frequency
16A
2m
52.8mV/s
600kHz
In Shark Bay VRTB Guideline, the output filter
requirements of VRTB specification for desktop platform
are as follows :
Output Inductor : 220nH/0.875mΩ
Output Ceramic Capacitor : 22μF/0805 (23pcs max sites
on top side)
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DS8886A-00 November 2013
RT8886A
(1)Initial Settings :

R2  3.2V
R1  R2
1.562 = 80A  R1 R2
R1  R2
(2)Loop Design :
R1 = 84.87kΩ, R2 = 25.37kΩ.
RT8886A initial voltage is 1.7V

IBIAS needs to connect a 100kΩ resistor to ground.

On time setting : Using the specification, TON is
VDAC(MAX)
1
tON =

= 158n(s)
fSW(MAX)
VIN
0.737 


The on time setting resistor RTON = 270kΩ

Current sensor adopts lossless RC filter to sense current
signal in DCR. For getting an expected load transient
waveform, RxCx time constant needs to match LX/DCRX
per phase. Cx = 1μF is set, then
LX
RX =
= 240
1F  DCR X

IMON resistor network design : TL = 25°C, TR = 50°C
and TH = 100°C are decided, NTC thermistor = 100kΩ
@25°C, β = 4485 and ICCMAX = 40A. According to the
sub-section “Current Loop Design in Details”, RIMON1
= 16.24kΩ, RIMON2 = 17.2kΩ and RIMON3 = 9.34kΩ can
be decided. The REQ (25°C) = 31.1kΩ.


1 DCR

 REQ
A V 4 RCS
=
=
(m)
R2
AI
R1
Where DCR (25°C) = 0.875mΩ, RCS = 680Ω and REQ
(25°C) = 31.1kΩ. Hence the AV = R2 / R1 = 5 can be
obtained. R1 = 10kΩ usually is decided, so R2 = 50kΩ.
SET1 resistor network design : First the DVID
compensation parameters need to be decided. The
DVID_TH can be calculated as the following equation :
DVID
VDVID_TH = LL  COUT 
dt
Where LL is load-line, COUT is total output capacitance
and DVID/dt is DVID fast slew rate. Thus VDVID_TH = 15mV
is needed in this case. And DVID_Width is chosen as
72μs typically. Next, OCP threshold is designed as 1.5 x
ICCMAX. Last, RAMP = 543kΩ / RTON = 200%, 200% is
set. By using above information, the two equations can
be listed by using multi-function pin setting mechanism
DS8886A-00 November 2013
SET3 resistor network design : first, the DVID_Slew Rate
needs to be selected. Assume 52.8mV/μs is selected.
The zero load line is disabled and enable Anti-Overshoot
function and Anti-Overshoot enhancement. The ZCD
threshold is chosen as 3.75mV typically and RSET
application is set to VR12.6. By using above information,
the two equations can be listed by using multi-function
pin setting mechanism :
R2
1.137 =
 3.2V
R1 R2
 R1 R2 
0.611 = 80A  

 R1 R2 
R1 = 20.15k, R2 = 11.85k
(3) Protection Settings :

OVP/UVP protections : When the VSEN pin voltage is
350mV higher than VID, the OVP will be latched. When
the VSEN pin voltage is 350mV lower than VID, the
UVP will be latched.

TSEN and VR_HOT design : Using the following equation
to calculate related resistances for VR_HOT setting.
R2
VTSEN = VCC 
= 1.887V
R2 + RNTC(100C) // R1

Copyright © 2013 Richtek Technology Corporation. All rights reserved.
SET2 resistor network design : the QR mechanism
parameters need to be designed first. Initial QR_TH is
designed as 45mV and QR_Width is designed as 0.67
x TON. The ICCMAX is designed as 40A. By using the
information, the two equations can be listed by using
multi-function pin setting mechanism
R2
0.253 =
 3.2V
R1 R2
 R1 R2 
1.537 = 80A  

 R1 R2 
R1 = 242.7kΩ, R2 = 20.82kΩ.
Load-line design : 2mΩ droop is required, because REQ
(25°C) is decided, the voltage loop Av gain is also
decided by the following equation :
RLL

Choosing R1 = 100kΩ and an NTC thermistor RNTC (25°C)
= 100kΩ and its β = 4485. When temperature is 100°C,
the RNTC(100°C) = 4.85kΩ.Then R2 = 2.8kΩ can be
calculated.
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RT8886A
Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PCB layout is critical to achieve low switching losses and
stable operation. The switching power stage requires
particular attention. If possible, mount all of the power
components on the top side of the board with their ground
terminals flushed against one another. Follow these
guidelines for the optimum PCB layout :

Keep the high current paths short, especially at the
ground terminals.

Keep the power traces and load connections short. This
is essential for high efficiency.

When trade-offs in trace lengths must be made, it's
preferable to let the inductor charging path be longer
than the discharging path.

Place the current sense component close to the
controller. ISENxP and ISENxN connections for current
limit and voltage positioning must be made using Kelvin
sense connections to guarantee current sense accuracy.
The PCB trace from the sense nodes should be
paralleled back to the controller.

Route high speed switching nodes away from sensitive
analog areas (COMP, FB, ISENxP, ISENxN, etc...)

Connect the exposed pad to the ground plane through
low impedance path. Recommend use of at least 5 vias
to connect to ground planes in PCB internal layers.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-32L 4x4 package, the thermal resistance, θJA, is
27.8°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (27.8°C/W) = 3.59W for
WQFN-32L 4x4 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 25 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
4.2
Four-Layer PCB
3.6
3.0
2.4
1.8
1.2
0.6
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 25. Derating Curve of Maximum Power
Dissipation
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44
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
RT8886A
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
3.900
4.100
0.154
0.161
D2
2.650
2.750
0.104
0.108
E
3.900
4.100
0.154
0.161
E2
2.650
2.750
0.104
0.108
e
L
0.400
0.300
0.016
0.400
0.012
0.016
W-Type 32L QFN 4x4 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS8886A-00 November 2013
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