TC4420/TC4429 6A High-Speed MOSFET Drivers Features General Description • Latch-Up Protected: Will Withstand >1.5A Reverse Output Current • Logic Input Will Withstand Negative Swing Up To 5V • ESD Protected: 4 kV • Matched Rise and Fall Times: - 25 ns (2500 pF load) • High Peak Output Current: 6A • Wide Input Supply Voltage Operating Range: - 4.5V to 18V • High Capacitive Load Drive Capability: 10,000 pF • Short Delay Time: 55 ns (typ.) • CMOS/TTL Compatible Input • Low Supply Current With Logic ‘1’ Input: - 450 µA (typ.) • Low Output Impedance: 2.5 • Output Voltage Swing to Within 25 mV of Ground or VDD • Space-Saving 8-Pin SOIC and 8-Pin 6x5 DFN Packages The TC4420/TC4429 are 6A (peak), single-output MOSFET drivers. The TC4429 is an inverting driver (pin-compatible with the TC429), while the TC4420 is a non-inverting driver. These drivers are fabricated in CMOS for lower power and more efficient operation versus bipolar drivers. Both devices have TTL/CMOS compatible inputs that can be driven as high as VDD + 0.3V or as low as –5V without upset or damage to the device. This eliminates the need for external level-shifting circuitry and its associated cost and size. The output swing is rail-to-rail, ensuring better drive voltage margin, especially during power-up/power-down sequencing. Propagational delay time is only 55 ns (typ.) and the output rise and fall times are only 25 ns (typ.) into 2500 pF across the usable power supply range. Unlike other drivers, the TC4420/TC4429 are virtually latch-up proof. They replace three or more discrete components, saving PCB area, parts and improving overall system reliability. Applications • • • • Switch-Mode Power Supplies Motor Controls Pulse Transformer Driver Class D Switching Amplifiers Package Types(1) VDD INPUT NC GND 1 2 3 TC4420 8 TC4420 TC4429 4 7 6 5 Note 1: 2: VDD OUTPUT OUTPUT GND 8-Pin DFN(2) TC4429 VDD OUTPUT OUTPUT GND VDD 1 INPUT 2 NC 3 TC4420 TC4429 GND 4 Duplicate pins must both be connected for proper operation. Exposed pad of the DFN package is electrically isolated. 2002-2012 Microchip Technology Inc. TC4420 TC4429 8 VDD 7 OUTPUT OUTPUT 6 OUTPUT OUTPUT 5 GND 5-Pin TO-220 Tab is Common to VDD VDD TC4420 TC4429 GND INPUT GND VDD GND OUTPUT 8-Pin CERDIP/ PDIP/SOIC DS21419D-page 1 TC4420/TC4429 Functional Block Diagram VDD 500 µA TC4429 Inverting 300 mV Output TC4420 Non-Inverting Input 4.7V GND Effective Input C = 38 pF DS21419D-page 2 2002-2012 Microchip Technology Inc. TC4420/TC4429 1.0 ELECTRICAL CHARACTERISTICS † Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings† Supply Voltage ..................................................... +20V Input Voltage .................................. – 5V to VDD + 0.3V Input Current (VIN > VDD)................................... 50 mA Power Dissipation (TA 70°C) 5-Pin TO-220 .................................................... 1.6W CERDIP ....................................................... 800 mW DFN ............................................ ...................Note 2 PDIP ............................................................ 730 mW SOIC............................................................ 470 mW Package Power Dissipation (TA 25°C) 5-Pin TO-220 (With Heatsink) ........................ 12.5W Thermal Impedances (To Case) 5-Pin TO-220 RJ-C ...................................... 10°C/W DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, TA = +25°C with 4.5V VDD 18V. Parameters Sym Min Typ Max Units Conditions Logic ‘1’, High Input Voltage VIH 2.4 1.8 — V Logic ‘0’, Low Input Voltage VIL — 1.3 0.8 V Input Voltage Range VIN –5 — VDD+0.3 V Input Current IIN –10 — +10 µA 0VVINVDD VOH VDD – 0.025 — — V DC TEST Low Output Voltage VOL — — 0.025 V DC TEST Output Resistance, High ROH — 2.1 2.8 IOUT = 10 mA, VDD = 18V Output Resistance, Low ROL — 1.5 2.5 IOUT = 10 mA, VDD = 18V Peak Output Current IPK — 6.0 — A VDD = 18V Latch-Up Protection Withstand Reverse Current IREV — > 1.5 — A Duty cycle2%, t 300 µsec Rise Time tR — 25 35 ns Figure 4-1, CL = 2,500 pF Fall Time tF — 25 35 ns Figure 4-1, CL = 2,500 pF Delay Time tD1 — 55 75 ns Figure 4-1 Delay Time tD2 — 55 75 ns Figure 4-1 IS — — 0.45 55 1.5 150 mA µA VIN = 3V VIN = 0V VDD 4.5 — 18 V Input Output High Output Voltage Switching Time (Note 1) Power Supply Power Supply Current Operating Input Voltage Note 1: 2: Switching times ensured by design. Package power dissipation is dependent on the copper pad area on the PCB. 2002-2012 Microchip Technology Inc. DS21419D-page 3 TC4420/TC4429 DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE) Electrical Specifications: Unless otherwise noted, over operating temperature range with 4.5V VDD 18V. Parameters Sym Min Typ Max Units Conditions Logic ‘1’, High Input Voltage VIH 2.4 — — V Logic ‘0’, Low Input Voltage VIL — — 0.8 V Input Voltage Range VIN –5 — VDD + 0.3 V Input Current IIN –10 — +10 µA 0VVINVDD VOH VDD – 0.025 — — V DC TEST Low Output Voltage VOL — — 0.025 V DC TEST Output Resistance, High ROH — 3 5 IOUT = 10 mA, VDD = 18V Output Resistance, Low ROL — 2.3 5 IOUT = 10 mA, VDD = 18V Rise Time tR — 32 60 ns Figure 4-1, CL = 2,500 pF Fall Time tF — 34 60 ns Figure 4-1, CL = 2,500 pF Delay Time tD1 — 50 100 ns Figure 4-1 Delay Time tD2 — 65 100 ns Figure 4-1 IS — — 0.45 60 3 400 mA µA VIN = 3V VIN = 0V VDD 4.5 — 18 V Input Output High Output Voltage Switching Time (Note 1) Power Supply Power Supply Current Operating Input Voltage Note 1: Switching times ensured by design. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V VDD 18V. Parameters Sym Min Typ Max Units Specified Temperature Range (C) TA 0 — +70 °C Specified Temperature Range (I) TA –25 — +85 °C Specified Temperature Range (E) TA –40 — +85 °C Specified Temperature Range (V) TA –40 — +125 °C Maximum Junction Temperature TJ — — +150 °C Storage Temperature Range TA –65 — +150 °C Conditions Temperature Ranges Package Thermal Resistances Thermal Resistance, 5L-TO-220 JA — 71 — °C/W Thermal Resistance, 8L-CERDIP JA — 150 — °C/W Thermal Resistance, 8L-6x5 DFN JA — 33.2 — °C/W Thermal Resistance, 8L-PDIP JA — 125 — °C/W Thermal Resistance, 8L-SOIC JA — 155 — °C/W DS21419D-page 4 Typical four-layer board with vias to ground plane. 2002-2012 Microchip Technology Inc. TC4420/TC4429 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V. 120 100 80 C L = 10,000 pF 80 Time (nsec) Time (nsec) 100 60 C L = 4700 pF 40 C L = 2200 pF 5 7 9 11 13 C L = 4700 pF 40 C L = 2200 pF 20 20 0 C L = 10,000 pF 60 0 15 5 7 Supply Voltage (V) Rise Time vs. Supply FIGURE 2-4: Voltage. 100 80 80 60 60 VDD = 5V 40 VDD = 12V VDD = 18V 20 13 15 40 VDD = 5V VDD = 12V VDD = 18V 20 10 1000 10 1000 10,000 10,000 Capcitive Load (pF) FIGURE 2-2: Load. Capacitive Load (pF) Rise Time vs. Capacitive FIGURE 2-5: Load. 50 Fall Time vs. Capacitive 84 C L = 2200 pF VDD = 18V VDD = 15V 70 40 t D2 30 Supply Current (mA) Delay Time (nsec) 11 Fall Time vs. Supply 100 Time (nsec) Time (nsec) FIGURE 2-1: Voltage. 9 Supply Voltage (V) t D1 20 10 56 42 500 kHz 28 200 kHz 14 20 kHz 0 –60 FIGURE 2-3: Temperature. –20 20 60 TA (°C) 100 140 Propagation Delay Time vs. 2002-2012 Microchip Technology Inc. 0 0 FIGURE 2-6: Capacitive Load. 100 1000 Capacitive Load (pF) 10,000 Supply Current vs. DS21419D-page 5 TC4420/TC4429 Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V. 50 5 C L = 2200 pF VDD = 18V 40 30 ROUT (Ω ) Time (nsec) 100 mA 4 t FALL t RISE 20 50 mA 10 mA 3 10 0 –60 –20 FIGURE 2-7: Temperature. 20 60 TA (°C) 100 2 140 Rise and Fall Times vs. 5 7 9 11 13 Supply Voltage (V) 15 FIGURE 2-10: High-State Output Resistance vs Supply Voltage. 65 200 Load = 2200 pF 160 Delay Time (nsec) Delay Time (nsec) 60 55 tD2 50 45 tD1 120 Input 2.4V Input 3V 80 Input 5V 40 40 35 4 6 8 10 12 14 16 Input 8V and 10V 0 18 5 6 7 Supply Voltage (V) FIGURE 2-8: Supply Voltage. Propagation Delay Time vs. 8 9 10 11 12 13 14 15 VDD (V) FIGURE 2-11: Effect of Input Amplitude on Propagation Delay. 2.5 1000 CL = 2200 pF 10V 100 5V 10 2 ROUT (Ω ) Supply Current (mA) 18V 100 mA 50 mA 1.5 10 mA 0 0 FIGURE 2-9: Frequency. DS21419D-page 6 100 1000 Frequency (kHz) 10,000 Supply Current vs. 1 5 7 9 11 13 Supply Voltage (V) 15 FIGURE 2-12: Low-State Output Resistance vs. Supply Voltage. 2002-2012 Microchip Technology Inc. TC4420/TC4429 Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V. Crossover Area (A•S) x 10 -8 4 3 2 1 0 5 6 7 8 9 10 11 12 13 14 15 Supply Voltage (V) The values on this graph represent the loss seen by the driver during one complete cycle. For a single transition, divide the value by 2. FIGURE 2-13: Crossover Energy. 2002-2012 Microchip Technology Inc. DS21419D-page 7 TC4420/TC4429 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin No. 8-Pin CERDIP/ PDIP/SOIC Pin No. 8-Pin DFN Pin No. 5-Pin TO-220 Symbol 1 1 — VDD 2 2 1 INPUT 3 3 — NC 4 4 2 GND Ground 5 5 4 GND Ground 6 6 5 OUTPUT CMOS push-pull output 7 7 — OUTPUT CMOS push-pull output 3.1 Description Supply input, 4.5V to 18V Control input, TTL/CMOS compatible input No Connection 8 8 3 VDD Supply input, 4.5V to 18V — PAD — NC Exposed Metal Pad — — TAB VDD Metal Tab is at the VDD Potential Supply Input (VDD) The VDD input is the bias supply for the MOSFET driver and is rated for 4.5V to 18V with respect to the ground pins. The VDD input should be bypassed to ground with a local ceramic capacitor. The value of the capacitor should be chosen based on the capacitive load that is being driven. A minimum value of 1.0 µF is suggested. 3.3 The MOSFET driver output is a low-impedance, CMOS, push-pull style output capable of driving a capacitive load with 6.0A peak currents. The MOSFET driver output is capable of withstanding 1.5A peak reverse currents of either polarity. 3.4 3.2 Control Input The MOSFET driver input is a high-impedance, TTL/CMOS compatible input. The input circuitry of the TC4420/TC4429 MOSFET driver also has a “speedup” capacitor. This helps to decrease the propagation delay times of the driver. Because of this, input signals with slow rising or falling edges should not be used, as this can result in double-pulsing of the MOSFET driver output. DS21419D-page 8 CMOS Push-Pull Output Ground The ground pins are the return path for the bias current and the high peak currents that discharge the load capacitor. The ground pins should be tied into a ground plane or have very short traces to the bias supply source return. 3.5 Exposed Metal Pad The exposed metal pad of the 6x5 DFN package is not internally connected to any potential. Therefore, this pad can be connected to a ground plane or other copper plane on a printed circuit board (PCB) to aid in heat removal from the package. 2002-2012 Microchip Technology Inc. TC4420/TC4429 4.0 APPLICATIONS INFORMATION +5V 90% Input VDD = 18V 0V tD1 tD2 tF +18V 4.7 µF 1 10% tR 90% 90% Output 8 0.1 µF 0.1 µF 10% 10% 0V Inverting Driver Input 2 6 TC4429 Output 7 CL = 2,500 pF +5V 90% Input 4 5 0V +18V Input: 100 kHz, square wave, tRISE = tFALL 10 ns 10% tD1 90% tR Output 0V 10% tD2 90% tF 10% Non-Inverting Driver TC4420 Note: Pinout shown is for the PDIP, SOIC, DFN and CERDIP packages. FIGURE 4-1: Switching Time Test Circuits. 2002-2012 Microchip Technology Inc. DS21419D-page 9 TC4420/TC4429 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 5-Lead TO-220 XXXXXXXXX XXXXXXXXX YYWWNNN 8-Lead CERDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead DFN XXXXXXX XXXXXXX XXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS21419D-page 10 Example: TC4420CAT 0419256 Example: TC4420 MJA256 0419 Example: TC4420 EMF 0419 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2002-2012 Microchip Technology Inc. TC4420/TC4429 Package Marking Information (Continued) 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 2002-2012 Microchip Technology Inc. Example: TC4420 CPA256 0419 Example: TC4420 EOA0419 256 DS21419D-page 11 TC4420/TC4429 5-Lead Plastic Transistor Outline (AT) (TO-220) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging L H1 Q b e3 e1 E e ØP EJECTOR PIN a (5X) C1 A J1 F D Units Dimension Limits e Lead Pitch Overall Lead Centers Space Between Leads Overall Height Overall Width Overall Length Flag Length Flag Thickness Through Hole Center Through Hole Diameter Lead Length Base to Bottom of Lead Lead Thickness Lead Width Mold Draft Angle e1 e3 A E D H1 F Q P L J1 C1 b a INCHES* MIN MAX .060 .072 .263 .273 .030 .040 .160 .190 .385 .415 .560 .590 .234 .258 .045 .055 .103 .113 .146 .156 .540 .560 .090 .115 .022 .014 .025 .040 3° 7° MILLIMETERS MAX MIN 1.52 1.83 6.68 6.93 0.76 1.02 4.06 4.83 9.78 10.54 14.22 14.99 5.94 6.55 1.14 1.40 2.62 2.87 3.71 3.96 14.22 13.72 2.29 2.92 0.36 0.56 0.64 1.02 3° 7° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: TO-220 Drawing No. C04-036 DS21419D-page 12 2002-2012 Microchip Technology Inc. TC4420/TC4429 8-Lead Ceramic Dual In-line – 300 mil (JA) (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 2 1 n D E A2 A c L B1 eB B A1 Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Standoff § Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing *Controlling Parameter JEDEC Equivalent: MS-030 A A1 E E1 D L c B1 B eB p MIN .160 .020 .290 .230 .370 .125 .008 .045 .016 .320 INCHES* NOM 8 .100 .180 .030 .305 .265 .385 .163 .012 .055 .018 .360 MAX .200 .040 .320 .300 .400 .200 .015 .065 .020 .400 MILLIMETERS NOM 8 2.54 4.06 4.57 0.51 0.77 7.37 7.75 5.84 6.73 9.40 9.78 3.18 4.13 0.20 0.29 1.14 1.40 0.41 0.46 8.13 9.15 MIN MAX 5.08 1.02 8.13 7.62 10.16 5.08 0.38 1.65 0.51 10.16 Drawing No. C04-010 2002-2012 Microchip Technology Inc. DS21419D-page 13 TC4420/TC4429 8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Saw Singulated Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21419D-page 14 2002-2012 Microchip Technology Inc. TC4420/TC4429 8-Lead Plastic Dual In-line (PA) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic § A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2002-2012 Microchip Technology Inc. DS21419D-page 15 TC4420/TC4429 8-Lead Plastic Small Outline (OA) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21419D-page 16 2002-2012 Microchip Technology Inc. TC4420/TC4429 6.0 REVISION HISTORY Revision D (December 2012) Added a note to each package outline drawing. 2002-2012 Microchip Technology Inc. DS21419D-page 17 TC4420/TC4429 NOTES: DS21419D-page 18 2002-2012 Microchip Technology Inc. TC4420/TC4429 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range Device: TC4420: TC4429: XX XXX X Package Tape and Reel PB Free 6A High-Speed MOSFET Driver, Non-Inverting 6A High-Speed MOSFET Driver, Inverting Examples: a) TC4420CAT: 6A High-Speed MOSFET Driver, Non-inverting, TO-220 package, 0°C to +70°C. b) TC4420EOA: 6A High-Speed MOSFET Driver, Non-inverting, SOIC package, -40°C to +85°C. Temperature Range: Package: PB Free C I E V = = = = 0°C to +70°C (PDIP, SOIC, and TO-220 Only) -25°C to +85°C (CERDIP Only) -40°C to +85°C -40°C to +125°C AT JA = TO-220, 5-lead (C-Temp Only) = Ceramic Dual In-line (300 mil Body), 8-lead (I-Temp Only) MF = Dual, Flat, No-Lead (6X5 mm Body), 8-lead MF713 = Dual, Flat, No-Lead (6X5 mm Body), 8-lead (Tape and Reel) PA = Plastic DIP (300 mil Body), 8-lead OA = Plastic SOIC, (150 mil Body), 8-lead OA713 = Plastic SOIC, (150 mil Body), 8-lead (Tape and Reel) G = Lead-Free device* = Blank c) TC4420VMF: 6A High-Speed MOSFET Driver, Non-inverting, DFN package, -40°C to +125°C. a) TC4429CAT: 6A High-Speed MOSFET Driver, Inverting, TO-220 package, 0°C to +70°C b) TC4429EPA: 6A High-Speed MOSFET Driver, Inverting, PDIP package, -40°C to +85°C c) TC4429VMF: * Available on selected packages. Contact your local sales representative for availability 6A High-Speed MOSFET Driver, Inverting, DFN package, -40°C to +125°C Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002-2012 Microchip Technology Inc. DS21419D-page 19 TC4420/TC4429 NOTES: DS21419D-page 20 2002-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. 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Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2002-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620767948 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2002-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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