TC7660 Charge Pump DC-to-DC Voltage Converter Features Package Types • • • • • Wide Input Voltage Range: +1.5V to +10V Efficient Voltage Conversion (99.9%, typ) Excellent Power Efficiency (98%, typ) Low Power Consumption: 80 µA (typ) @ VIN = 5V Low Cost and Easy to Use - Only Two External Capacitors Required • Available in 8-Pin Small Outline (SOIC), 8-Pin PDIP and 8-Pin CERDIP Packages • Improved ESD Protection (3 kV HBM) • No External Diode Required for High-Voltage Operation PDIP/CERDIP/SOIC NC CAP+ 2 GND 3 TC7660 CAP- 4 8 V+ 7 OSC 6 LOW VOLTAGE (LV) 5 VOUT General Description The TC7660 device is a pin-compatible replacement for the industry standard 7660 charge pump voltage converter. It converts a +1.5V to +10V input to a corresponding -1.5V to -10V output using only two low-cost capacitors, eliminating inductors and their associated cost, size and electromagnetic interference (EMI). Applications • • • • 1 RS-232 Negative Power Supply Simple Conversion of +5V to ±5V Supplies Voltage Multiplication VOUT = ± n V+ Negative Supplies for Data Acquisition Systems and Instrumentation The on-board oscillator operates at a nominal frequency of 10 kHz. Operation below 10 kHz (for lower supply current applications) is possible by connecting an external capacitor from OSC to ground. The TC7660 is available in 8-Pin PDIP, 8-Pin Small Outline (SOIC) and 8-Pin CERDIP packages in commercial and extended temperature ranges. Functional Block Diagram V+ CAP+ 8 OSC LV 7 RC Oscillator 2 2 Voltage Level Translator 4 CAP- 6 5 VOUT Internal Internal Voltage Voltage Regulator Regulator Logic Network TC7660 3 GND 2002-2011 Microchip Technology Inc. DS21465C-page 1 TC7660 1.0 ELECTRICAL CHARACTERISTICS * Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Supply Voltage .............................................................+10.5V LV and OSC Inputs Voltage: (Note 1) .............................................. -0.3V to VSS for V+ < 5.5V ..................................... (V+ – 5.5V) to (V+) for V+ > 5.5V Current into LV ......................................... 20 µA for V+ > 3.5V Output Short Duration (VSUPPLY 5.5V)............... Continuous Package Power Dissipation: (TA 70°C) 8-Pin CERDIP ....................................................800 mW 8-Pin PDIP .........................................................730 mW 8-Pin SOIC .........................................................470 mW Operating Temperature Range: C Suffix.......................................................0°C to +70°C I Suffix .....................................................-25°C to +85°C E Suffix ....................................................-40°C to +85°C M Suffix .................................................-55°C to +125°C Storage Temperature Range .........................-65°C to +160°C ESD protection on all pins (HBM) ................... .............. 3 kV Maximum Junction Temperature ........... ....................... 150°C 1 C1 + 10 µF 2 3 IS 8 TC7660 4 7 V+ (+5V) IL COSC 6 RL 5 VOUT C2 + 10 µF FIGURE 1-1: TC7660 Test Circuit. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, specifications measured over operating temperature range with V+ = 5V, COSC = 0, refer to test circuit in Figure 1-1. Parameters Supply Current Supply Voltage Range, High Supply Voltage Range, Low Output Source Resistance Sym Min Typ Max Units I+ Conditions — 80 180 µA RL = V+H V+L 3.0 — 10 V Min TAMax, RL = 10 k, LV Open 1.5 — 3.5 V Min TAMax, RL = 10 k, LV to GND ROUT — 70 100 IOUT=20 mA, TA = +25°C — — 120 IOUT=20 mA, TA +70°C (C Device) — — 130 IOUT=20 mA, TA +85°C (E and I Device) — 104 150 IOUT=20 mA, TA +125°C (M Device) — 150 300 V+ = 2V, IOUT = 3 mA, LV to GND 0°C TA +70°C — 160 600 V+ = 2V, IOUT = 3 mA, LV to GND -55°C TA +125°C (M Device) Oscillator Frequency fOSC — 10 — kHz Pin 7 open Power Efficiency PEFF 95 98 — % RL = 5 k VOUTEFF 97 99.9 — % RL = ZOSC — 1.0 — M V+ = 2V — 100 — k V+ = 5V Voltage Conversion Efficiency Oscillator Impedance Note 1: Destructive latch-up may occur if voltages greater than V+ or less than GND are supplied to any input pin. DS21465C-page 2 2002-2011 Microchip Technology Inc. TC7660 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, C1 = C2 = 10 µF, ESRC1 = ESRC2 = 1 , TA = 25°C. See Figure 1-1. POWER CONVERSION EFFICIENCY (%) 12 SUPPLY VOLTAGE (V) 10 8 6 SUPPLY VOLTAGE RANGE 4 2 0 -55 -25 0 +25 +50 +75 +100 +125 TEMPERATURE (°C) FIGURE 2-1: Temperature. Operating Voltage vs. OUTPUT SOURCE RESISTANCE (Ω) OUTPUT SOURCE RESISTANCE (Ω) IOUT = 1 mA 96 94 92 IOUT = 15 mA 90 88 86 84 82 V+ = +5V 80 100 1k OSCILLATOR FREQUENCY (Hz) 10k 500 1k 100Ω 10Ω 0 1 2 3 4 5 6 SUPPLY VOLTAGE (V) 7 10k 200 150 V + = +2V 100 OSCILLATOR FREQUENCY (kHz) 100 10 10k FIGURE 2-3: Frequency of Oscillation vs. Oscillator Capacitance. V + = +5V 50 20 1k 2002-2011 Microchip Technology Inc. 400 -25 0 +25 +50 +75 +100 +125 TEMPERATURE (°C) FIGURE 2-5: vs. Temperature. V+ = +5V 10 100 1000 OSCILLATOR CAPACITANCE (pF) IOUT = 1 mA 450 0 -55 8 FIGURE 2-2: Output Source Resistance vs. Supply Voltage. OSCILLATOR FREQUENCY (Hz) 98 FIGURE 2-4: Power Conversion Efficiency vs. Oscillator Frequency. 10k 1 100 Output Source Resistance V+ = +5V 18 16 14 12 10 8 6 -55 -25 0 +25 +50 +75 +100 +125 TEMPERATURE (°C) FIGURE 2-6: Unloaded Oscillator Frequency vs. Temperature. DS21465C-page 3 TC7660 0 5 -1 4 -2 3 OUTPUT VOLTAGE (V) -3 -4 -5 -6 -7 -8 0 -1 -2 -3 SLOPE 55Ω LV OPEN -5 10 FIGURE 2-7: Current. 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (mA) 0 Output Voltage vs. Output 100 20 18 80 16 70 14 60 12 50 10 40 8 30 6 20 4 10 2 0 0 9.0 1.5 3.0 4.5 6.0 7.5 LOAD CURRENT (mA) SUPPLY CURRENT (mA) V+ = 2V 90 FIGURE 2-8: Supply Current and Power Conversion Efficiency vs. Load Current. 2 10 FIGURE 2-10: Current. POWER CONVERSION EFFICIENCY (%) 0 POWER CONVERSION EFFICIENCY (%) 2 1 -4 -9 -10 OUTPUT VOLTAGE (V) V+ = +5V 20 30 40 50 60 LOAD CURRENT (mA) 70 80 Output Voltage vs. Load 100 100 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 SUPPLY CURRENT (mA) OUTPUT VOLTAGE (V) Note: Unless otherwise indicated, C1 = C2 = 10 µF, ESRC1 = ESRC2 = 1 , TA = 25°C. See Figure 1-1. 10 V+ = +5V 0 0 10 20 30 40 50 LOAD CURRENT (mA) 60 FIGURE 2-11: Supply Current and Power Conversion Efficiency vs. Load Current. V+ = +2V 1 0 -1 SLOPE 150Ω -2 0 FIGURE 2-9: Current. DS21465C-page 4 1 2 3 4 5 6 LOAD CURRENT (mA) 7 8 Output Voltage vs. Load 2002-2011 Microchip Technology Inc. TC7660 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: 3.1 PIN FUNCTION TABLE Pin No. Symbol 1 NC 2 CAP+ Charge pump capacitor positive terminal 3 GND Ground terminal 4 CAP- Charge pump capacitor negative terminal 5 VOUT Output voltage 6 LV 7 OSC 8 V+ Description No connection Low voltage pin. Connect to GND for V+ < 3.5V Oscillator control input. Bypass with an external capacitor to slow the oscillator Power supply positive voltage input Charge Pump Capacitor (CAP+) Positive connection for the charge pump capacitor, or flying capacitor, used to transfer charge from the input source to the output. In the voltage-inverting configuration, the charge pump capacitor is charged to the input voltage during the first half of the switching cycle. During the second half of the switching cycle, the charge pump capacitor is inverted and charge is transferred to the output capacitor and load. It is recommended that a low ESR (equivalent series resistance) capacitor be used. Additionally, larger values will lower the output resistance. 3.2 Ground (GND) Input and output zero volt reference. 3.3 Charge Pump Capacitor (CAP-) Negative connection for the charge pump capacitor, or flying capacitor, used to transfer charge from the input to the output. Proper orientation is imperative when using a polarized capacitor. 3.4 3.5 Low Voltage Pin (LV) The low voltage pin ensures proper operation of the internal oscillator for input voltages below 3.5V. The low voltage pin should be connected to ground (GND) for input voltages below 3.5V. Otherwise, the low voltage pin should be allowed to float. 3.6 Oscillator Control Input (OSC) The oscillator control input can be utilized to slow down or speed up the operation of the TC7660. Refer to Section 5.4 “Changing the TC7660 Oscillator Frequency”, for details on altering the oscillator frequency. 3.7 Power Supply (V+) Positive power supply input voltage connection. It is recommended that a low ESR (equivalent series resistance) capacitor be used to bypass the power supply input to ground (GND). Output Voltage (VOUT) Negative connection for the charge pump output capacitor. In the voltage-inverting configuration, the charge pump output capacitor supplies the output load during the first half of the switching cycle. During the second half of the switching cycle, charge is restored to the charge pump output capacitor. It is recommended that a low ESR (equivalent series resistance) capacitor be used. Additionally, larger values will lower the output ripple. 2002-2011 Microchip Technology Inc. DS21465C-page 5 TC7660 4.0 DETAILED DESCRIPTION 4.1 Theory of Operation 1 R OUT = ----------------------------- + 8R SW + 4ESR C1 + ESR C2 fPUMP C1 The TC7660 charge pump converter inverts the voltage applied to the V + pin. The conversion consists of a twophase operation (Figure 4-1). During the first phase, switches S2 and S4 are open and switches S1 and S3 are closed. C1 charges to the voltage applied to the V + pin, with the load current being supplied from C2. During the second phase, switches S2 and S4 are closed and switches S1 and S3 are open. Charge is transferred from C1 to C2, with the load current being supplied from C1. V+ S1 S2 + GND Where: f OSC f PUMP = ----------2 R SW = on-resistance of the switches ESR C1 = equivalent series resistance of C 1 ESR C2 = equivalent series resistance of C 2 4.2 1. C2 Losses from power consumed by the internal oscillator, switch drive, etc. These losses will vary with input voltage, temperature and oscillator frequency. Conduction losses in the non-ideal switches. Losses due to the non-ideal nature of the external capacitors. Losses that occur during charge transfer from C1 to C2 when a voltage difference between the capacitors exists. + VOUT = -VIN 2. 3. 4. FIGURE 4-1: Inverter. Switched Capacitor Inverter Power Losses The overall power loss of a switched capacitor inverter is affected by four factors: C1 S4 S3 EQUATION Ideal Switched Capacitor In this manner, the TC7660 performs a voltage inversion, but does not provide regulation. The average output voltage will drop in a linear manner with respect to load current. The equivalent circuit of the charge pump inverter can be modeled as an ideal voltage source in series with a resistor, as shown in Figure 4-2. Figure 4-3 depicts the non-ideal elements associated with the switched capacitor inverter power loss. RSW V+ + - ROUT IDD C1 RSW + ESRC1 VOUT - S1 RSW S3 S2 C2 + ESRC2 RSW IOUT LOAD S4 V+ + FIGURE 4-2: Switched Capacitor Inverter Equivalent Circuit Model. The value of the series resistor (ROUT) is a function of the switching frequency, capacitance and equivalent series resistance (ESR) of C1 and C2 and the on-resistance of switches S1, S2, S3 and S4. A close approximation for ROUT is given in the following equation: DS21465C-page 6 FIGURE 4-3: Non-Ideal Switched Capacitor Inverter. The power loss is calculated using the following equation: EQUATION 2 P LOSS = I OUT R OUT + I DD V + 2002-2011 Microchip Technology Inc. TC7660 5.0 APPLICATIONS INFORMATION 5.2 5.1 Simple Negative Voltage Converter To reduce the value of ROUT, multiple TC7660 voltage converters can be connected in parallel (Figure 5-2). The output resistance will be reduced by approximately a factor of n, where n is the number of devices connected in parallel. Figure 5-1 shows typical connections to provide a negative supply where a positive supply is available. A similar scheme may be employed for supply voltages anywhere in the operating range of +1.5V to +10V, keeping in mind that pin 6 (LV) is tied to the supply negative (GND) only for supply voltages below 3.5V. EQUATION R OUT of TC7660 R OUT = --------------------------------------------------------n number of devices While each device requires its own pump capacitor (C1), all devices may share one reservoir capacitor (C2). To preserve ripple performance, the value of C2 should be scaled according to the number of devices connected in parallel. V+ 8 1 C1 10 µF 2 + 3 7 TC7660 VOUT* C2 + 10 µF 6 5 4 5.3 Cascading Devices A larger negative multiplication of the initial supply voltage can be obtained by cascading multiple TC7660 devices. The output voltage and the output resistance will both increase by approximately a factor of n, where n is the number of devices cascaded. * VOUT = -V+ for 1.5V V+ 10V FIGURE 5-1: Paralleling Devices Simple Negative Converter. The output characteristics of the circuit in Figure 5-1 are those of a nearly ideal voltage source in series with a 70resistor. Thus, for a load current of -10 mA and a supply voltage of +5V, the output voltage would be -4.3V. EQUATION + VOUT = – n V ROUT = n R OUT of TC7660 V+ 1 C1 2 + 3 8 TC7660 4 “1” 8 1 7 6 C1 5 + 2 3 4 TC7660 “n” RL 7 6 5 + FIGURE 5-2: C2 Paralleling Devices Lowers Output Impedance. V+ 8 1 10 µF + 2 3 TC7660 4 “1” 7 1 6 5 10 µF + 2 3 4 * VOUT = -n FIGURE 5-3: V+ + 8 TC7660 “n” 10 µF 7 6 VOUT * 5 + 10 µF for 1.5V V+ 10V Increased Output Voltage By Cascading Devices. 2002-2011 Microchip Technology Inc. DS21465C-page 7 TC7660 5.4 Changing the TC7660 Oscillator Frequency The operating frequency of the TC7660 can be changed in order to optimize the system performance. The frequency can be increased by over-driving the OSC input (Figure 5-4). Any CMOS logic gate can be utilized in conjunction with a 1 k series resistor. The resistor is required to prevent device latch-up. While TTL level signals can be utilized, an additional 10 k pull-up resistor to V+ is required. Transitions occur on the rising edge of the clock input. The resultant output voltage ripple frequency is one half the clock input. Higher clock frequencies allow for the use of smaller pump and reservoir capacitors for a given output voltage ripple and droop. Additionally, this allows the TC7660 to be synchronized to an external clock, eliminating undesirable beat frequencies. At light loads, lowering the oscillator frequency can increase the efficiency of the TC7660 (Figure 5-5). By lowering the oscillator frequency, the switching losses are reduced. Refer to Figure 2-3 to determine the typical operating frequency based on the value of the external capacitor. At lower operating frequencies, it may be necessary to increase the values of the pump and reservoir capacitors in order to maintain the desired output voltage ripple and output impedance. V+ 8 1 10 µF 2 + 3 4 TC7660 “1” 7 1 k C1 + 2 3 TC7660 4 VOUT 10 µF V+ 7 COSC VOUT 5 + FIGURE 5-5: Frequency. DS21465C-page 8 where: VF1 is the forward voltage drop of diode D1 and VF2 is the forward voltage drop of diode D2. V+ 1 2 8 TC7660 C2 FIGURE 5-6: 5.6 7 6 5 CMOS GATE 5 6 + V OUT = 2 V – V F1 + V F2 4 6 8 EQUATION 3 External Clocking. 1 Positive Voltage Multiplication Positive voltage multiplication can be obtained by employing two external diodes (Figure 5-6). Refer to the theory of operation of the TC7660 (Section 4.1 “Theory of Operation”). During the half cycle when switch S2 is closed, capacitor C1 of Figure 5-6 is charged up to a voltage of V+ - VF1, where VF1 is the forward voltage drop of diode D1. During the next half cycle, switch S1 is closed, shifting the reference of capacitor C1 from GND to V+. The energy in capacitor C1 is transferred to capacitor C2 through diode D2, producing an output voltage of approximately: V+ + FIGURE 5-4: 5.5 D1 + D2 C1 VOUT = (2 V+) - (2 VF) + C2 Positive Voltage Multiplier. Combined Negative Voltage Conversion and Positive Supply Multiplication Simultaneous voltage inversion and positive voltage multiplication can be obtained (Figure 5-7). Capacitors C1 and C3 perform the voltage inversion, while capacitors C2 and C4, plus the two diodes, perform the positive voltage multiplication. Capacitors C1 and C2 are the pump capacitors, while capacitors C3 and C4 are the reservoir capacitors for their respective functions. Both functions utilize the same switches of the TC7660. As a result, if either output is loaded, both outputs will drop towards GND. Lowering Oscillator 2002-2011 Microchip Technology Inc. TC7660 V+ 1 2 3 + C1 VOUT = -V+ 8 TC7660 4 7 D1 6 + C3 VOUT = D2 (2 V+) - (2 VF) 5 + + C2 C4 FIGURE 5-7: Combined Negative Converter and Positive Multiplier. 5.7 Efficient Positive Voltage Multiplication/Conversion Since the switches that allow the charge pumping operation are bidirectional, the charge transfer can be performed backwards as easily as forwards. Figure 5-8 shows a TC7660 transforming -5V to +5V (or +5V to +10V, etc.). The only problem here is that the internal clock and switch-drive section will not operate until some positive voltage has been generated. An initial inefficient pump, as shown in Figure 5-7, could be used to start this circuit up, after which it will bypass the other (D1 and D2 in Figure 5-7 would never turn on), or else the diode and resistor shown dotted in Figure 5-8 can be used to “force” the internal regulator on. VOUT = -V - C1 10 µF + 1 8 2 7 3 4 TC7660 + 1 M 10 µF 6 5 V - input FIGURE 5-8: Conversion. Positive Voltage 2002-2011 Microchip Technology Inc. DS21465C-page 9 TC7660 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead CERDIP (.300”) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) NNN Legend: XX...X Y YY WW NNN e3 * Note: DS21465C-page 10 Example TC7660 CPA e3 256 1208 Example TC7660 MJA e3 256 Example TC7660 CPA256 1208 Example TC7660 MJA256 1208 1208 Example Example TC7660C OA e3 1208 TC7660C OA1208 256 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. 2002-2011 Microchip Technology Inc. TC7660 4&'!&"& 5#*!( !!& 5 %&&#& && 366***' '6 5 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 7&! '!:'&! 8"')%! 8,9. 8 8 8; < = & && > > ##55!! 1 - 1 2!&& 1 > > "#&"#?#& . - -1 ##5?#& . 1 = ; :& -= -1 && : 1 - 1 :#5!! = 1 ) ) = 2 > > 7 :#?#& :*:#?#& ; * + 2, - !"#$%&"' ()"&'"!&)&#*&&&# +%&,&!& - '!!#.#&"#'#%! &"!!#%! &"!!!&$#/ !# '!#& .01 2,32!'!&$& "!**&"&&! * ,=2 2002-2011 Microchip Technology Inc. DS21465C-page 11 TC7660 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21465C-page 12 2002-2011 Microchip Technology Inc. TC7660 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2002-2011 Microchip Technology Inc. DS21465C-page 13 TC7660 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21465C-page 14 2002-2011 Microchip Technology Inc. TC7660 ! " "##$%&'!"( 4&'!&"& 5#*!( !!& 5 %&&#& && 366***' '6 5 2002-2011 Microchip Technology Inc. DS21465C-page 15 TC7660 APPENDIX A: REVISION HISTORY Revision C (March 2012) The following is the list of modifications. 1. 2. Updated Figure 5-5. Added Appendix A. Revision B (March 2003) Undocumented changes. Revision A (May 2002) Original release of this document. DS21465C-page 16 2002-2012 Microchip Technology Inc. TC7660 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Temperature Range Package Examples: a) b) c) Device: TC7660: DC-to-DC Voltage Converter d) Temperature Range: C E I M = = = = 0°C to +70°C -40°C to +85°C -25°C to +85°C (CERDIP only) -55°C to +125°C (CERDIP only) e) f) g) Package: PA JA OA OA713 = = = = Plastic DIP, (300 mil body), 8-lead Ceramic DIP, (300 mil body), 8-lead SOIC (Narrow), 8-lead SOIC (Narrow), 8-lead (Tape and Reel) 2002-2012 Microchip Technology Inc. h) TC7660COA: Commercial Temp., SOIC package. TC7660COA713:Tape and Reel, Commercial Temp., SOIC package. TC7660CPA: Commercial Temp., PDIP package. TC7660EOA: Extended Temp., SOIC package. TC7660EOA713: Tape and Reel, Extended Temp., SOIC package. TC7660EPA: Extended Temp., PDIP package. TC7660IJA: Industrial Temp., CERDIP package TC7660MJA: Military Temp., CERDIP package. DS21465C-page 17 TC7660 NOTES: DS21465C-page 18 2002-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. 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Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-089-5 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2002-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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