NTD4805N D

NTD4805N, NVD4805N
Power MOSFET
30 V, 88 A, Single N−Channel, DPAK/IPAK
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(on) MAX
ID MAX
5.0 mW @ 10 V
30 V
88 A
7.4 mW @ 4.5 V
D
Applications
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
N−Channel
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
S
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
17.4
A
TA = 25°C
TA = 85°C
3
TA = 25°C
PD
2.65
W
Continuous Drain
Current (RqJA) (Note 2)
TA = 25°C
ID
12.7
A
TA = 25°C
PD
1.41
W
Continuous Drain
Current (RqJC)
(Note 1)
TC = 25°C
ID
95
A
Power Dissipation
(RqJC) (Note 1)
TC = 25°C
Pulsed Drain Current
Steady
State
TA = 85°C
9.8
TC = 85°C
tp=10ms
Current Limited by Package
73
PD
79
W
TA = 25°C
IDM
175
A
TA = 25°C
IDmaxPkg
45
A
TJ, Tstg
−55 to
175
°C
IS
55
A
ISM
175
A
Operating Junction and Storage Temperature
Source Current (Body Diode)
Source Current (Body Diode) Pulsed tp=20 ms
1
1 2
13.5
Power Dissipation
(RqJA) (Note 1)
Power Dissipation
(RqJA) (Note 2)
4
Drain to Source dV/dt
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
L = 1.0 mH, IL(pk) = 24 A, RG = 25 W)
EAS
288
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
2
3
IPAK
CASE 369D
(Straight Lead DPAK)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
AYWW
48
05NG
Continuous Drain
Current (RqJA) (Note 1)
4
AYWW
48
05NG
Parameter
2
1 Drain 3
Gate Source
A
Y
WW
4805N
G
1 2 3
Gate Drain Source
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 8
1
Publication Order Number:
NTD4805N/D
NTD4805N, NVD4805N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
1.9
°C/W
Junction−to−TAB (Drain)
RqJC−TAB
3.5
Junction−to−Ambient − Steady State (Note 1)
RqJA
56.6
Junction−to−Ambient − Steady State (Note 2)
RqJA
106.6
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
27
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
"100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
gFS
1.5
5.86
VGS = 10 to
11.5 V
ID = 30 A
4.3
ID = 15 A
4.2
VGS = 4.5 V
ID = 30 A
6.0
ID = 15 A
5.8
VDS = 15 V, ID = 15 A
mV/°C
5.0
mW
7.4
17
S
2865
pF
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
338
Total Gate Charge
QG(TOT)
20.5
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
Total Gate Charge
VGS = 0 V, f = 1.0 MHz,
VDS = 12 V
VGS = 4.5 V, VDS = 15 V,
ID = 30 A
QGD
QG(TOT)
610
26
nC
4.05
8.28
8.36
VGS = 11.5 V, VDS = 15 V,
ID = 30 A
48
nC
17.2
ns
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
20.3
20.8
tf
8.0
td(on)
10.8
tr
td(off)
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
20.5
30.8
4.4
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2
ns
NTD4805N, NVD4805N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
TJ = 25°C
0.87
1.2
V
TJ = 125°C
0.76
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V,
IS = 30 A
25.7
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 30 A
ns
13.1
12.6
QRR
18
nC
Source Inductance
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK
LD
Gate Inductance
LG
3.46
Gate Resistance
RG
0.8
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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3
NTD4805N, NVD4805N
TYPICAL PERFORMANCE CURVES
180
10 V
6V
3.8 V
5V
4.5 V
90
80
3.6 V
70
60
3.4 V
50
40
30
3.2 V
20
3V
10
0
1
120
100
80
60
TJ = 125°C
40
TJ = 25°C
TJ = −55°C
0
5
1
2
4
3
5
6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.045
ID = 30 A
TJ = 25°C
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
3
4
5
6
7
8
9
10
0.01
TJ = 25°C
0.009
0.008
VGS = 4.5 V
0.007
0.006
0.005
0.004
VGS = 11.5 V
0.003
0.002
0.001
0
30 35 40
45
50 55 60
65 70 75
80
85 90
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.0
100,000
VGS = 0 V
ID = 30 A
VGS = 10 V
TJ = 175°C
10,000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
140
0
4
3
2
VDS ≥ 10 V
160
20
2.8 V
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
4V
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
110
100
1.5
1.0
0.5
−50 −25
1000
TJ = 125°C
100
10
0
25
50
75
100
125
150
175
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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4
25
NTD4805N, NVD4805N
5000
VDS = 0 V VGS = 0 V
TJ = 25°C
Ciss
4000
C, CAPACITANCE (pF)
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES
3000
Ciss
2000
Crss
1000
Coss
0
10
Crss
0
5
VGS
5
10
15
20
25
VDS
7
6
5
2
ID = 30 A
VGS = 4.5 V
TJ = 25°C
1
0
0
5
20
10
15
QG, TOTAL GATE CHARGE (nC)
25
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
30
1000
IS, SOURCE CURRENT (AMPS)
VDD = 15 V
ID = 30 A
VGS = 11.5 V
100
td(off)
tr
td(on)
10
tf
1
10
RG, GATE RESISTANCE (OHMS)
VGS = 0 V
25
100
15
10
5
100 ms
1 ms
1
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
0.7
0.8
1.0
0.9
Figure 10. Diode Forward Voltage vs. Current
1000
10
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
TJ = 25°C
20
0
0.5
1
I D, DRAIN CURRENT (AMPS)
Q2
3
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
QT
Q1
4
450
400
ID = 29 A
350
300
250
200
150
100
50
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
100
125
50
75
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTD4805N, NVD4805N
TYPICAL PERFORMANCE CURVES
I D, DRAIN CURRENT (AMPS)
100
100°C
125°C
25°C
10
1
1
100
10
PULSE WIDTH (ms)
1000
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
Figure 13. Avalanche Characteristics
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
1.0E-05
1.0E-04
t1
t2
DUTY CYCLE, D = t1/t2
1.0E-03
1.0E-02
t, TIME (s)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E-01
1.0E+00
1.0E+01
Figure 14. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD4805NT4G
DPAK
(Pb−Free)
2,500 / Tape & Reel
NTD4805N−1G
IPAK
(Pb−Free)
75 Units / Rail
NVD4805NT4G*
DPAK
(Pb−Free)
2,500 / Tape & Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable.
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6
NTD4805N, NVD4805N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
A
E
b3
c2
B
4
L3
Z
D
1
2
H
DETAIL A
3
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
L4
b2
e
c
b
0.005 (0.13)
M
C
H
L2
GAUGE
PLANE
C
L
SEATING
PLANE
A1
L1
DETAIL A
ROTATED 905 CW
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
NTD4805N, NVD4805N
PACKAGE DIMENSIONS
IPAK
CASE 369D
ISSUE C
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
3 PL
0.13 (0.005)
M
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
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For additional information, please contact your local
Sales Representative
NTD4805N/D