NTMFS4835N D

NTMFS4835N
Power MOSFET
30 V, 104 A, Single N−Channel, SO−8FL
Features
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices
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V(BR)DSS
Applications
•
•
•
•
Refer to Application Note AND8195/D
CPU Power Delivery
DC−DC Converters
Low Side Switching
RDS(ON) MAX
ID MAX
3.5 mW @ 10 V
30 V
104 A
5.0 mW @ 4.5 V
D (5,6)
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
Unit
VDSS
30
V
VGS
±20
V
ID
20
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.27
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
12
A
Power Dissipation
RqJA (Note 2)
TA = 85°C
Steady
State
G (4)
S (1,2,3)
N−CHANNEL MOSFET
14
TA = 85°C
MARKING
DIAGRAM
D
9.0
TA = 25°C
PD
0.89
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
104
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
TC = 85°C
75
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
A
Y
W
ZZ
S
S
S
G
D
4835N
AYWZZ
D
D
= Assembly Location
= Year
= Work Week
= Lot Traceability
PD
62.5
W
IDM
208
A
TJ,
TSTG
−55 to
+150
°C
IS
52
A
Drain to Source DV/DT
dV/dt
6
V/ns
Device
Package
Shipping†
Single Pulse Drain−to−Source Avalanche
Energy TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 28 Apk, L = 1.0 mH, RG = 25 W
EAS
392
mJ
NTMFS4835NT1G
SO−8FL
(Pb−Free)
1500 /
Tape & Reel
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
NTMFS4835NT3G
SO−8FL
(Pb−Free)
5000 /
Tape & Reel
Pulsed Drain
Current
TA = 25°C,
tp = 10 ms
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 7
1
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTMFS4835N/D
NTMFS4835N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
2.0
Junction−to−Ambient – Steady State (Note 3)
RqJA
55.1
Junction−to−Ambient – Steady State (Note )
RqJA
140.1
Unit
°C/W
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
22.4
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
1.5
1.9
5.3
VGS = 10 V to
11.5 V
ID = 30 A
2.9
ID = 15 A
2.5
VGS = 4.5 V
ID = 30 A
4.3
ID = 15 A
3.9
gFS
VDS = 15 V, ID = 15 A
mV/°C
3.5
5.0
21
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
3100
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VGS = 0 V, f = 1 MHz, VDS = 12 V
670
360
Total Gate Charge
QG(TOT)
22
Threshold Gate Charge
QG(TH)
4.7
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
pF
VGS = 4.5 V, VDS = 15 V; ID = 30 A
8.3
39
nC
8.8
QG(TOT)
VGS = 11.5 V, VDS = 15 V;
ID = 30 A
52
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
16
tr
td(OFF)
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
31
22
tf
13
td(ON)
10
tr
td(OFF)
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
23
30
10
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
ns
ns
NTMFS4835N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
TJ = 25°C
0.77
1.0
TJ = 125°C
0.70
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 30 A
tRR
ta
tb
27
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
V
50
15
ns
12
QRR
18
nC
Source Inductance
LS
0.65
nH
Drain Inductance
LD
0.005
nH
Gate Inductance
LG
1.84
nH
Gate Resistance
RG
PACKAGE PARASITIC VALUES
TA = 25°C
1.3
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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3
5.0
W
NTMFS4835N
TYPICAL PERFORMANCE CURVES
170
130
TJ = 25°C
110
3.5 V
90
3.2 V
70
3.0 V
50
2.8 V
30
2.6 V
0
1
3
2
4
5
6
7
8
9
10
110
90
70
TJ = 25°C
50
30
TJ = 125°C
2
1
0
TJ = −55°C
4
3
6
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
TJ = 25°C
0.025
0.020
0.015
0.010
0.005
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
130
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.030
0
VDS ≥ 10 V
150
10
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
10
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = 5.0 to 10 V
ID, DRAIN CURRENT (AMPS)
150
4.0 V
2
4
8
6
10
12
0.008
0.007
TJ = 25°C
0.006
0.005
VGS = 4.5 V
0.004
0.003
VGS = 11.5 V
0.002
0.001
0
10
15
20
25
35
30
40
45
50
55
60
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
2.0
VGS = 0 V
ID = 30 A
VGS = 10 V
10,000
1.5
IDSS, LEAKAGE (nA)
ID, DRAIN CURRENT (AMPS)
170
1.0
0.5
0
−50
TJ = 150°C
1,000
TJ = 125°C
100
10
−25
0
25
50
75
100
125
150
4
8
12
16
20
24
28
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTMFS4835N
TYPICAL PERFORMANCE CURVES
12
TJ = 25°C
Ciss
4000
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
4500
3500
2500
Crss
2000
1500
1000
Coss
500
0
15
10
5
0
5
VGS
VDS
10
15
25
20
30
VGS
8
10
6
td(off)
tr
1
td(on)
1
10
RG, GATE RESISTANCE (W)
2
0
0
5
I D, DRAIN CURRENT (AMPS)
1 ms
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0
55
VGS = 0 V
25
TJ = 25°C
20
15
10
5
0
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
0.1
50
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Figure 10. Diode Forward Voltage vs. Current
100 ms
1
15 20 25 30 35 40 45
QG, TOTAL GATE CHARGE (nC)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
2
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
100
1000
10
4
ID = 30 A
TJ = 25°C
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
6
30
tf
10
8
Qgd
Qgs
4
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
100
14
12
Figure 7. Capacitance Variation
VDS = 15 V
ID = 15 A
VGS = 11.5 V
16
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
18
10
Ciss
3000
20
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
5000
400
ID = 28 A
360
320
280
240
200
160
120
80
40
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
NTMFS4835N
TYPICAL PERFORMANCE CURVES
I D, DRAIN CURRENT (AMPS)
1000
100
25°C
10
100°C
125°C
1
1
10
1000
100
PULSE WIDTH (ms)
Figure 13. Avalanche Characteristics
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6
10000
NTMFS4835N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE G
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
2X
0.20 C
4X
E1
2
3
q
E
2
1
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
c
A1
4
TOP VIEW
C
3X
e
0.10 C
SEATING
PLANE
DETAIL A
A
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
0.10 C
SIDE VIEW
SOLDERING FOOTPRINT*
DETAIL A
3X
8X
0.10
C A B
0.05
c
4X
e/2
1
4
0.965
K
G
0.750
1.000
L
PIN 5
(EXPOSED PAD)
4X
1.270
b
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15 BSC
4.50
4.90
5.10
3.50
−−−
4.22
6.15 BSC
5.50
5.80
6.10
3.45
−−−
4.30
1.27 BSC
0.51
0.61
0.71
1.20
1.35
1.50
0.51
0.61
0.71
0.05
0.17
0.20
3.00
3.40
3.80
0_
−−−
12 _
1.330
2X
0.905
2X
E2
L1
M
0.495
4.530
3.200
0.475
D2
2X
BOTTOM VIEW
1.530
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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NTMFS4835N/D