2N6796 Data Sheet November 1998 8A, 100V, 0.180 Ohm, N-Channel Power MOSFET • 8A, 100V • rDS(ON) = 0.180Ω • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Majority Carrier Device Ordering Information 2N6796 PACKAGE TO-205AF 1594.2 Features The 2N6796 is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. PART NUMBER File Number • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” BRAND 2N6796 NOTE: When ordering, use the entire part number. Symbol D G S Packaging JEDEC TO-205AF DRAIN (CASE) SOURCE GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 321-724-7143 | Copyright © Intersil Corporation 1999 2N6796 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IS Pulse Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 2N6796 100 100 8 5 32 ±20 8 32 25 0.20 -55 to 150 UNITS V V A A A V A A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 0.25mA, VGS = 0V 100 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 0.5mA 2 - 4 V Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) VDS(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) rDS(ON) VDS = 100V, VGS = 0V - - 250 µA VDS = 80V, VGS = 0V, TC = 125oC - - 1000 µA ID = 8A, VGS = 10V - - 1.56 V VGS = ±20V - - ±100 nA ID = 5A, VGS = 10V - 0.14 0.180 Ω - - 0.350 Ω Diode Forward Voltage (Note 2) VSD ID = 5A, VGS = 10V, TC = 125oC TC = 25oC, IS = 8A, VGS = 0V 0.75 - 1.5 V Forward Transconductance (Note 2) gfs VDS = 5V, ID = 5A 3 5.5 9 S VDD ≅ 30V, ID = 5A, RG = 50Ω (Figure 17) MOSFET Switching Times are Essentially Independent of Operating Temperature - - 30 ns - - 75 ns - - 40 ns Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time tf - - 45 ns 350 600 900 pF COSS 150 300 500 pF Input Capacitance CISS Output Capacitance VDS = 25V, VGS = 0V, f = 1MHz, (Figure 11) Reverse Transfer Capacitance CRSS 50 100 150 pF Thermal Resistance Junction to Case RθJC - - 5 oC/W Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 175 oC/W Safe Operating Area SOA VDS = 80V, ID = 310mA 25 - - W VDS = 3.12V, ID = 8A 25 - - W MIN TYP MAX - 300 - ns - 1.5 - µC Source to Drain Diode Specifications PARAMETER SYMBOL Reverse Recovery Time trr Reverse Recovered Charge QRR TEST CONDITIONS TJ = 150oC, ISD = 8A, dISD/dt = 100A/µs TJ = 150oC, ISD = 8A, dISD/dt = 100A/µs NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 2 UNITS 2N6796 Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER 1.2 10 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 8 6 4 2 0 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 50 25 150 100 75 125 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZθJC, NORMALIZED THERMAL IMPEDANCE 1.0 0.5 0.2 PDM 0.1 0.1 0.05 t1 t2 0.02 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 10 1 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 35 10V 10µs 100µs 10 1ms 10ms 1 100ms -0.1 -1 TC = 25oC TJ = MAX RATED SINGLE PULSE PULSE DURATION = 80µs 30 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) OPERATION IN THIS AREA IS LIMITED BY rDS(ON) DC 9V 25 8V 20 7V 15 10 6V 5 5V 4V 0 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 1000 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 3 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. OUTPUT CHARACTERISTICS 50 2N6796 Typical Performance Curves 80µs PULSE TEST VGS = 10V 30 ID, DRAIN CURRENT (A) 35 PULSE DURATION = 80µs 30 ID, DRAIN CURRENT (A) 35 Unless Otherwise Specified (Continued) 25 9V 20 8V 15 7V 10 6V 5 5V 0 1 20 TJ = 125oC 15 TJ = 25oC TJ = -55oC 10 5 4V 0 25 4 2 3 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 6 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 0 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 2.00 NORMALIZED ON-RESISTANCE rDS(ON), ON-STATE RESISTANCE (Ω) 0.6 0.5 0.4 VGS = 10V 0.3 0.2 VGS = 20V 0.1 0 10 0 10 20 30 40 ID, DRAIN CURRENT (A) 50 VGS = 10V ID = 4A 1.75 1.50 1.25 1.00 0.75 0.50 0.25 -80 60 -40 80 120 0 40 TJ , JUNCTION TEMPERATURE (oC) 160 NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 1.10 1600 C, CAPACITANCE (pF) NORMALIZED ON-RESISTANCE 1.15 1.05 1.00 0.95 0.90 1200 800 CISS 400 COSS 0.85 0.80 -80 CRSS 0 -40 80 120 0 40 TJ , JUNCTION TEMPERATURE (oC) 160 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 4 0 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 2N6796 Typical Performance Curves 8 ISD, SOURCE TO DRAIN CURRENT (A) 80µs PULSE TEST TJ = -55oC TJ = 25oC 6 TJ = 125oC 4 2 5 2 10 5 TJ = 25oC TJ = 150oC 2 1 0 0 5 10 15 20 25 ID, DRAIN CURRENT (A) 30 35 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 0 0.5 1.0 1.5 2.0 2.5 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 ID = 18A VGS, GATE TO SOURCE (V) gfs, TRANSCONDUCTANCE (S) 10 Unless Otherwise Specified (Continued) VDS = 20V VDS = 50V VDS = 80V 15 10 5 0 0 8 16 24 Qg , TOTAL GATE CHARGE (nC) 32 FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 3.0 2N6796 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr VDS RL 90% 90% + RG - VDD 10% 10% 0 90% DUT VGS VGS 0 10% VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0.2µF 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. SWITCHING TIME TEST CIRCUIT 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G IG(REF) 0 S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS 2N6796 TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE INCHES ØD ØD1 SYMBOL P A SEATING PLANE h L Øb e e1 2 e2 1 90o 3 45o j k MIN MILLIMETERS MAX MIN MAX NOTES A 0.160 0.180 4.07 4.57 - Øb 0.016 0.021 0.41 0.53 2, 3 ØD 0.350 0.370 8.89 9.39 - ØD1 0.315 0.335 8.01 8.50 - e 0.095 0.105 2.42 2.66 4 e1 0.190 0.210 4.83 5.33 4 e2 0.095 0.105 2.42 2.66 4 h 0.010 0.020 0.26 0.50 - j 0.028 0.034 0.72 0.86 - k 0.029 0.045 0.74 1.14 - L 0.500 0.560 12.70 14.22 3 P 0.075 - 1.91 - 5 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 7 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029