Data Sheet CoreControlTM TDA21102 High speed Driver with bootstrapping for dual Power MOSFETs P-DSO-14-3 • • • • • • • • • • • Features Fast rise and fall times for frequencies up to 2 MHz Capable of sinking more than 4 A peak current for lowest switching losses Charges the High Side and Low Side MOSFET´s gate to 5..12 V according to PVCC setting. Adjustable High Side and Low Side MOSFET gate drive voltage via PVCC pin for optimizing ON losses and gate drive losses Integrates the bootstrap diode for reducing the part count Prevents from cross-conducting by adaptive gate drive control High voltage rating on Phase node Supports shut-down mode for very low quiescent current through three-state input Compatible to standard PWM controller ICs (Intersil, Analog Devices) Floating High Side MOSFET drive Ideal for multi-phase Desktop CPU supplies on motherboards and VRM´s Type TDA21102 Package P-DSO-14-3 Pinout & Description Top View PWM1 VCC PWM2 PHASE1 GND GATGATEHS1 Marking 21102 Ordering Code Q67042-S4244 Number 1 2 3 4 Name PWM1 PWM2 GND GATELS1 5 6 7 PVCC PGND GATELS2 8 PHASE2 9 GATEHS2 10 BOOT2 11 BOOT1 GATELS1 BOOT1 PVCC BOOT2 PGND GATEHS2 12 GATEHS1 GATELS2 PHASE2 13 PHASE1 14 VCC Rev. 2.0 Page 1 Description Input for the PWM1 controller signal Input for the PWM2 controller signal Ground Gate drive output for the N-Channel Low Side MOSFET 1. Input to adjust the High Side gate drive Power ground return for the Low Side Drivers Gate drive output for the N-Channel Low Side MOSFET 2. To be connected to the junction of the High Side and the Low Side MOSFET 2 Gate drive output for the N-Channel High Side MOSFET 2. Floating bootstrap pin. To be connected to the external bootstrap capacitor to generate the gate drive voltage for the High Side N-Channel MOSFET 2. Floating bootstrap pin. To be connected to the external bootstrap capacitor to generate the gate drive voltage for the High Side N-Channel MOSFET 1. Gate drive output for the N-Channel High Side MOSFET 1. To be connected to the junction of the High Side and the Low Side MOSFET 1 Supply Voltage Aug 31, 2004 CoreControlTM Data Sheet TDA21102 General Description The dual high speed driver is designed to drive a wide range of N-Channel low side and N-Channel high side MOSFETs with varying gate charges. It has a small propagation delay from input to output, short rise and fall times and the same pin configuration as the HIP6602B. In addition it provides several protection features as well as a shut down mode for efficiency reasons. The high breakdown voltage makes it suitable for mobile applications. Target application The dual high speed driver is designed to work well in half-bridge type circuits where dual N-Channel MOSFETs are utilized. A circuit designer can fully take advantage of the driver´s capabilities in highefficiency, high-density synchronous DC/DC converters that operate at high switching frequencies, e.g. in multi-phase converters for CPU supplies on motherboards and VRM´s but also in motor drive and class-D amplifier type applications. Block Diagram PVCC BOOT HS Driver GATEHS PHASE PWM Control Logic Shoot Through Protection GND VCC GATELS LS Driver PVCC BOOT Bias HS Driver GATEHS PHASE PWM Control Logic Shoot Through Protection LS Driver GATELS GND Rev. 2.0 Page 2 Aug 31, 2004 Data Sheet CoreControlTM TDA21102 Absolute Maximum Ratings At Tj = 25 °C, unless otherwise specified Parameter Symbol Voltage supplied to ‘VCC’ pin VVCC Value Min. Max. -0.3 25 Voltage supplied to ‘PVCC’ pin VPVCC -0.3 25 VPWM VBOOT – VPHASE VPHASE -0.3 -0.3 5.5 25 -1 -20 25 30 VGATEHS -3.5 Voltage supplied to ‘PWM’ pin Voltage supplied to ‘BOOT’ pin referenced to ‘PHASE’ Voltage rating at ‘PHASE’ pin, DC Voltage rating at ‘PHASE’ pin, tpulse_max =500ns Max Duty Cycle = 2% Voltage supplied to GATEHS pin referenced to ‘PHASE’ Tpulse_max < 100ns, E < 2uJ Voltage supplied to GATELS pin referenced to ‘GND’ Tpulse_max < 100ns, E < 2uJ Junction temperature Storage temperature ESD Rating; Human Body Model IEC climatic category; DIN EN 60068-1 VGATELS TJ TS VBOOT +0.3 -5 VVCC +0.3 -25 150 -55 150 4 55/150/56 Unit V °C kV - Thermal Characteristic Parameter Symbol Thermal resistance, junction-solder joint ( pin 4 ) Thermal resistance, junction-case Thermal resistance, junction-ambient Rev. 2.0 Page 3 Rth-JS Rth-JC Rth-JA Values Unit Min. Typ. Max. 40.5 44.7 116.2 K/W Aug 31, 2004 Data Sheet CoreControlTM TDA21102 Electrical Characteristic At Tj = 25 °C, unless otherwise specified Parameter Symbol Conditions Supply Characteristic Bias supply current IVCC f = 1 MHz, NO LOAD VPVCC = VVCC = 12 V 1.8 V ≤ VPWM ≤ 3.0 V f = 1 MHz, NO LOAD VPVCC = VVCC = 12 V VVCC rising threshold VVCC falling threshold 9.7 7.3 10.1 10.5 7.6 8.0 V V V_PWM = 0.4 V V_PWM = 4.5 V t_SHUT > 350 ns 1.7 V ≤ VPWM ≤ 3.1 V -80 120 1.7 100 115 180 µA VPWM_O VPWM_L 1.8 2.0 VPWM_H 3.7 Quiescent current Power supply current Under-voltage lockout Under-voltage lockout Input Characteristic Current in ‘PWM’ pin Current in ‘PWM’ pin Shut down window Shut down hold-off time PWM pin open PWM Low level threshold (falling) PWM High level threshold (rising) Pulse Width High Side IVCCQ IPVCC IPWM_L IPWM_H VIN_SHUT t_SHUT t_p = Pulse with on PWM pin At Tj = 25 °C, unless otherwise specified Dynamic Characteristic Turn-on propagation td(ON)_HS Delay High Side* Turn-off propagation td(OFF)_HS delay High Side Rise time High Side tr_HS PPVCC = VVCC= 12 V Fall time High Side tf_HS CISS = 3000 pF Turn-on propagation td(ON)_LS Delay Low Side Turn-off propagation td(OFF)_LS delay Low Side Rise time Low Side tr_LS Fall time Low Side tf_LS Rev. 2.0 Page 4 Values Unit Min. Typ. Max. 1.3 1.8 3.8 4.9 25 33 200 -150 250 3.1 320 2.2 1.4 40 mA V ns V ns 18 35 18 25 14 14 17 28 22 23 14 20 22 14 29 22 ns Aug 31, 2004 Data Sheet CoreControlTM TDA21102 At Tj = 125 °C, unless otherwise specified Dynamic Characteristic Turn-on propagation td(ON)_HS Delay High Side* Turn-off propagation td(OFF)_HS delay High Side Rise time High Side tr_HS PPVCC = VVCC= 12 V Fall time High Side tf_HS CISS = 3000 pF Turn-on propagation td(ON)_LS Delay Low Side Turn-off propagation td(OFF)_LS delay Low Side Rise time Low Side tr_LS Fall time Low Side tf_LS 22 22 16 16 20 ns 18 23 16 Measurement Timing diagram PWM @ 50% PWM @ 50% Td(ON)_HS Td(Off)_HS GATEHS @ 90% GATEHS @ 10% Td(Off)_LS GATEHS Tf_HS Tr_HS PHASE @ 2V Td(On)_LS PHASE GATELS @ 90% GATELS @ 2V GATELS @ 10% Tf_LS Rev. 2.0 GATELS Tr_LS Page 5 Aug 31, 2004 Data Sheet CoreControlTM TDA21102 Operating Conditions At Tj = 25 °C, unless otherwise specified Parameter Voltage supplied to ‘VCC’ pin Voltage supplied to ‘PVCC’ pin Input signal transition frequency Power dissipation Junction temperature Symbol Conditions VVCC Values Unit Min. Typ. Max. 10.8 13.2 V VPVCC 5 13.2 V f 0.1 2 MHz 150 W °C PTOT TJ TA = 25 °C, TJ = 125 °C 0.9 -25 At Tj = 25 °C, unless otherwise specified Parameter Values Unit Min. Typ. Max. Output Characteristic High Side (HS) and Low Side (LS), ensured by design Output HS; Source PPVCC = VVCC= 12 V I_HS_SRC 1(1) Ω Resistance =2A HS; Sink VVCC= 12 V , PPVCC = 5V 1 1.3 Ω HS; Sink PPVCC = VVCC= 12 V 0.9 1.2 Ω (2) LS; Source PPVCC = VVCC= 12 V I_HS_SRC 1.4 Ω =2A LS; Sink VVCC= 12 V , PPVCC = 5V 1 1.3 Ω LS; Sink PPVCC = VVCC= 12 V 1 1.25 Ω HS; Source PPVCC = VVCC= 12 V 4 A Peak outputt_P_HS / Pulse < 20 ns HS; Sink 4 t_P_LS / Pulse < 40 ns current LS; Source 4 < 2%, D < 4% D _HS _LS 4 LS; Sink 1 2 Conditions Incremental resistance VBOOT-VHS=4.3V @ ISOURCE=2A Incremental resistance VVCC –VLS=4.4V @ ISOURCE=2A Rev. 2.0 Page 6 Aug 31, 2004 Data Sheet CoreControlTM TDA21102 Package Drawing P-DSO-14-3 Layout Footprints e 1,27 mm Rev. 2.0 A 5,69 mm L 1,31 mm Page 7 B 0,65 mm Aug 31, 2004 CoreControlTM Data Sheet TDA21102 Published by Infineon Technologies AG, Bereichs Kommunikation St.-Martin-Strasse 53, D-81541 München Infineon Technologies AG 1999 All Rights Reserved. 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Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 2.0 Page 8 Aug 31, 2004