Data Sheet No. PD60251 IRS2112(-1,-2,S)PbF HIGH AND LOW SIDE DRIVER Features • • • • • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 3.3 V logic compatible Separate logic supply range from 3.3 V to 20 V Logic and power ground +/- 5 V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in phase with inputs RoHS compliant Description Product Summary VOFFSET 600 V max. IO+/- 200 mA / 440 mA VOUT 10 V - 20 V ton/off (typ.) 135 ns & 105 ns Delay Matching 30 ns Packages 14-Lead PDIP IRS2112 16-Lead PDIP (w/o leads 4 & 5) IRS2112-2 The IRS2112 is a high voltage, high speed power MOSFET and IGBT driver with independent high- and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable rug14-Lead PDIP gedized monolithic construction. Logic inputs are com(w/o lead 4) patible with standard CMOS or LSTTL outputs, down IRS2112-1 to 3.3 V logic. The output drivers feature a high pulse 16-Lead SOIC current buffer stage designed for minimum driver IRS2112S cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V. up to 600 V Typical Connection HO V DD VDD VB HIN HIN VS SD SD LIN LIN VCC V SS VSS COM V CC TO LOAD LO (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IRS2112(-1,-2,S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figs. 28 through 35. Symbol Definition VB High-side floating supply voltage VS Min. Max. -0.3 625 High-side floating supply offset voltage VB - 25 VB + 0.3 VHO High-side floating output voltage VS - 0.3 VB + 0.3 VCC Low-side fixed supply voltage -0.3 25 VLO Low- side output voltage -0.3 VCC + 0.3 VDD Logic supply voltage -0.3 VSS + 25 VSS Logic supply offset voltage VCC - 25 VCC + 0.3 Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3 — 50 VIN dVs/dt PD RTHJA Allowable offset supply voltage transient (Fig. 2) Package power dissipation @ TA ≤ +25 °C Thermal resistance, junction to ambient (14 Lead DIP) — 1.6 (16 Lead SOIC) — 1.25 (14 Lead DIP) — 75 (16 Lead SOIC) — 100 TJ Junction temperature — 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 Units V V/ns W °C/W °C Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential. Typical ratings at other bias conditions are shown in Figs. 36 and 37. Symbol Definition Min. Max. VB High-side floating supply absolute voltage VS + 10 VS + 20 VS High-side floating supply offset voltage Note 1 600 VB VHO High-side floating output voltage VS VCC Low-side fixed supply voltage 10 20 VLO Low- side output voltage 0 VCC VDD Logic supply voltage VSS Logic supply offset voltage VIN TA VSS + 3 VSS + 20 -5 (Note 2) 5 Logic input voltage (HIN, LIN & SD) VSS VDD Ambient temperature -40 125 Units V °C Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details). Note 2: When VDD < 5 V, the minimum VSS offset is limited to -VDD. www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 2 IRS2112(-1,-2,S)PbF Dynamic Electrical Characteristics VBIAS (VCC , VBS, VDD ) = 15 V, CL = 1000 pF, TA = 25 °C and VSS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Fig. 3. Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay — 135 180 toff Turn-off propagation delay — 130 160 tsd Shutdown propagation delay — 130 160 tr Turn-on rise time — 75 130 tf Turn-off fall time — 35 65 Delay matching, HS & LS Turn-on/off — — 30 MT VS = 0 V VS = 600 V ns Static Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15 V, TA = 25 °C and VSS = COM unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are applicable to all three logic input leads: HIN, LIN, and SD. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol VIH Definition Min. Typ. Max. Units Test Conditions Logic “1” input voltage 9.5 — — VIL Logic “0” input voltage — — 6.0 VOH High level output voltage, VBIAS - VO — 0.05 0.2 VOL Low level output voltage, VO — 0.02 0.1 V IO = 2 mA ILK Offset supply leakage current — — 50 IQBS Quiescent VBS supply current — 25 100 IQCC Quiescent VCC supply current — 80 180 IQDD Quiescent VDD supply current — 2.0 30 IIN+ Logic “1” input bias current — 20 40 VIN = VDD IIN- Logic “0” input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold — — 1.0 VIN = 0 V 7.4 8.5 9.6 7.0 8.1 9.2 7.6 8.6 9.6 7.2 8.2 9.2 VBSUV+ VBSUVVCCUV+ VCCUV- VB = VS = 600 V VIN = 0 V or VDD µA V IO+ Output high short circuit pulsed current 200 290 — IO- Output low short circuit pulsed current 420 600 — mA www.irf.com PDF created with pdfFactory trial version www.pdffactory.com VO = 0 V, VIN = VDD PW ≤ 10 µs VO = 15 V, VIN = 0 V PW ≤ 10 µs 3 IRS2112(-1,-2,S)PbF Functional Block Diagram VB UV DETECT VDD R Q S HIN HV LEVEL SHIFT VDD /VCC LEVEL SHIFT PULSE FILTER PULSE GEN R R Q HO S VS SD VCC LIN S VDD /VCC LEVEL SHIFT R Q UV DETECT LO DELAY COM VSS Lead Definitions Symbol Description VDD Logic supply HIN SD LIN VSS VB HO VS VCC LO COM Logic input for high-side gate driver output (HO), in phase Logic input for shutdown Logic input for low-side gate driver output (LO), in phase Logic ground High-side floating supply High-side gate drive output High-side floating supply return Low-side supply Low-side gate drive output Low-side return www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 4 IRS2112(-1,-2,S)PbF Lead Assignments 14 Lead PDIP 16 Lead SOIC (Wide Body) IRS2112 IRS2112S 16 Lead PDIP w/o leads 4 & 5 14 Lead PDIP w/o lead 4 IRS2112-2 IRS2112-1 Part Number www.irf.com 5 IRS2112(-1,-2,S)PbF VCC = 15 V HV = 10 V to 600 V 10 k F6 10 µF HIN LIN 0.1 µF 9 3 200 µH 0.1 µF 6 100 µF 10 k F6 5 10 SD 7 HO 11 dVs 1 10 k F6 12 ct OUTPUT MONITOR HO LO 13 2 IRF820 Figure 1. Input/Output Timing Diagram VCC = 15 V HV = 10 V to 600 V 0.1 µF 10 µF 9 Figure 2. Floating Supply Voltage Transient Test Circuit 3 0.1 µF 6 + 10 µF 7 - VS (0 V to 600 V) CL HO 11 1 SD 12 ton 10 µF 50% toff tr 90% tf 90% LO LIN HO LO CL 13 50% HIN LIN 15 V 5 10 HIN VB 2 Figure 3. Switching Time Test Circuit 10% 10% Figure 4. Switching Time Waveform Definition HIN LIN 50% 50% 50% SD LO HO tsd HO LO 10% 90% MT MT 90% LO Figure 5. Shutdown Waveform Definitions HO Figure 6. Delay Matching Waveform Definitions www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 6 250 200 M ax. 150 100 250 Tu rn- On Delay Tim e ( ns ) . Tu rn- On Delay Tim e ( ns) . IRS2112(-1,-2,S)PbF Typ. 50 M ax 200 150 T yp. 100 50 0 0 -50 -25 0 25 50 75 100 10 125 12 Figure 7A. Turn-On Propagation Delay Time vs. Temperature 400 18 20 250 M ax. 300 200 Typ. 100 200 150 0 2 4 6 8 10 12 14 16 M ax. 100 Typ . 50 0 - 50 0 18 20 -25 0 25 50 75 100 125 Temperature(oC) V DD Supply V oltage (V ) Figure 8A. Turn-Off Propagation Delay Time vs. Temperature Figure 7C. Turn-On Propagation Delay Time vs. VDD Supply Voltage 250 400 Tur n-O ff Delay Tim e ( ns ) Tu rn- O ff T im e (ns ) 16 Figure 7B. Turn-On Propagation Delay Time vs. VCC/VBS Supply Voltage Turn- Off Time (ns ) Tur n-O n Delay Tim e ( ns) . 14 V CC / V BS Supply V oltage (V ) Temperature(oC) M ax. 200 150 Typ. 100 50 M ax . 300 200 T yp. 100 0 0 10 12 14 16 18 20 0 4 6 8 10 12 14 16 18 20 V DD Supply V oltage (V ) V CC/V BS Supply V oltage (V ) Figure 8B. Turn-Off Propagation Delay Time vs. VCC/VBS Supply Voltage 2 Figure 8C. Turn-Off Propagation Delay Time vs. VDD Supply Voltage www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 7 IRS2112(-1,-2,S)PbF 250 Sh utd ow n D ela y T ime ( n s ) Shutdow n D elay Time (ns) 250 200 150 M ax. 100 Typ . 50 0 - 50 M ax. 200 150 Typ. 100 50 0 -25 0 25 50 75 100 125 10 12 Temperature(oC) 18 20 Figure 9B. Shutdown Delay Time vs. VCC/VBS Supply Voltage 400 Tur n-O n Ris e T ime (ns) . 250 M ax . 300 200 T yp. 100 0 200 150 M ax. 100 50 T yp. 0 0 2 4 6 8 10 12 14 16 18 20 -5 0 -25 0 V DD Supply V oltage (V ) 25 50 75 100 125 o Temperature ( C) Figure 9C. Shutdown Time vs. VDD Supply Voltage Figure 10A. Turn-On Rise Time vs. Temperature 125 Tur n- O ff Fal l T im e ( ns ) 250 Tur n-O n Ris e Time (ns) . 16 V C C /V BS Supply V oltage (V ) Figure 9A. Shutdown Delay Time vs. Temperature Shutdown De lay Time (ns ) 14 200 M ax 150 100 Typ 50 0 10 12 14 16 18 20 100 75 M ax. 50 25 0 -50 -25 0 25 50 75 100 125 o Temper ature ( C) V BIAS Supply V oltage (V ) Figure 10B. Turn-On Rise Time vs. Voltage Typ. Figure 11A. Turn-Off Fall Time vs. Temperature www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 8 IRS2112(-1,-2,S)PbF 15 Logic "1" Input Threshold (V) Tur n- O ff Fal l Tim e ( ns) 125 100 M ax 75 50 Typ 25 0 10 12 14 16 18 20 12 Min. 9 6 3 0 -50 -25 0 V BIAS Supply Voltage (V ) 75 100 125 15 Figure 12A. Logic “I” Input Threshold vs. Temperature 9 12 Logic "0" Input Threshold (V) 15 3 6 Min. 0 Logic " 1 " Input Treshold (V) 50 Temperature (°C) Figure 11B. Turn-Off Fall Time vs. Supply Voltage 12 9 Max. 6 3 0 2.5 5 7.5 10 V DD Logic 12.5 15 17.5 20 -5 0 7.5 10 12.5 15 17.5 20 50 75 100 125 1.0 0.8 0.6 0.4 M ax. 0.2 0.0 -50 V DD Logic Supply Voltage (V) Figure 13B. Logic “0” Input Threshold vs. Voltage 25 Figure 13A. Logic “0” Input Threshold vs. Temperature High Lev el O utput Voltag e ( V) 15 12 9 6 3 0 5 0 Supply Voltage (V) Max. 2.5 -2 5 Temperature (°C) Figure 12B. Logic “I” Input Threshold vs. Voltage Logic " 0 " Input Treshold (V) 25 - 25 0 25 50 75 100 125 Temperature ( oC) Figure 14A. High Level Output Voltage vs. Temperature (Io = 2 mA) www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 9 IRS2112(-1,-2,S)PbF Low L ev el O utput Vo ltage ( V) Hig h Level O utput Voltage (V) 1.0 0.8 0.6 0.4 M ax 0.2 0.0 10 12 14 16 18 20 1.0 0.8 0.6 0.4 0.2 M ax 0.0 -50 -25 0 75 100 125 Temperature ( C) Figure 14B. High Level Output Voltage vs. Supply Voltage (Io = 2 mA) Figure 15A. Low Level Output Voltage vs. Temperature (Io = 2 mA) 200 1.0 VBS Supply Current (µA) Low Level Output Voltage (V) 50 o V BAIS Supply V oltage (V ) 0.8 0.6 0.4 0.2 M ax 0.0 150 100 M ax. 50 Typ. 0 10 12 14 16 18 20 -50 -25 0 V BAIS Supply Volt age (V) 25 50 75 100 125 o Temperature ( C) Figure 15B. Low Level Output Voltage vs. Supply Voltage (Io = 2 mA) Figure 16A. VBS Supply Current vs. Temperatur e 200 100 VBS Supply Current (µA) VBS Supply Current (µA) 25 150 100 M ax. 50 Typ. 80 60 Max. 40 20 Typ. 0 0 10 12 14 16 18 V BS Supply Voltage (V) Figure 16B. V BS Supply Current vs. Voltage www.irf.com 20 -50 -25 0 25 50 75 100 125 Tem perature (°C ) Figure 17A. VBS Supply Current vs. Temperature 10 IRS2112(-1,-2,S)PbF 300 VCC Supply Current (µA) VBS Supply Current (µA) 100 80 M ax. 60 40 Ty p. 20 250 200 150 Max. 100 50 0 Typ. 0 10 12 14 16 18 20 -5 0 -2 5 0 V B S Floating S upply Voltage (V ) 12 250 10 VDD Supply Current (µA) Vcc Supply Current (µA) 300 Max. 150 100 Typ. 50 10 100 125 Max. 8 6 Typ. 4 2 12 14 16 18 20 -50 -25 0 Logic "1 " Input Bias Current (µA) 12 10 8 Max. 4 2 Typ. 0 2 4 6 8 10 12 14 16 50 75 100 125 Figure 19A. VDD Supply Current vs. Temperature Figure 18B. VCC Supply Current vs. Voltage 6 25 Temperature (°C) V cc Fixed Supply Voltage (V) V DD S u p p ly C u rre n t (µA) 75 0 0 0 50 Figure 18A. VCC Supply Current vs. Temperature Figure 17B. VBS Supply Current vs. Voltage 200 25 Temperature (°C) 18 100 20 60 Max. 40 20 Typ. 0 -50 VDD Logic Supply Voltage (V) Figure 19B. VDD Supply Current vs. VDD Voltage 80 -25 0 25 50 75 100 125 Temperature (°C) Figure 20A. Logic “I” Input Current vs. Temperature www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 11 100 80 60 Max. 40 20 Typ. 0 0 2 4 6 8 10 12 14 16 18 VDD Logic Supply Voltage (V) 20 6 Logic "0" Input Bias Current (µA) Logic "1" Input Bias Current (uA) IRS2112(-1,-2,S)PbF 5 Max 4 3 2 1 0 -50 -25 0 25 50 75 100 125 Temperature (°C) Figure 20B. Logic “1” Input Current vs. V DD Voltage Figure 21A. Logic "0" Input Bias Current 5 VBS Undervoltage Lockout +(V) Logic "0" Input Bias Current (µA) vs. Temperature 6 Max 4 3 2 1 0 10 12 14 16 18 20 11 10 Max. 9 Typ. 8 Min. 7 6 -50 -25 Supply Voltage (V) 0 25 50 75 100 125 Temperature (°C) Figure 22. VBS Undervoltage (+) vs. Temperature Figure 21B. Logic "0" Input Bias Current vs. Voltage 11 10 Max. 9 Typ. 8 Min. 7 6 -50 -25 0 25 50 75 100 125 Temperature (°C) Figure 23. VBS Undervoltage (-) vs. Temperature www.irf.com VCC Undervoltage Lockout +(V) VBS Undervoltage Lockout -(V) 11 10 Max. 9 Typ. 8 Min. 7 6 -50 -25 0 25 50 75 100 125 Temperature (oC ) Figure 24. VCC Undervoltage (-) vs. Temperature 12 VCC Undervoltage Lockout - (V) IRS2112(-1,-2,S)PbF Ou tpu t S our c e Cu r r e nt ( mA ) 11 10 Max. 9 Typ. 8 Min. 7 500 400 T yp. 300 200 100 0 6 -50 -25 0 25 50 75 100 M in. - 50 125 - 25 0 Temperature (°C) 75 100 125 Temperature ( C) Figure 26A. Output Source Current vs. Temperature 500 750 Ou tpu t S ink Cu rre nt ( mA ) O u tp u t So u r c e C u r r e n t ( m A ) 50 o Figure 25. VCC Undervoltage (-) vs. Temperature 400 300 200 25 Typ . 100 M in. T yp. 600 M in. 450 300 150 0 0 10 12 14 16 18 20 - 50 - 25 0 25 50 75 100 12 5 Temperatu re ( oC) V BIA S Supply Voltage ( V) Figure 27A. Output Sink Current vs. Temperature Figure 26B. Output Source Current vs. Supply Voltage Ou tpu t Sink Cur ren t (m A ) 750 600 450 Typ. 300 M in. 150 0 10 12 14 16 18 20 V BIA S Supply V oltage (V ) Figure 27B. Output Sink Current vs. Supply Voltage www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 13 IRS2112(-1,-2,S)PbF 150 125 320 V 100 75 140 V 10 V 50 Junction Temperature (°C) Junction Temperature (°C) 150 25 125 140 V 100 75 10 V 50 25 0 1E+2 320 V 0 1E+3 1E+4 1E+5 1E+6 1E+2 1E+3 Frequency (Hz) Figure 28. IRS2112 TJ vs. Frequency (IRFBC20) RGATE = 33 Ω , VCC = 15 V 1E+6 125 140 V 100 320 V 140 V 10 V 150 10 V 75 50 Junction Temperature (°C) Junction Temperature (°C) 1E+5 Figure 29. IRS2112 TJ vs. Frequency (IRFBC30) RGATE = 22 Ω , VCC = 15 V 320 V 150 25 125 100 75 50 25 0 0 1E+2 1E+3 1E+4 1E+5 1E+6 1E+2 1E+3 Frequency (Hz) 150 1E+5 1E+6 Figure 31. IRS2112 TJ vs. Frequency (IRFPE50) RGATE = 10 Ω , VCC = 15 V 140 V 75 10 V 50 25 Junction Temperature (°C) 100 320 V 150 320 V 125 140 V 125 100 75 10 V 50 25 0 1E+2 1E+4 Frequency (Hz) Figure 30. IRS2112 TJ vs. Frequency (IRFBC40) RGATE = 15 Ω , VCC = 15 V Junction Temperature (°C) 1E+4 Frequency (Hz) 0 1E+3 1E+4 1E+5 1E+6 1E+2 Frequency (Hz) Figure 32. IRS2112S TJ vs. Frequency (IRFBC20) RGATE = 33 Ω , VCC = 15 V 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) Figure 33. IRS2112S TJ vs. Frequency (IRFBC30) RGATE = 22 Ω , VCC = 15 V www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 14 IRS2112(-1,-2,S)PbF 320 V 150 320 V 140 V 10 V 150 10 V 125 100 75 50 Junction Temperature (°C) Junction Temperature (°C) 140 V 25 125 100 75 50 25 0 0 1E+2 1E+3 1E+4 1E+5 1E+6 1E+2 1E+3 Frequency (Hz) Figure 34. IRS2112S TJ vs. Frequency (IRFBC40) RGATE = 15 Ω , VCC = 15 V 1E+5 1E+6 Figure 35. IRS2112S TJ vs. Frequency (IRFPE50) RGATE = 10 Ω , VCC = 15 V 20.0 VSS Logic Supply Offset Voltage (V) 0.0 VS Offset Supply Voltage (V) 1E+4 Frequency (Hz) -3.0 Typ. -6.0 -9.0 -12.0 -15.0 16.0 12.0 8.0 Typ. 4.0 0.0 10 12 14 16 18 20 10 VBS Floating Supply Voltage (V) Figure 36. Maximum VS Negative Offset vs. VBS Supply Voltage 12 14 16 18 20 VCC Fixed Supply Voltage (V) Figure 37. Maximum VSS Positive Offset vs. VCC Supply Voltage www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 15 IRS2112(-1,-2,S)PbF Case outline 14-Lead PDIP 01-6010 01-3002 03 (MS-001AC) 14-Lead PDIP w/o Lead 4 01-6010 01-3008 02 (MS-001AC) www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 16 IRS2112(-1,-2,S)PbF 16 Lead PDIP w/o Leads 4 & 5 16-Lead SOIC (wide body) www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 01-6015 01-3010 02 01 6015 01-3014 03 (MS-013AA) 17 IRS2112(-1,-2,S)PbF Tape & Reel 16-Lead SOIC LOAD ED TA PE FEED DIRECTION A B H D F C N OT E : CO NTROLLING D IMENSION IN MM E G C A R R I E R T A P E D IM E N S I O N F O R 1 6 S O IC W M etr ic Im p eria l Code M in M ax M in M ax A 1 1 .9 0 1 2. 1 0 0. 4 6 8 0 .4 76 B 3 .9 0 4.1 0 0. 1 5 3 0 .1 61 C 1 5 .7 0 1 6. 3 0 0. 6 1 8 0 .6 41 D 7 .4 0 7.6 0 0. 2 9 1 0 .2 99 E 1 0 .8 0 1 1. 0 0 0. 4 2 5 0 .4 33 F 1 0 .6 0 1 0. 8 0 0. 4 1 7 0 .4 25 G 1 .5 0 n/ a 0. 0 5 9 n/ a H 1 .5 0 1.6 0 0. 0 5 9 0 .0 62 F D C B A E G H R E E L D IM E N S I O N S F O R 1 6 SO IC W M etr ic Im p eria l Code M in M ax M in M ax A 32 9. 60 3 30 .2 5 1 2 .9 76 1 3 .0 0 1 B 2 0 .9 5 2 1. 4 5 0. 8 2 4 0 .8 44 C 1 2 .8 0 1 3. 2 0 0. 5 0 3 0 .5 19 D 1 .9 5 2.4 5 0. 7 6 7 0 .0 96 E 9 8 .0 0 1 02 .0 0 3. 8 5 8 4 .0 15 F n /a 2 2. 4 0 n /a 0 .8 81 G 1 8 .5 0 2 1. 1 0 0. 7 2 8 0 .8 30 H 1 6 .4 0 1 8. 4 0 0. 6 4 5 0 .7 24 www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 18 IRS2112(-1,-2,S)PbF LEADFREE PART MARKING INFORMATION Part number Date code IRSxxxx YWW? ?XXXX Pin 1 Identifier ? P IR logo Lot Code (Prod mode - 4 digit SPN code) MARKING CODE Lead Free Released Non-Lead Free Released Assembly site code Per SCOP 200-002 ORDER INFORMATION 14-Lead PDIP IRS2112PbF 14-Lead PDIP IRS2112-1PbF 16-Lead PDIP IRS2112-2PbF 16-Lead SOIC IRS2112SPbF 16-Lead SOIC Tape & Reel IRS2112STRPbF The SOIC-16 is MSL3 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 11/27/2006 www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 19