FINAL PRODUCT/PROCESS CHANGE NOTIFICATION Generic Copy 24 Apr 2009 SUBJECT: ON Semiconductor Final Product/Process Change Notification #16251 TITLE: NCP3420 Gresham Fab Qualification and Copper Wire Qualification Notice PROPOSED FIRST SHIP DATE: 24 Jul 2009 AFFECTED PRODUCT DIVISION(S): CCPG FOR ANY QUESTIONS CONCERNING THIS NOTIFICATION: Contact your local ON Semiconductor Sales Office or David Chu <[email protected]> SAMPLES: Contact your local ON Semiconductor Sales Office ADDITIONAL RELIABILITY DATA: Available Contact your local ON Semiconductor Sales Office or Nicky Siu <[email protected]> NOTIFICATION TYPE: Final Product/Process Change Notification (FPCN) Final change notification sent to customers. FPCNs are issued at least 90 days prior to implementation of the change. ON Semiconductor will consider this change approved unless specific conditions of acceptance are provided in writing within 30 days of receipt of this notice. To do so, contact your local ON Semiconductor Sales Office. DESCRIPTION AND PURPOSE: ON Semiconductor has qualified the NCP3420DR2G on a second fab process, Gresham ONBCD25. The products affected will be dual sourced from both TSMC and Gresham wafer fabs. ON Semiconductor has qualified the use of copper wire on the NCP3420DR2G. The wirebonding for the affected device will be dual sourced and will use either gold or copper wire until gold wire inventory is depleted. Due to the process change noted above, there have been changes to the electrical characteristics of the affected device. These changes are not expected to adversely affect the customer’s application or the device’s performance. See the electrical characteristics summary below for specific details about these changes. Issue Date: 24 Apr 2009 Rev.14 Jun 2007 Page 1 of 4 Final Product/Process Change Notification # 16251 RELIABILITY DATA SUMMARY: Gresham Qualification Plan 1. High Temp Op Life (125 °C Tj, Dynamic) 3 lots/vehicle Demonstrate ≤1000 FIT 2. High Temp Storage (150 °C)3 lots/vehicle X 80 units/lot 504, 1008 hrs. 3. Pre-Conditioning MSL 3 lots/vehicle X 240 units/lot 4. HAST (130 °C/85%RH) 3 lots/vehicle X 80 units/lot 96 hrs. 5. Autoclave (121 °C/100%RH/15PSIG)3 lots/vehicle X 80 units/lot 96 hrs. 6. Temp Cycling (-65 °C to +150 °C)3 lots/vehicle X 80 units/lot 500, 1000 cycles 7. External Visual Inspection All Units 8. Wire Bond Pull Strength 3 lots 9. Bond Shear Test 3 lots 10. ESD - Human Body Model 3 lots 11. ESD - Machine Model 3 lots 12. Latch-Up 3 lots 13. Characterization: A minimum of 30 packaged units from each of the three qualification lots are to be characterized across the full temperature range of the device as documented in the datasheet Copper Wire Qualification Plan # TEST 1 Prep Initial Electric al 2 NAME Sample preparation and intial part testing Intitial Electrical Prior To PC 3 HTOL High Temp Op Life 4 PC Preconditioning MSL 1 5 HAST+ PC Highly Accelerated Stress Test 6 TC+PC Temp Cycling+ preconditioning 7 AC+PC Autoclave+preco nditioning Issue Date: 24 Apr 2009 TEST CONDITIONS END POINT REQUIREMENTS SS x No. Lots various --- all --- ---- ALL Ta=125°C for 1008hrs (JA108) J STD 020A , JA 113 IR reflow at 260°C, HAST, TC, AC Temp = +130°C; RH = 85%, psig ~28 with bias** for 96hrs (JA110) Temp = -65°C to +150°C; for 500 cycles (JA104B) 121°C/100% RH/15 PSIG for 96 hrs (JA102) Rev.14 Jun 2007 RESULTS c = 0, Room 80 x 3 lots 0/240 c = 0, Room 240 x 3 lots 0/720 c = 0, Room 80 x 3 lots 0/240 c = 0, Room 80 x 3 lots 0/240 c = 0, Room 80 x 3 lots 0/240 Page 2 of 4 Final Product/Process Change Notification # 16251 8 HTSL High Temp Storage Life 9 RSH Resistance to Solder Heat 10 DPA 11 ED DeProcessing Analysis Tri-Temp Electrical Characterization 12 TR 13 Yield Thermal Resistance Wirebond Related Yield Analysis 14 BPS Bond Pull Strength 15 BS Bond Shear Ta=150°C for 1008hrs (JA103) TS=260C, Tdwell=10 sec. Test after RSH. SMD devices are fully submerged during test. (JESD22 B106) Post HAST+PC, post TC+PC, and post AC+PC Characterizatio n of all parameters Provide thermal comparison data to ensure spec compliance per assembly MRB procedure M2011 Condition C or D AEC-Q100001 c = 0, Room 80 x 3 lots 0/240 N/A 30 x 3 lots 0/90 2 x 3 lots PASS 30 units x 3 lots PASS 10 units x 1 eval lot + 1 cont lot PASS All units x 3 lots PASS 30 bonds on min. 5 units 30 x 3 lots 0/90 30 bonds on min. 5 units 30 x 3 lots 0/90 Room, Hot, Cold Reliability Test Results: Available Upon Request Issue Date: 24 Apr 2009 Rev.14 Jun 2007 Page 3 of 4 Final Product/Process Change Notification # 16251 ELECTRICAL CHARACTERISTIC SUMMARY: Due to the process change noted above, the following electrical characteristics have changed. These changes will be reflected in the NCP3420 datasheet. All other electrical parameters will remain the same. Parameter Old Lower Limit Output Resistance, Unbiased SW Pulldown Resistance Propogation Delay, tpdlODb Propogation Delay, tpdhODb Old Typical Limit Old Upper Limit Revised Lower Limit Revised Typical Limit Revised Upper Limit 15 kOhms 10 kOhms 55 kOhms 15 kOhms 10 kOhms 55 kOhms 10ns 25ns 45ns 1ns 25ns 45ns 10ns 25ns 45ns 1ns 25ns 45ns AFFECTED DEVICE LIST NCP3420DR2G Issue Date: 24 Apr 2009 Rev.14 Jun 2007 Page 4 of 4