CY7C1480BV25
72-Mbit (2M × 36) Pipelined Sync SRAM
72-Mbit (2M × 36) Pipelined Sync SRAM
Features
Functional Description
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
2.5 V core power supply
■
2.5 V I/O operation
■
Fast clock-to-output time
❐ 3.0 ns (for 250 MHz device)
■
Provide high performance 3-1-1-1 access rate
■
User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed writes
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1480BV25 available in JEDEC-standard Pb-free 100-pin
thin quad flat pack (TQFP), Pb-free and non Pb-free 165-ball
fine-pitch ball grid array (FBGA) package.
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
“ZZ” sleep mode option
The CY7C1480BV25 SRAM integrates 2M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
can be internally generated as controlled by the Advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed Write cycle. This part supports Byte Write
operations (see Pin Definitions on page 6 and Truth Table on
page 9 for further details). Write cycles can be one to two or four
bytes wide, as controlled by the byte write control inputs. When
it is active LOW, GW writes all bytes.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum access time
250 MHz
200 MHz
167 MHz
Unit
3.0
3.0
3.4
ns
Maximum operating current
450
450
400
mA
Maximum complementary metal oxide semiconductor (CMOS) standby current
120
120
120
mA
Cypress Semiconductor Corporation
Document Number: 001-15143 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 13, 2016
CY7C1480BV25
Logic Block Diagram – CY7C1480BV25
A 0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BW D
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ D ,DQPD
BYTE
WRITE DRIVER
BW C
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
ZZ
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
DQ A ,DQP A
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE REGISTER
GW
CE 1
CE 2
CE 3
OE
MEMORY
ARRAY
PIPELINED
ENABLE
INPUT
REGISTERS
SLEEP
CONTROL
Document Number: 001-15143 Rev. *N
Page 2 of 33
CY7C1480BV25
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 16
Document Number: 001-15143 Rev. *N
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC®Solutions ....................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Page 3 of 33
CY7C1480BV25
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1480BV25
(2M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
Document Number: 001-15143 Rev. *N
A
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 4 of 33
CY7C1480BV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1480BV25 (2M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
3
4
5
6
7
8
9
10
11
NC
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDDQ
NC
VDDQ
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQC
NC
DQD
DQB
NC
DQA
DQB
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
A
Document Number: 001-15143 Rev. *N
A0
Page 5 of 33
CY7C1480BV25
Pin Definitions
Pin Name
A0, A1, A
I/O
Description
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
Synchronous CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the
two-bit counter.
InputByte Write Select (BWS) Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWA, BWB,
BWC, BWD, Synchronous Sampled on the rising edge of CLK.
BWE, BWF,
BWG, BWH
GW
InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
BWE
InputByte Write Enable (BWE) Input, Active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
CLK
InputClock
Clock Input. Captures all synchronous inputs to the device. Also increments the burst counter when
ADV is asserted LOW during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
s
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
InputZZ “Sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
Asynchronou condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
s
pin has an internal pull down.
DQs,
DQPs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
Ground
VSS
VSSQ
[1]
VDDQ
Ground for the Core of the Device.
I/O Ground
Ground for the I/O Circuitry.
I/O Power
Supply
Power Supply for the I/O Circuitry.
Note
1. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the I/O circuitry.
Document Number: 001-15143 Rev. *N
Page 6 of 33
CY7C1480BV25
Pin Definitions (continued)
Pin Name
MODE
I/O
Description
Input Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull up.
TDO
JTAG Serial Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature
Output
is not used, this pin must be disconnected. This pin is not available on TQFP packages.
Synchronous
TDI
JTAG Serial Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Input
Synchronous
TMS
JTAG Serial Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
Input
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
JTAG Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected to VSS.
This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.0 ns (250 MHz device).
The CY7C1480BV25 supports secondary cache in systems
using either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486 processors.
The linear burst sequence is suited for processors that use a
linear burst sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tristate control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data is
Document Number: 001-15143 Rev. *N
allowed to propagate through the output register and onto the
data bus within 3.0 ns (250-MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state; its outputs are always
tristated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single read cycles are supported. After the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output tristates immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the BWE and BWX signals control the write
operation.
The CY7C1480BV25 provides Byte Write capability that is
described in the Truth Table for Read/Write on page 10 (for
CY7C1480BV25). Asserting the Byte Write Enable input (BWE)
with the selected Byte Write (BWX) input, selectively writes to
only the desired bytes. Bytes not selected during a byte write
operation remain unaltered. A synchronous self-timed write
mechanism is provided to simplify the write operations.
Because CY7C1480BV25 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs inputs. Doing so tristates the output drivers. As a
safety precaution, DQs are automatically tristated whenever a
write cycle is detected, regardless of the state of OE.
Page 7 of 33
CY7C1480BV25
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the write inputs (GW, BWE, and
BWX) are asserted active to conduct a write to the desired
byte(s). ADSC-triggered write accesses need a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
are required to enter into or exit from this “sleep” mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the “sleep” mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the “sleep” mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Because CY7C1480BV25 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs inputs. Doing so tristates the output drivers. As a
safety precaution, DQs are automatically tristated whenever a
write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1480BV25 provides a two-bit wraparound counter, fed
by A1:A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock cycles
ZZ Mode Electrical Characteristics
Min
Max
Unit
IDDZZ
Parameter
Sleep mode standby current
Description
ZZ > VDD– 0.2 V
–
120
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-15143 Rev. *N
Test Conditions
Page 8 of 33
CY7C1480BV25
Truth Table
The truth table for CY7C1480BV25 follows. [2, 3, 4, 5, 6]
Operation
Add. Used
CE1 CE2 CE3
ZZ
ADSP ADSC ADV
WRITE
OE
CLK
DQ
Deselect cycle, power down
None
H
X
X
L
X
L
X
X
X
L–H
Tristate
Deselect cycle, power down
None
L
L
X
L
L
X
X
X
X
L–H
Tristate
Deselect cycle, power down
None
L
X
H
L
L
X
X
X
X
L–H
Tristate
Deselect cycle, power down
None
L
L
X
L
H
L
X
X
X
L–H
Tristate
Deselect cycle, power down
None
L
X
H
L
H
L
X
X
X
L–H
Tristate
Sleep mode, power down
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H
Tristate
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H
Tristate
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tristate
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tristate
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tristate
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tristate
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
2. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tristate. OE is a do not care for
the remainder of the write cycle
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document Number: 001-15143 Rev. *N
Page 9 of 33
CY7C1480BV25
Truth Table for Read/Write
The read-write truth table for the CY7C1480BV25 follows. [7]
Function (CY7C1480BV25)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Note
7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Document Number: 001-15143 Rev. *N
Page 10 of 33
CY7C1480BV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1480BV25 incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion places
an added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 2.5 V I/O logic
levels.
The CY7C1480BV25 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to VDD through a pull up resistor. TDO must be left unconnected.
At power up, the device comes up in a reset state, which does
not interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the TAP Controller State Diagram on
page 13. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. Whether the output is active depends on the current
state of the TAP state machine. The output changes on the falling
edge of TCK. TDO is connected to the least significant bit (LSB)
of any register.
Performing a TAP Reset
Perform a RESET by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
Document Number: 001-15143 Rev. *N
TAP Registers
Registers are connected between the TDI and TDO balls to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction register. Data is
serially loaded into the TDI ball on the rising edge of TCK. Data
is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. At power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The × 36 configuration has a
73-bit-long register, and the × 18 configuration has a 54-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller moves to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
Page 11 of 33
CY7C1480BV25
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction that is executed
whenever the instruction register is loaded with all zeros.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-zero instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High Z state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is in a test logic reset
state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High Z
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured. Repeatable
results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-15143 Rev. *N
Page 12 of 33
CY7C1480BV25
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-15143 Rev. *N
Page 13 of 33
CY7C1480BV25
TAP Controller Block Diagram
0
Bypass Register
2 1 0
Selection
Circuitry
TDI
Selection
Circuitry
Instruction Register
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
TAP Timing
Figure 3. TAP Timing
1
2
Test Clock
(TCK)
3
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 001-15143 Rev. *N
UNDEFINED
Page 14 of 33
CY7C1480BV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [8, 9]
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS setup to TCK clock rise
5
–
ns
tTDIS
TDI setup to TCK clock rise
5
–
ns
tCS
Capture setup to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
8. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
9. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-15143 Rev. *N
Page 15 of 33
CY7C1480BV25
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
Input pulse levels ...............................................VSS to 2.5 V
1.25V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
50Ω
Output reference levels .............................................. 1.25 V
TDO
Test load termination supply voltage .......................... 1.25 V
Z O= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [10]
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH voltage
IOH = –1.0 mA, VDDQ = 2.5 V
1.7
–
V
VOH2
Output HIGH voltage
IOH = –100 A, VDDQ = 2.5 V
2.1
–
V
VOL1
Output LOW voltage
IOL = 1.0 mA, VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW voltage
IOL = 100 A, VDDQ = 2.5 V
–
0.2
V
VIH
Input HIGH voltage
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VIL
Input LOW voltage
VDDQ = 2.5 V
–0.3
0.7
V
IX
Input load current
GND VI VDDQ
–5
5
A
Note
10. All voltages refer to VSS (GND).
Document Number: 001-15143 Rev. *N
Page 16 of 33
CY7C1480BV25
Identification Register Definitions
Instruction Field
CY7C1480BV25 (2M × 36)
Revision number (31:29)
000
Device depth (28:24)
01011
Description
Describes the version number
Reserved for internal use
Architecture/Memory Type(23:18)
000000
Defines memory type and architecture
Bus width/density(17:12)
100100
Defines width and density
Cypress JEDEC ID code (11:1)
00000110100
ID register presence indicator (0)
1
Enables unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
Bypass
1
ID
32
Boundary scan order – 165-ball FBGA
73
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures the I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-15143 Rev. *N
Page 17 of 33
CY7C1480BV25
Boundary Scan Order
(2 M × 36)
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
1
C1
21
R3
2
D1
22
P2
41
L10
61
B8
42
K11
62
A7
3
E1
23
R4
43
J11
63
B7
4
D2
24
P6
44
K10
64
B6
5
E2
25
R6
45
J10
65
A6
6
F1
26
N6
46
H11
66
B5
7
G1
27
P11
47
G11
67
A5
8
F2
28
R8
48
F11
68
A4
9
G2
29
P3
49
E11
69
B4
10
J1
30
P4
50
D10
70
B3
11
K1
31
P8
51
D11
71
A3
12
L1
32
P9
52
C11
72
A2
13
J2
33
P10
53
G10
73
B2
14
M1
34
R9
54
F10
15
N1
35
R10
55
E10
16
K2
36
R11
56
A10
17
L2
37
N11
57
B10
18
M2
38
M11
58
A9
19
R1
39
L11
59
B9
20
R2
40
M10
60
A8
Document Number: 001-15143 Rev. *N
Page 18 of 33
CY7C1480BV25
Maximum Ratings
Operating Range
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Ambient
Temperature
Range
VDD
0 C to +70 C
Storage temperature ................................ –65 C to +150 C
Commercial
Ambient temperature
with power applied ................................... –55 C to +125 C
Industrial
Supply voltage on VDD relative to GND .......–0.3 V to +3.6 V
Neutron Soft Error Immunity
Supply voltage on VDDQ relative to GND ...... –0.3 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Parameter
2.5 V– 5% / 2.5 V – 5% to
+ 5%
VDD
–40 C to +85 C
Description
Test
Conditions Typ
Max*
Unit
LSBU
Logical
single-bit
upsets
25 °C
361
394
FIT/
Mb
LMBU
Logical
multi-bit
upsets
25 °C
0
0.01
FIT/
Mb
Single event
latch up
85 °C
0
0.1
FIT/
Dev
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
VDDQ
Latch up current .................................................... > 200 mA
SEL
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”
Electrical Characteristics
Over the Operating Range
Parameter [11, 12]
Description
VDD
Power supply voltage
Test Conditions
VDDQ
I/O supply voltage
For 2.5 V I/O
VOH
Output HIGH voltage
For 2.5 V I/O, IOH = –1.0 mA
VOL
Output LOW voltage
For 2.5 V I/O, IOL = 1.0 mA
Min
Max
Unit
2.375
2.625
V
2.375
VDD
V
2.0
–
V
–
0.4
V
V
Input HIGH voltage
[11]
For 2.5 V I/O
1.7
VDD + 0.3
VIL
Input LOW voltage
[11]
For 2.5 V I/O
–0.3
0.7
V
IX
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
VIH
Input current of ZZ
IOZ
Output leakage current
GND VI VDDQ, output disabled
–5
5
A
IDD[13]
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0 ns cycle,
250 MHz
–
450
mA
5.0 ns cycle,
200 MHz
–
450
mA
6.0 ns cycle,
167 MHz
–
400
mA
Notes
11. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2).Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
12. Power up: assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
13. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15143 Rev. *N
Page 19 of 33
CY7C1480BV25
Electrical Characteristics (continued)
Over the Operating Range
Parameter [11, 12]
Description
Automatic CE power down
current – TTL Inputs
ISB1
Test Conditions
Min
Max
Unit
VDD = Max, Device Deselected, 4.0 ns cycle,
VIN VIH or VIN VIL,
250 MHz
f = fMAX = 1/tCYC
5.0 ns cycle,
200 MHz
–
200
mA
–
200
mA
6.0 ns cycle,
167 MHz
–
200
mA
ISB2
Automatic CE power down
current – CMOS inputs
VDD = Max, Device Deselected, All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f=0
–
120
mA
ISB3
Automatic CE power down
current – CMOS inputs
VDD = Max, Device Deselected, 4.0 ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 250 MHz
f = fMAX = 1/tCYC
5.0 ns cycle,
200 MHz
–
200
mA
–
200
mA
6.0 ns cycle,
167 MHz
–
200
mA
–
135
mA
ISB4
Automatic CE power down
current – TTL inputs
VDD = Max, Device Deselected, All speeds
VIN VIH or VIN VIL, f = 0
Capacitance
Parameter [14]
Description
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
100-pin TQFP 165-ball FBGA Unit
Package
Package
CADDRESS
Address input capacitance
CDATA
Data input capacitance
5
5
pF
CCTRL
Control input capacitance
8
8
pF
CCLK
Clock input capacitance
6
6
pF
CIO
Input/output capacitance
5
5
pF
6
6
pF
Thermal Resistance
Parameter [14]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
100-pin TQFP 165-ball FBGA Unit
Max
Max
24.63
16.3
C/W
2.28
2.1
C/W
Note
14. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-15143 Rev. *N
Page 20 of 33
CY7C1480BV25
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1583
VL = 1.25 V
(a)
Document Number: 001-15143 Rev. *N
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Page 21 of 33
CY7C1480BV25
Switching Characteristics
Over the Operating Range
Parameter [15, 16]
tPOWER
Description
VDD(typical) to the first access [17]
250 MHz
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
4.0
–
5.0
–
6.0
–
ns
tCH
Clock HIGH
2.0
–
2.0
–
2.4
–
ns
tCL
Clock LOW
2.0
–
2.0
–
2.4
–
ns
Output Times
tCO
Data output valid after CLK rise
–
3.0
–
3.0
–
3.4
ns
tDOH
Data output hold after CLK rise
1.3
–
1.3
–
1.5
–
ns
1.3
–
1.3
–
1.5
–
ns
–
3.0
–
3.0
–
3.4
ns
–
3.0
–
3.0
–
3.4
ns
0
–
0
–
0
–
ns
–
3.0
–
3.0
–
3.4
ns
[18, 19, 20]
tCLZ
Clock to Low Z
tCHZ
Clock to High Z [18, 19, 20]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output Low Z
[18, 19, 20]
OE HIGH to output High Z
[18, 19, 20]
Setup Times
tAS
Address setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tADS
ADSC, ADSP setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tADVS
ADV setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
Hold Times
Notes
15. Timing reference level is 1.25 V when VDDQ = 2.5 V.
16. Test conditions shown in (a) of Figure 4 on page 21 unless otherwise noted.
17. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(minimum) initially before a read or write operation can be initiated.
18. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 21. Transition is measured ±200 mV from steady-state voltage.
19. At any possible voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
Document Number: 001-15143 Rev. *N
Page 22 of 33
CY7C1480BV25
Switching Waveforms
Figure 5. Read Cycle Timing [21]
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document Number: 001-15143 Rev. *N
Page 23 of 33
CY7C1480BV25
Switching Waveforms (continued)
Figure 6. Write Cycle Timing [22, 23]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 001-15143 Rev. *N
Page 24 of 33
CY7C1480BV25
Switching Waveforms (continued)
Figure 7. Read/Write Cycle Timing [24, 25, 26]
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE, BW X
t CES
tCEH
CE
ADV
OE
t DS
tCO
tDH
t OELZ
Data In (D)
High-Z
tOEHZ
tCLZ
Data Out (Q)
High-Z
Q(A1)
D(A5)
D(A3)
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
25. The data bus (Q) remains in high Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
26. GW is HIGH.
Document Number: 001-15143 Rev. *N
Page 25 of 33
CY7C1480BV25
Switching Waveforms (continued)
Figure 8. ZZ Mode Timing [27, 28]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
27. Device must be deselected when entering ZZ mode. See Truth Table on page 9 for all possible signal conditions to deselect the device.
28. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-15143 Rev. *N
Page 26 of 33
CY7C1480BV25
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
200
Part and Package Type
Operating
Range
CY7C1480BV25-167AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1480BV25-167BZXC
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
CY7C1480BV25-200BZC
51-85165 165-ball FBGA (15 × 17 × 1.4 mm)
Ordering Code
Package
Diagram
CY7C1480BV25-200BZXC
250
CY7C1480BV25-250BZI
Commercial
165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
51-85165 165-ball FBGA (15 × 17 × 1.4 mm)
Industrial
Ordering Code Definitions
CY
7
C 1480 B V25 - XXX XX
X X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Frequency Range: XXX = 167 MHz or 200 MHz or 250 MHz
Voltage: 2.5 V
Die Revision: errata fix PCN084636
Part Identifier: 1480 = SCD, 2Mb × 36 (72Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-15143 Rev. *N
Page 27 of 33
CY7C1480BV25
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-15143 Rev. *N
Page 28 of 33
CY7C1480BV25
Package Diagrams (continued)
Figure 10. 165-ball FBGA ((15 × 17 × 1.40 mm) 0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *E
Document Number: 001-15143 Rev. *N
Page 29 of 33
CY7C1480BV25
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
EIA
Electronic Industries Alliance
°C
degree Celsius
FBGA
Fine-Pitch Ball Grid Array
MHz
megahertz
I/O
Input/Output
µA
microampere
JEDEC
Joint Electron Devices Engineering Council
mA
milliampere
JTAG
Joint Test Action Group
mm
millimeter
LSB
Least Significant Bit
ms
millisecond
LMBU
Logical multi bit upset
mV
millivolt
LSBU
Logical Single Bit Upset
ns
nanosecond
MSB
Most Significant Bit
OE
Output Enable
SEL
Single Event Latch-up
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
Document Number: 001-15143 Rev. *N
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 30 of 33
CY7C1480BV25
Document History Page
Document Title: CY7C1480BV25, 72-Mbit (2M × 36) Pipelined Sync SRAM
Document Number: 001-15143
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
1024385
See ECN
*A
1562944
See ECN
VKN /
AESA
Updated Features (Removed 1.8 V I/O offering).
Updated Functional Description (Removed 1.8 V I/O offering).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed 1.8 V I/O
offering).
Removed 1.8 V TAP AC Test Conditions.
Removed 1.8 V TAP AC Output Load Equivalent.
Updated TAP DC Electrical Characteristics and Operating Conditions
(Removed 1.8 V I/O offering).
Updated Electrical Characteristics (Removed 1.8 V I/O offering).
Updated AC Test Loads and Waveforms (Removed 1.8 V I/O offering).
Updated Switching Characteristics (Removed 1.8 V I/O offering).
*B
1897447
See ECN
VKN /
AESA
Updated Electrical Characteristics (Added Note 13 and referred the same note
in IDD parameter).
Description of Change
VKN /
New data sheet.
KKVTMP
*C
2082487
See ECN
VKN
*D
2159486
See ECN
VKN /
PYRS
*E
2899725
03/26/2010
NJY
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
*F
2957481
06/21/2010
VKN
Added Neutron Soft Error Immunity.
Updated Ordering Information (Included “CY7C1480BV25-167BZXC” in the
Ordering Information table, modified the disclaimer for the Ordering
information) and added Ordering Code Definitions.
*G
3211551
04/19/2011
NJY
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
Added Units of Measure.
Updated to new template.
*H
3244686
04/29/2011
NJY
Updated Ordering Information (Updated part numbers).
*I
3255165
08/11/2011
NJY
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
*J
3596931
04/23/2012
NJY
Updated Features (Removed CY7C1482BV25, CY7C1486BV25 related
information, removed 209-ball FBGA package related information).
Updated Functional Description (Removed CY7C1482BV25, CY7C1486BV25
related information, removed the Note “For best practices recommendations,
refer to the Cypress application note AN1064, SRAM System Guidelines.” and
its reference).
Removed Logic Block Diagram – CY7C1482BV25.
Removed Logic Block Diagram – CY7C1486BV25.
Updated Pin Configurations (Removed CY7C1482BV25, CY7C1486BV25
related information, removed 209-ball FBGA package related information).
Updated Functional Overview (Removed CY7C1482BV25, CY7C1486BV25
related information).
Updated Truth Table (Removed CY7C1482BV25, CY7C1486BV25 related
information).
Updated Truth Table for Read/Write (Corresponding to CY7C1482BV25,
CY7C1486BV25).
Document Number: 001-15143 Rev. *N
Changed status from Preliminary to Final.
Minor Change (Post to external web).
Page 31 of 33
CY7C1480BV25
Document History Page (continued)
Document Title: CY7C1480BV25, 72-Mbit (2M × 36) Pipelined Sync SRAM
Document Number: 001-15143
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*J (cont.)
3596931
04/23/2012
NJY
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1482BV25, CY7C1486BV25 related information).
Updated Identification Register Definitions (Removed CY7C1482BV25,
CY7C1486BV25 related information).
Updated Scan Register Sizes (Removed Bit Size (× 18) and Bit Size (× 72)
columns, removed 209-ball FBGA package related information).
Removed Boundary Scan Order (Corresponding to CY7C1482BV25,
CY7C1486BV25, 209-ball FBGA package).
Updated Capacitance (Removed 209-ball FBGA package related information).
Updated Thermal Resistance (Removed 209-ball FBGA package related
information).
Updated Package Diagrams (spec 51-85165 (Changed revision from *C to *D,
removed 209-ball FBGA package related information (spec 51-85167)).
*K
4396347
06/02/2014
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*L
4574263
11/19/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*M
4781192
05/29/2015
PRIT
Updated Package Diagrams:
spec 51-85165 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*N
5306249
06/13/2016
PRIT
Updated to new template.
Completing Sunset Review.
Document Number: 001-15143 Rev. *N
Page 32 of 33
CY7C1480BV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-15143 Rev. *N
Revised June 13, 2016
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
Page 33 of 33