Supertex inc. HV57009 64-Channel Serial to Parallel Converter with P-Channel Open Drain Controllable Output Current Features ►► HVCMOS technology ►► 5.0V CMOS Logic ►► Output voltage up to -85V ►► Output current source control ►► 16MHz equivalent data rate ►► Latched data outputs ►► Forward and reverse shifting options (DIR pin) ►► Diode to VDD allows efficient power recovery ® General Description The HV57009 is a low-voltage serial to high-voltage parallel converter with P-channel open drain outputs. This device has been designed for use as a driver for plasma panels. The device has two parallel 32-bit shift registers, permitting data rates twice the speed of one (they are clocked together). There are also 64 latches and control logic to perform the blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to VSS, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), or the BL (blanking) inputs. Transfer of data from the shift registers to latches occurs when the LE input is high. The data in the latches is stored when LE is low. The HV570 has 64 channels of output constant current sourcing capability. They are adjustable from 0.1 to 2.0mA through one external resistor or a current source. Functional Block Diagram DI/O2A DI/O1A LE BL VDD I/O HVOUT1 HVOUT2 HVOUT3 • • • HVOUT32 Latch DIR CLK SR1 Latch Latch SR2 Latch Programmable Current I/O DI/O2B DI/O1B VSS VBP +IN HVOUT33 HVOUT34 HVOUT35 • • • HVOUT64 -IN Note: Each SR (shift register) provides 32 outputs. SR1 supplies outputs 1 to 32 and SR2 supplies outputs 33 to 64. Doc.# DSFP-HV57009 A061913 Supertex inc. www.supertex.com HV57009 Pin Configuration Ordering Information Part Number Package Option Packing HV57009PG-G 80-Lead PQFP 66/Tray -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value Supply voltage, VDD1 -0.5V to +7.5V Output voltage , VNN1 VDD + 0.5V to -95V Logic input levels1 -0.3V to VDD +0.3V Ground current2 80 1 80-Lead PQFP 1.5A Continuous total power dissipation3 Operating temperature range Storage temperature range 1200mW Product Marking -40°C to +85°C HV57009PG -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. LLLLLLLLLL YYWW CCCCCCCC AAA L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = “Green” Packaging Package may or may not include the following marks: Si or Notes: 1. All voltages are referenced to VSS. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. 80-Lead PQFP Typical Thermal Resistance Package θja 80-Lead PQFP 37OC/W Recommended Operating Conditions Sym Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V HVOUT HV output off voltage -85 VDD V VIH High-level input voltage VDD -1.2V VDD V VIL Low-level input voltage 0 1.2 V fCLK Clock frequency per register DC TA Operating free-air temperature -40 8.0 4.5 +85 MHz °C Notes: Power-up sequence should be the following: 1. Connect ground 2. Apply VDD 3. Set all inputs to a known state Power-down sequence should be the reverse of the above. Doc.# DSFP-HV57009 A061913 2 Supertex inc. www.supertex.com HV57009 DC Electrical Characteristics (All voltages are referenced to V Sym Parameter , VSS = 0, TA = 25OC) SS Min Max Units Conditions IDD VDD supply current - 15 mA INN High voltage supply current - -10 µA IDDQ Quiescent VDD supply current - 100 µA VOH High level output VDD -0.5V - V IO = -100µA +1.0 VDD V IO = -2.0mA VOL Low level output - +0.5 V IO = 100µA IIH High-level logic input current - 1.0 µA VIH = VDD IIL Low-level logic input current - -1.0 µA VIL = 0V - -2.0 mA VREF = 2.0V, REXT = 1.0KΩ, see Figures 1a and 1b VREF = 0.1V, REXT = 1.0KΩ, see Figures 1a and 1b % VREF = 2.0V, REXT = 1.0KΩ ICS ΔICS Data Out HVOUT Data Out High output source current -0.1 - - 10 HV output source current for IREF = 2.0mA VDD = VDD max, fCLK = 8.0MHz Outputs off, HVOUT = -85V (total of all outputs) All inputs = VDD, except +IN = VSS = GND Note: Current going out of the chip is considered negative. AC Electrical Characteristics (Logic signal inputs and data inputs have t , t ≤ 5ns [10% and 90% points] for measurements) r Sym Parameter Min Clock frequency DC Clock width high or low 62 - ns --- tSU Data set-up time before clock rises 20 - ns --- tH Data hold time after clock rises 15 - ns --- tON, tOFF Time from latch enable to HVOUT - 500 ns CL = 15pF tDHL Delay time clock to data high to low - 150 ns CL = 15pF tDLH Delay time clock to data low to high - 150 ns CL = 15pF tDLE Delay time clock to LE low to high 45 - ns --- tWLE LE pulse width 25 - ns --- tSLE LE set-up time before clock rises 0 - ns --- tr, tf Max. allowable clock rise and fall time (10% and 90% points) - 100 ns --- fCLK tWL, tWH Doc.# DSFP-HV57009 A061913 3 Max f 8.0 4.5 Units MHz Conditions Per register When cascading devices Supertex inc. www.supertex.com HV57009 Input and Output Equivalent Circuits VDD VDD DATA OUTPUT DATA INPUT VSS VSS Logic Data Output Logic Inputs VDD VDD ICS DATA INPUT PCNTRL To Internal Circuits HVOUT VSS Analog Input High Voltage Output Shift Register Operation HVOUT32 • DIR = VDD; CW (HVOUT1→HVOUT64) DIR = VSS; CCW (HVOUT64→HVOUT1) • • CW • • CW • • SR1 HVOUT2 HVOUT1 Pin DIR = VDD DIR = VSS Doc.# DSFP-HV57009 A061913 • • SR1 • HVOUT33 HVOUT63 HVOUT64 25 26 36 DI/O1A DI/O2A DI/O2A DI/O1A 37 DI/O2B DI/O1B DI/O1B DI/O2B 4 Supertex inc. www.supertex.com HV57009 Switching Waveforms DATA INPUT 50% Data Valid VDD 50% tf tH tSU CLK 50% 90% 50% 50% tWL VSS tr 90% 10% tWH 10% 50% VSS tDLH VDD 50% VSS tDLH VSS tWLE tDLE HVOUT w/ Data Input Low tSLE VDD 90% 10% Previous IO = IREF HVOUT(OFF) IO = 0 tOFF 10% HVOUT w/ Data Input High VDD 50% 50% LE VSS VDD 50% DATA OUT VDD 90% VDD IO = IREF HVOUT(OFF) tON Previous IO = 0 Function Table Inputs Function Outputs Data In CLK LE BL DIR Shift Reg HV Outputs Data Out All O/P high X X L X * ON * Data falls through (latches transparent) L H H X L.....L ON L H X _ _↑ _ _↑ H H X H.....H OFF H Data stored in latches X L H X * Inversion of stored data * H H H Qn→Qn+1 New ON or OFF DI/O1-2B L H H Qn→Qn+1 Previous ON or OFF DI/O1-2B L H L Qn→Qn-1 Previous ON or OFF DI/O1-2A H H L Qn→Qn-1 New ON or OFF DI/O1-2A DI/O1-2A I/O relation DI/O1-2A DI/O1-2B DI/O1-2B X _ _↑ _ _↑ _ _↑ _ _↑ Note: * = dependent on previous stage’s state. See Figure 7 for DIN and DOUT pin designation for CW and CCW shift. H = VDD (Logic)/VNN (HV Outputs) L = VSS Doc.# DSFP-HV57009 A061913 5 Supertex inc. www.supertex.com HV57009 Typical Current Programing Circuits VDD 0.1µF HV57009 HV57009 VBP VBP To other outputs Logic HVOUT HVOUT +IN -IN VSS IREF IOUT - + -IN REXT To other outputs Logic IOUT - + +IN VDD 0.1µF RD *10kΩ RD *10kΩ REXT VREF IREF CD *390pF VSS CD *390pF VREF Figure 1b: Positive Control Figure 1a: Negative Control *Required if REXT > 10KΩ or REXT is replaced by a constant current source. Since: diminish. This effect depends on the magnitude of the output current. Given IOUT and VREF, the REXT can be calculated by using: IOUT = IREF = │ VREF │ / REXT Therefore: If IOUT = 2.0mA and VREF = -5.0V → REXT = 2.5KΩ. If IOUT = 1.0mA and REXT = 1.0KΩ → VREF = -1.0V. REXT = VREF / IREF = VREF / IOUT The intersection of a set of IOUT and VREF values can be located in the graph shown below. The value picked for REXT must always be in the shaded area for linear operation. This control method has the advantage that VREF is positive, and draws only leakage current. If REXT > 10KΩ, add series network RD and CD to ground for stability as shown. If REXT >10KΩ, add series network RD and CD to ground for stability as shown. This control method behaves linearly as long as the operational amplifier is not saturated. However, it requires a negative power source and needs to provide a current IREF = IOUT for each HV570 chip being controlled. Note: Lower reference current IREF, results in higher distortion, ∆ICS, on the output. If HVOUT ≥ +1.0V, the HVOUT cascade may no longer operate as a perfect current source, and the output current will HV57009 IOUT vs. VREF 4 0.1k 0.2k 0.5k 1.0k 2.0k 3.0k IOUT (mA) 3 2 5.0K 1 0 0 1 2 3 4 5 VREF (V) Doc.# DSFP-HV57009 A061913 6 Supertex inc. www.supertex.com HV57009 Pin Function Pin # Function Pin # Function Pin # Function Pin # Function 1 HVOUT24 21 HVOUT4 41 HVOUT64 61 HVOUT44 2 HVOUT23 22 HVOUT3 42 HVOUT63 62 HVOUT43 3 HVOUT22 23 HVOUT2 43 HVOUT62 63 HVOUT42 4 HVOUT21 24 HVOUT1 44 HVOUT61 64 HVOUT41 5 HVOUT20 25 DI/O1A 45 HVOUT60 65 HVOUT40 6 HVOUT19 26 DI/O2A 46 HVOUT59 66 HVOUT39 7 HVOUT18 27 NC 47 HVOUT58 67 HVOUT38 8 HVOUT17 28 NC 48 HVOUT57 68 HVOUT37 9 HVOUT16 29 LE 49 HVOUT56 69 HVOUT36 10 HVOUT15 30 CLK 50 HVOUT55 70 HVOUT35 11 HVOUT14 31 BL 51 HVOUT54 71 HVOUT34 12 HVOUT13 32 VSS 52 HVOUT53 72 HVOUT33 13 HVOUT12 33 DIR 53 HVOUT52 73 HVOUT32 14 HVOUT11 34 VDD 54 HVOUT51 74 HVOUT31 15 HVOUT10 35 -IN 55 HVOUT50 75 HVOUT30 16 HVOUT9 36 DI/O2B 56 HVOUT49 76 HVOUT29 17 HVOUT8 37 DI/O1B 57 HVOUT48 77 HVOUT28 18 HVOUT7 38 NC 58 HVOUT47 78 HVOUT27 19 HVOUT6 39 +IN 59 HVOUT46 79 HVOUT26 20 HVOUT5 40 VBP 60 HVOUT45 80 HVOUT25 Notes: 1. Pin designation for DIR = VDD. 2. A 0.1µF capacitor is needed between VDD and VBP (pin 40) for better output current stability and to prevent transient cross-coupling between outputs. See Figures 1a and 1b. Doc.# DSFP-HV57009 A061913 7 Supertex inc. www.supertex.com HV57009 80-Lead PQFP Package Outline (PG) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint D D1 E1 E Note 1 (Index Area D1/4 x E1/4) 80 1 e b Top View θ1 View B A A2 Seating Plane A1 L L1 Side View L2 Gauge Plane θ Seating Plane View B Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 MIN 2.80* 0.25 NOM - - MAX 3.40 A2 b D D1 E E1 2.55 0.30 23.65* 19.80* 17.65* 13.80* 2.80 - 23.90 20.00 17.90 14.00 0.50* 3.05 0.45 24.15* 20.20* 18.15* 14.20* e 0.80 BSC L 0.73 0.88 1.03 L1 L2 1.95 REF 0.25 BSC θ θ1 0O 5O 3.5O - 7O 16O JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995. * This dimension is not specified in the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-80PQFPPG, Version C041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV57009 A061913 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com