Supertex inc. HV574 100MHz, 80-Channel Serial to Parallel Converter with Push-Pull Outputs Features ►► HVCMOS technology ►► 5.0V CMS Logic ►► Output voltage up to 80V ►► Low power level shifting ►► 100MHz equivalent data rate using four dynamic shift registers ►► Latched data outputs ►► Foreward and reverse shifting options (DIR pin) ►► Diode to VPP allows efficient power recovery ►► Outputs may be hot switched ® General Description The HV574 is a low-voltage serial to high-voltage parallel con-verter with push-pull outputs. This device has been designed for use as a driver for printer applications. It can also be used in any application requiring multiple output high-voltage current sour-cing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The device has 4 parallel 20-bit dynamic shift registers, permitting data rates 4X the speed of one (they are clocked together). There are 80 static latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT80). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE (latch enable) input is high. The data in the latches is stored when LE is low. Functional Block Diagram VDD LE BL VPP HVOUT1 DIR DINA DOUTA POL 20-bit Shift Register HVOUT20 CLK HVOUT21 DINB DOUTB 20-bit Shift Register DINC DOUTC 20-bit Shift Register DIND DOUTD 20-bit Shift Register HVOUT40 HVOUT41 HVOUT60 HVOUT61 HVOUT80 GND Doc.# DSFP-HV574 A061913 Supertex inc. www.supertex.com HV574 Pin Configuration Ordering Information Part Number Package Option Packing HV574PG-G 100-Lead PQFP 66/Tray -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to +7.5V Output voltage, VPP -0.5V to +90V Logic input levels 100 1 100-Lead PQFP (top view) -0.3V to VDD +0.3V Ground current1 1.5A Continuous total power dissipation2 Operating temperature range Storage temperature range 1200mW Product Marking HV574PG -40°C to +85°C LLLLLLLLLL YYWW CCCCCCCC AAA -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Limited by the total dissipated in the package. 2. For operation above 25°C ambient derate linearly to 85OC at 20mW/°C. L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = “Green” Packaging Package may or may not include the following marks: Si or 100-Lead PQFP Typical Thermal Resistance Package θja 100-Lead PQFP 39OC/W Recommended Operating Conditions Sym Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V VPP Output voltage 12 80 V VIH High-level input voltage VDD -0.5V - V VIL Low-level input voltage 0 0.5 V fCLK Clock frequency per register 0.001 25 MHz TA Operating free-air temperature -40 +85 °C Notes: Power-up sequence should be the following: 1. Apply ground 2. Apply VDD 3. Set all inputs (Data, CLK, Enable etc.) to a known state 4. Apply VPP The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Doc.# DSFP-HV574 A061913 2 Supertex inc. www.supertex.com HV574 DC Electrical Characteristics (Over recommended operating conditions unless otherwise noted) Sym Parameter Min Max Units Conditions - 30 mA VDD = VDD max, fCLK = 25MHz - 100 µA Outputs high - 100 µA Outputs low - 100 µA All VIN = VDD HVOUT VPP -9.0 - V IO = -30mA, VPP = +80V Data out VDD -0.5 - V IO = -100µA HVOUT - 3.75 V IO = +15mA, VDD = +5.0V Data out - 0.5 V IO = +100µA IDD VDD supply current IPP Quiescent VPP supply current IDDQ Quiescent VDD supply current VOH High-level output VOL Low-level output IIH High-level logic input current - 1.0 µA VIH = VDD IIL Low-level logic input current - -1.0 µA VIL = 0V AC Electrical Characteristics (T A Sym Min Max 0.001 25 0.001 20 Clock width high or low 20 - ns --- tSU Data set-up time before clock rises 0 - ns --- tH Data hold time after clock rises 15 - ns --- tON, tOFF Time from latch enable to HVOUT - 500 ns CL = 15pF tDHL Delay time clock to data high to low - 38 ns CL = 15pF, VDD = 5.0V tDLH Delay time clock to data low to high - 38 ns CL = 15pF, VDD = 5.0V tDLE* Delay time clock to LE low to high 25 - ns --- tWLE LE pulse width 25 - ns --- tSLE LE set-up time before clock rises 0 - ns --- tr, tf Output rise/fall time - 1.0 µs CL = 600pF, HVOUT from 0 - 60V fCLK tWL, tWH Parameter = 85°C max. Logic signal inputs and data inputs have tr, tf ≤ 5.0ns [10% and 90% points]) Clock frequency Units MHz Conditions VDD = 4.5V, TJ = 25OC VDD = 4.5V, TJ = 125OC * tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize). Doc.# DSFP-HV574 A061913 3 Supertex inc. www.supertex.com HV574 Input and Output Equivalent Circuits VDD VDD VPP DATA OUT DATA IN GND GND HVOUT GND Logic Data Output Logic Inputs High Voltage Outputs Switching Waveforms VIH DATA INPUT 50% Data Valid Data Valid VIL tH tSU VIH CLOCK 50% tWL 50% 50% 50% tWH VOH 50% DATA OUT VOL tDLH VOH 50% VOL tDHL tWLE tDLE tSLE 90% 10% HVOUT w/ S/R LOW tOFF HVOUT w/ S/R HIGH VOH 50% 50% LE tf 90% 10% tr VIL VOL VOH VOL VOH VOL tON Doc.# DSFP-HV574 A061913 4 Supertex inc. www.supertex.com HV574 Function Table Inputs Function Outputs Data CLK LE BL POL DIR Shift Reg HV Outputs Data Out All O/P high X X X L L X - H - All O/P low X X X L H X - L - O/P normal X X X H H X - No inversion - O/P inverted X X X H L X - Inversion - L ↑ H H H X L L - H ↑ H H H X H H - L ↑ H H L X L H - H ↑ H H L X H L - X X L H H X * Stored Data - X X L H L X * Inversion of stored data - DINX ↑ H H H H Qn→Qn+1 New H or L DOUTX DINX ↑ L H H H Qn→Qn+1 Previous H or L DOUTX DOUTX ↑ L H H L Qn→Qn-1 Previous H or L DINX DOUTX ↑ H H H L Qn→Qn-1 New H or L DINX Data falls through (latches transparent) Data stored/ latches loaded I/O relation Note: * = dependent on previous stage’s state. See Pin configuration for DIN and DOUT pin designation for CW and CCW shift. Doc.# DSFP-HV574 A061913 5 Supertex inc. www.supertex.com HV574 Pin Function Pin # Function Pin # Function Pin # Function Pin # Function 1 HVOUT30 26 HVOUT5 51 HVOUT80 76 HVOUT55 2 HVOUT29 27 HVOUT4 52 HVOUT79 77 HVOUT54 3 HVOUT28 28 HVOUT3 53 HVOUT78 78 HVOUT53 4 HVOUT27 29 HVOUT2 54 HVOUT77 79 HVOUT52 5 HVOUT26 30 HVOUT1 55 HVOUT76 80 HVOUT51 6 HVOUT25 31 NC 56 HVOUT75 81 HVOUT50 7 HVOUT24 32 VPP 57 HVOUT74 82 HVOUT49 8 HVOUT23 33 HVGND 58 HVOUT73 83 HVOUT48 9 HVOUT22 34 DINA 59 HVOUT72 84 HVOUT47 10 HVOUT21 35 DINB 60 HVOUT71 85 HVOUT46 11 HVOUT20 36 DINC 61 HVOUT70 86 HVOUT45 12 HVOUT19 37 DIND 62 HVOUT69 87 HVOUT44 13 HVOUT18 38 VDD 63 HVOUT68 88 HVOUT43 14 HVOUT17 39 POL 64 HVOUT67 89 HVOUT42 15 HVOUT16 40 LE 65 HVOUT66 90 HVOUT41 16 HVOUT15 41 CLK 66 HVOUT65 91 HVOUT40 17 HVOUT14 42 DIR 67 HVOUT64 92 HVOUT39 18 HVOUT13 43 BL 68 HVOUT63 93 HVOUT38 19 HVOUT12 44 GND 69 HVOUT62 94 HVOUT37 20 HVOUT11 45 DOUTD 70 HVOUT61 95 HVOUT36 21 HVOUT10 46 DOUTC 71 HVOUT60 96 HVOUT35 22 HVOUT9 47 DOUTB 72 HVOUT59 97 HVOUT34 23 HVOUT8 48 DOUTA 73 HVOUT58 98 HVOUT33 24 HVOUT7 49 HVGND 74 HVOUT57 99 HVOUT32 25 HVOUT6 50 VPP 75 HVOUT56 100 HVOUT31 Doc.# DSFP-HV574 A061913 6 Supertex inc. www.supertex.com HV574 100-Lead PQFP Package Outline (PG) 20.00x14.00mm body, 3.40mm height (max), 0.65mm pitch, 3.90mm footprint D D1 E1 E Note 1 (Index Area D1/4 x E1/4) 100 1 e b θ1 Top View View B A A2 Seating Plane A1 L L1 L2 Gauge Plane θ Seating Plane View B Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b 2.80* 0.25 2.55 0.22 - - 2.80 - 3.40 0.50* 3.05 0.38 D D1 E E1 23.65* 19.80* 17.65* 13.80* e L 0.73 L1 L2 θ θ1 0 5O 0.65 1.95 0.25 0.88 3.5O BSC REF BSC O 24.15* 20.20* 18.15* 14.20* 1.03 7 16O 23.90 20.00 17.90 14.00 JEDEC Registration MO-112, Variation CC-1, Issue B, Sept.1995. * This dimension is not specified in the JEDEC drawing.. Drawings not to scale. Supertex Doc. #: DSPD-100PQFPPG, Version B041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV574 A061913 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com