HV57908 DATA SHEET (06/27/2014) DOWNLOAD

Supertex inc.
HV57908
8MHz, 64-Channel Serial to Parallel Converter
with Push-Pull Outputs
Features
►► HVCMOS technology
►► 5.0V CMS Logic
►► Output voltage up to +80V
►► Low power level shifting
►► 8.0MHz data rate
►► Latched data outputs
►► Forward and reverse shifting options (DIR pin)
►► Diode to VPP allows efficient power recovery
►► Outputs may be hot switched
®
General Description
The HV57908 is a low voltage serial to high voltage parallel
converter with push-pull outputs. The device has been designed
for use as a driver for EL displays. It can also be used in any
application requiring multiple output high voltage current sourcing
and sinking capability such as driving plasma panels, vacuum
fluorescent displays, or large matrix LCD displays.
The device consists of a 64-bit shift register, 64 latches and control
logic to perform the polarity select and blanking of the outputs.
HVOUT1 is connected to the first stage of the first shift register
through the polarity and blanking logic. Data is shifted through the
shift registers on the logic low to high transition of the clock. The
DIR pin causes CCW shifting when connected to GND, and CW
shifting when connected to VDD. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register (HVOUT64). Operation of the shift
register is not affected by the LE (latch enable), BL (blanking), or
the POL (polarity) inputs. Transfer of data from the shift registers
to the latches occurs when the LE input is high. The data in the
latches is stored when the LE is low.
Functional Block Diagram
POL
BL
VPP
LE
DI/OA
HVOUT1
CLK
HVOUT2
DIR
•
•
•
60 Additional
Outputs
•
•
•
64-bit
Static Shift
Register
64 Latches
HVOUT63
HVOUT64
DI/OB
Doc.# DSFP-HV57908
A061913
Supertex inc.
www.supertex.com
HV57908
Ordering Information
Pin Configuration
Part Number
Package Option
Packing
HV57908PG-G
80-Lead PQFP
66/Tray
-G denotes a lead (Pb)-free / RoHS compliant package
Absolute Maximum Ratings
Parameter
Value
Supply voltage, VDD
-0.5V to +7.5V
Output voltage, VPP
-0.5V to +90V
Logic input levels
Ground current1
1
1.5A
Continuous total power dissipation2
80-Lead PQFP
Product Marking
1200mW
Operating temperature range
Storage temperature range
80
-0.3V to VDD +0.3V
-40°C to +85°C
HV57908PG
-65°C to +150°C
LLLLLLLLLL
YYWW
CCCCCCCC AAA
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
L = Lot Number
YY = Year Sealed
WW = Week Sealed
C = Country of Origin
A = Assembler ID
= “Green” Packaging
Package may or may not include the following marks: Si or
80-Lead PQFP
Notes:
1. Limited by the total dissipated in the package.
2. For operation above 25°C ambiant derate linearly to maximum
operating temperature at 20mW/°C.
Typical Thermal Resistance
Package
θja
80-Lead PQFP
37OC/W
Recommended Operating Conditions
Sym
Parameter
Min
Max
Units
VDD
Logic supply voltage
4.5
5.5
V
VPP
Output voltage
8.0
80
V
VIH
High-level input voltage
VDD - 0.5
-
V
VIL
Low-level input voltage
0
0.5
V
fCLK
Clock frequency per register
-
8.0
MHz
TA
Operating free-air temperature
-40
+85
°C
Notes:
Power-up sequence should be the following:
1. Apply ground
2. Apply VDD
3. Set all inputs (Data, CLK, Enable, etc.) to a known state
4. Apply VPP
5. The VPP should not drop below VDD or float during operation
Power-down sequence should be the reverse of the above.
Doc.# DSFP-HV57908
A061913
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Supertex inc.
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HV57908
DC Electrical Characteristics (Over recommended operating conditions unless otherwise noted, T = -40°C to +85°C)
A
Sym
Parameter
Min
Max
Units
Conditions
-
15
mA
VDD = VDD max, fCLK = 8.0MHz
-
100
µA
Outputs high
-
100
µA
Outputs low
-
100
µA
All VIN = VDD
65
-
V
IO = -15mA, VPP = +80V
VDD -0.5V
-
V
IO = -100µA
HVOUT
-
7.0
V
IO = +12mA, VPP = +80V
DOUT
-
0.5
V
IO = 100µA
IDD
VDD supply current
IPP
High voltage supply current
IDDQ
Quiescent VDD supply current
VOH
High level output
VOL
Low level output
IIH
High-level logic input current
-
1.0
µA
VIH = VDD
IIL
Low-level logic input current
-
-1.0
µA
VIL = 0V
High voltage clamp diode
-
1.0
V
IOC = 1.0mA
VOC
HVOUT
DOUT
AC Electrical Characteristics (T = +85°C max. Logic signal inputs and data inputs have t , t ≤ 5.0ns [10% and 90% points])
A
Sym
f
Min
Max
Units
Conditions
-
8.0
MHz
Per register
Clock width high or low
62
-
ns
---
tSU
Data set-up time before clock rises
10
-
ns
---
tH
Data hold time after clock rises
15
-
ns
---
tON, tOFF
Time from latch enable to HVOUT
-
500
ns
CL = 15pF
tDHL
Delay time clock to data high to low
-
70
ns
CL = 15pF
tDLH
Delay time clock to data low to high
-
70
ns
CL = 15pF
tDLE*
Delay time clock to LE low to high
25
-
ns
---
tWLE
LE pulse width
25
-
ns
---
tSLE
LE set-up time before clock rises
0
-
ns
---
fCLK
tWL, tWH
Parameter
r
Clock frequency
Note:
* tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes
(allows internal SR output to stabilize).
Doc.# DSFP-HV57908
A061913
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Supertex inc.
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HV57908
Input and Output Equivalent Circuits
VDD
VPP
VDD
DATA
OUTPUT
INPUT
DATA
GND
GND
Logic Inputs
HVOUT
GND
Logic Data Output
High Voltage Outputs
Switching Waveforms
VIH
DATA
INPUT
50%
Data Valid
50%
CLK
50%
tf
tH
tSU
90%
50%
50%
tWL
10%
10%
tWH
VIL
VOH
50%
VOL
tDHL
VIH
50%
50%
tWLE
tDLE
HVOUT
w/ S/R LOW
tSLE
90%
10%
tOFF
HVOUT
w/ S/R HIGH
VIH
VOL
tDLH
LE
90%
50%
VOH
50%
DATA
OUT
VIL
tr
10%
90%
VOL
VOH
VOL
VOH
VOL
tON
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Supertex inc.
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HV57908
Function Table
Inputs
Function
Outputs
Data
CLK
LE
BL
POL
DIR
Shift Reg
HV Outputs
Data Out
All O/P high
X
X
X
L
L
X
-
H
-
All O/P low
X
X
X
L
H
X
-
L
-
O/P normal
X
X
X
H
H
X
-
No inversion
-
O/P inverted
X
X
H
L
X
-
Inversion
-
H
H
H
X
L
L
-
H
H
H
X
H
H
-
H
H
L
X
L
H
-
H
X
_
_↑
_
_↑
_
_↑
_
_↑
H
H
L
X
H
L
-
X
X
L
H
H
X
*
Stored Data
-
X
X
_
_↑
_
_↑
L
H
L
X
*
Inversion of
stored data
-
X
X
X
H
QN→QN+1
-
DI/OB
X
X
X
L
QN→QN-1
-
DI/OA
Data falls
through
(latches
transparent)
Data stored/
latches loaded
I/O relation
L
H
L
DI/OA
DI/OB
Notes:
* = dependent upon previous stage’s state.
Shift Register Operation
HVOUT32
DIR = H; CW (HVOUT1 → HVOUT64)
DIR = L; CCW (HVOUT64 → HVOUT1)
•
DIR = H
•
•
DIR = L
•
SR
•
•
•
•
•
•
HVOUT2
HVOUT63
HVOUT1
HVOUT64
Pin
Doc.# DSFP-HV57908
A061913
HVOUT33
39
D I/OB
25
D I/OA
5
Supertex inc.
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HV57908
Pin Function
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
HVOUT24/41
21
HVOUT4/61
41
HVOUT64/1
61
HVOUT44/21
2
HVOUT23/42
22
HVOUT3/62
42
HVOUT63/2
62
HVOUT43/22
3
HVOUT22/43
23
HVOUT2/63
43
HVOUT62/3
63
HVOUT42/23
4
HVOUT21/44
24
HVOUT1/64
44
HVOUT61/4
64
HVOUT41/24
5
HVOUT20/45
25
DI/OA
45
HVOUT60/5
65
HVOUT40/25
6
HVOUT19/46
26
N/C
46
HVOUT59/6
66
HVOUT39/26
7
HVOUT18/47
27
N/C
47
HVOUT58/7
67
HVOUT38/27
8
HVOUT17/48
28
N/C
48
HVOUT57/8
68
HVOUT37/28
9
HVOUT16/49
29
LE
49
HVOUT56/9
69
HVOUT36/29
10
HVOUT15/50
30
CLK
50
HVOUT55/10
70
HVOUT35/30
11
HVOUT14/51
31
BL
51
HVOUT54/11
71
HVOUT34/31
12
HVOUT13/52
32
VDD
52
HVOUT53/12
72
HVOUT33/32
13
HVOUT12/53
33
DIR
53
HVOUT52/13
73
HVOUT32/33
14
HVOUT11/54
34
GND
54
HVOUT51/14
74
HVOUT31/34
15
HVOUT10/55
35
POL
55
HVOUT50/15
75
HVOUT30/35
16
HVOUT9/56
36
N/C
56
HVOUT49/16
76
HVOUT29/36
17
HVOUT8/57
37
N/C
57
HVOUT48/17
77
HVOUT28/37
18
HVOUT7/58
38
N/C
58
HVOUT47/18
78
HVOUT27/38
19
HVOUT6/59
39
DI/OB
59
HVOUT46/19
79
HVOUT26/39
20
HVOUT5/60
40
VPP
60
HVOUT45/20
80
HVOUT25/40
Notes:
Pin designation for DIR = H/L.
Example:For DIR = H, pin 41 is HVOUT64.
For DIR = L, pin 41 is HVOUT1.
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A061913
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Supertex inc.
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HV57908
80-Lead PQFP Package Outline (PG)
20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint
D
D1
E1 E
Note 1
(Index Area
D1/4 x E1/4)
80
1
e
b
Top View
θ1
View B
A A2
Seating
Plane
A1
L
L1
Side View
L2
Gauge
Plane
θ
Seating
Plane
View B
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
Dimension
(mm)
A
A1
MIN
2.80*
0.25
NOM
-
-
MAX
3.40
A2
b
D
D1
E
E1
2.55 0.30 23.65* 19.80* 17.65* 13.80*
2.80
-
23.90
20.00
17.90
14.00
0.50* 3.05 0.45 24.15* 20.20* 18.15* 14.20*
e
0.80
BSC
L
0.73
0.88
1.03
L1
1.95
REF
L2
0.25
BSC
θ
θ1
0
5O
O
3.5O
-
7
16O
O
JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995.
* This dimension is not specified in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-80PQFPPG, Version C041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV57908
A061913
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1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com