OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 Precision, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers Check for Samples: OPA188 FEATURES DESCRIPTION • Low Offset Voltage: 25 μV (max) • Zero-Drift: 0.03 μV/°C • Low Noise: 8.8 nV/√Hz – 0.1-Hz to 10-Hz Noise: 0.25 µVPP • Excellent DC Precision: – PSRR: 142 dB – CMRR: 146 dB – Open-Loop Gain: 136 dB • Gain Bandwidth: 2 MHz • Quiescent Current: 510 μA (max) • Wide Supply Range: ±2 V to ±18 V • Rail-to-Rail Output • Input Includes Negative Rail • RFI Filtered Inputs • MicroSIZE Packages The OPA188 operational amplifier uses TI proprietary auto-zeroing techniques to provide low offset voltage (25 μV, max), and near zero-drift over time and temperature. This miniature, high-precision, lowquiescent current amplifier offers high input impedance and rail-to-rail output swing within 15 mV of the rails. The input common-mode range includes the negative rail. Either single or dual supplies can be used in the range of +4 V to +36 V (±2 V to ±18 V). 1 2345 The single version is available in the MicroSIZE SOT23-5, MSOP-8, and SO-8 packages. All versions are specified for operation from –40°C to +125°C. 145 Offset Voltage (mV) APPLICATIONS • • • • • • • OPA188 Zero-Drift Architecture Precision Laser Trim Architecture 125 Bridge Amplifiers Strain Gauges Transducer Applications Temperature Measurement Electronic Scales Medical Instrumentation Resistance Temperature Detectors 105 85 65 45 25 5 -55 -35 5 -15 25 45 65 85 105 125 Temperature (°C) Zero-Drift Amplifier Portfolio VERSION Single Dual Quad PRODUCT OFFSET VOLTAGE (µV, max) OFFSET VOLTAGE DRIFT (µV/°C, max) BANDWIDTH (MHz) INPUT VOLTAGE NOISE (µVPP, f = 0.1 Hz to 10 Hz) OPA188 (4 V to 36 V) ±25 OPA333 (5 V) ±10 ±0.085 2 0.25 ±0.05 0.35 OPA378 (5 V) ±50 1.1 ±0.25 0.9 0.4 OPA735 (12 V) ±5 ±0.05 1.6 2.5 OPA2188 (4 V to 36 V) ±25 ±0.085 2 0.25 OPA2333 (5 V) ±10 ±0.05 0.35 1.1 OPA2378 (5 V) ±50 ±0.25 0.9 0.4 OPA2735 (12 V) ±5 ±0.05 1.6 2.5 OPA4188 (4 V to 36 V) ±25 ±0.085 2 0.25 OPA4330 (5 V) ±50 ±0.25 0.35 1.1 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE SOT23-5 DBV –40°C to +125°C SO-8 D –40°C to +125°C MSOP-8 DGK –40°C to +125°C OPA188 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Supply voltage Signal input terminals (2) Output short-circuit Electrostatic discharge (ESD) ratings (2) (3) (4) 2 UNIT V Voltage (V–) – 0.5 to (V+) + 0.5 V Current ±10 mA Differential ±0.7 V (3) Temperature range (1) VALUE ±20, 40 (single supply) Continuous Operating (4), TA –55 to +150 °C Storage, Tstg –65 to +150 °C Junction, TJ +150 °C 1.5 kV 1 kV Human body model (HBM) Charged device model (CDM) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should be current-limited to 10 mA or less. Short-circuit to ground, V-, or V+. Provided device does not exceed maximum junction temperature (TJ) at any time. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS: High-Voltage Operation, VS = ±4 V to ±18 V (VS = +8 V to +36 V) At TA = +25°C, RL = 10 kΩ connected to VS / 2 (1), and VCM = VOUT = VS / 2 (1), unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage PSRR Power-supply rejection ratio TA = –40°C to +125°C VS = 4 V to 36 V, TA = –40°C to +125°C Long-term stability (2) μV ±6 ±25 ±0.03 ±0.085 μV/°C ±0.075 ±0.3 μV/V μV 4 INPUT BIAS CURRENT IB VCM = VS / 2 Input bias current IOS ±160 TA = –40°C to +125°C ±320 Input offset current TA = –40°C to +125°C ±1400 pA ±8 nA ±2800 pA ±4 nA NOISE en f = 0.1 Hz to 10 Hz 250 nVPP f = 0.1 Hz to 10 Hz 40 nVrms Input voltage noise density f = 1 kHz 8.8 nV/√Hz Input current noise density f = 1 kHz 7 fA/√Hz Input voltage noise in INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR Common-mode rejection ratio TA = –40°C to +125°C V– (V+) – 1.5 V (V–) < VCM < (V+) – 1.5 V 120 134 dB (V–) + 0.5 V < VCM < (V+) – 1.5 V, VS = ±18 V 130 146 dB (V–) + 0.5 V < VCM < (V+) – 1.5 V, VS = ±18 V, TA = –40°C to +125°C 120 126 dB INPUT IMPEDANCE ZID Differential 100 || 6 MΩ || pF ZIC Common-mode 6 || 9.5 1012 Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.5 V < VO < (V+) – 0.5 V 130 136 dB (V–) + 0.5 V < VO < (V+) – 0.5 V, TA = –40°C to +125°C 120 126 dB FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate 2 MHz G = +1 0.8 V/μs 0.1% VS = ±18 V, G = 1, 10-V step 20 μs 0.01% VS = ±18 V, G = 1, 10-V step 27 μs 1 μs tS Settling time tOR Overload recovery time VIN × G = VS THD+N Total harmonic distortion + noise 1 kHz, G = 1, VOUT = 1 Vrms (1) (2) 0.0001% VS / 2 = midsupply. 1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 3 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS: High-Voltage Operation, VS = ±4 V to ±18 V (VS = +8 V to +36 V) (continued) At TA = +25°C, RL = 10 kΩ connected to VS / 2(1), and VCM = VOUT = VS / 2(1), unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT OUTPUT No load Voltage output swing from rail ISC Short-circuit current RO Open-loop output resistance CLOAD Capacitive load drive 6 15 mV RL = 10 kΩ 220 250 mV TA = –40°C to +125°C 310 350 mV Sinking -18 mA Sourcing +16 mA f = 1 MHz, IO = 0 120 Ω 1 nF POWER SUPPLY VS IQ Operating voltage range Quiescent current (per amplifier) 4 to 36 (±2 to ±18) VS = ±4 V to VS = ±18 V 450 IO = 0 mA, TA = –40°C to +125°C V 510 μA 540 μA TEMPERATURE RANGE Specified temperature range –40 +125 °C TA Operating temperature range –55 +150 °C Tstg Storage temperature range –65 +150 °C 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS: Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V) At TA = +25°C, RL = 10 kΩ connected to VS / 2 (1), and VCM = VOUT = VS / 2 (1), unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage PSRR Power-supply rejection ratio Long-term stability μV ±6 ±25 TA = –40°C to +125°C ±0.03 ±0.085 μV/°C VS = 4 V to 36 V, TA = –40°C to +125°C 0.075 0.3 μV/V (2) μV 4 INPUT BIAS CURRENT IB Input bias current IOS Input offset current ±160 TA = –40°C to +125°C ±320 TA = –40°C to +125°C ±1400 pA ±8 nA ±2800 pA ±4 nA NOISE en f = 0.1 Hz to 10 Hz 250 nVPP f = 0.1 Hz to 10 Hz 40 nVrms Input voltage noise density f = 1 kHz 8.8 nV/√Hz Input current noise density f = 1 kHz 7 fA/√Hz Input voltage noise in INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR Common-mode rejection ratio TA = –40°C to +125°C V– (V+) – 1.5 V (V–) < VCM < (V+) – 1.5 V 106 114 dB (V–) + 0.5 V < VCM < (V+) – 1.5 V, VS = ±2 V 114 120 dB (V–) + 0.5 V < VCM < (V+) – 1.5 V, VS = ±2 V, TA = –40°C to +125°C 110 120 dB INPUT IMPEDANCE ZID Differential 100 || 6 MΩ || pF ZIC Common-mode 6 || 9.5 1012 Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.5 V < VO < (V+) – 0.5 V, RL = 5 kΩ 110 120 dB (V–) + 0.5 V < VO < (V+) – 0.5 V 120 130 dB (V–) + 0.5 V < VO < (V+) – 0.5 V, TA = –40°C to +125°C 110 120 dB FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate G = +1 tOR Overload recovery time VIN × G = VS THD+N Total harmonic distortion + noise 1 kHz, G = 1, VOUT = 1 Vrms (1) (2) 2 MHz 0.8 V/μs 1 μs 0.0001% VS / 2 = midsupply. 1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 5 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS: Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V) (continued) At TA = +25°C, RL = 10 kΩ connected to VS / 2(1), and VCM = VOUT = VS / 2(1), unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT OUTPUT No load Voltage output swing from rail ISC Short-circuit current RO Open-loop output resistance CLOAD Capacitive load drive 6 15 mV RL = 10 kΩ 220 250 mV TA = –40°C to +125°C 310 350 mV Sinking -18 mA Sourcing +16 mA f = 1 MHz, IO = 0 120 Ω 1 nF POWER SUPPLY VS Operating voltage range IQ Quiescent current (per amplifier) 4 to 36 (±2 to ±18) VS = ±2 V to VS = ±4 V V 425 IO = 0 mA, TA = –40°C to +125°C 480 μA 525 μA TEMPERATURE RANGE Specified temperature range –40 +125 °C TA Operating temperature range –55 +150 °C Tstg Storage temperature range –65 +150 °C THERMAL INFORMATION OPA188 THERMAL METRIC (1) D (SO) DGK (MSOP) DBV (SOT23) 8 PINS 8 PINS 5 PINS θJA Junction-to-ambient thermal resistance 122.0 180.4 158.8 θJCtop Junction-to-case (top) thermal resistance 68.5 67.9 60.7 θJB Junction-to-board thermal resistance 63.5 102.1 44.8 ψJT Junction-to-top characterization parameter 13.7 10.4 1.6 ψJB Junction-to-board characterization parameter 62.8 100.3 44.2 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A N/A (1) 6 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 PIN CONFIGURATIONS OPA188 D, DGK PACKAGES (SO-8, MSOP-8) (TOP VIEW) (1) 1 8 NC -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC NC OPA188 DBV PACKAGE (SOT23-5) (TOP VIEW) OUT 1 V- 2 +IN 3 5 V+ 4 -IN (1) NC = no connection. FUNCTIONAL BLOCK DIAGRAM V+ C2 OPA188 CHOP1 GM1 NOTCH FILTER CHOP2 GM2 GM3 OUT +IN -IN C1 GM_FF V- Figure 1. Functional Block Diagram Table 1. Component Count COMPONENT COUNT Transistors 636 Diodes 5 Resistors 41 Capacitors 72 Figure 1 shows a representation of the proprietary OPA188 architecture. Table 1 contains both the active and passive component count for this device. The component count allows for accurate reliability calculations. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 7 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS Table 2. Characteristic Performance Measurements DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 2 Offset Voltage Drift Distribution Figure 3 Offset Voltage vs Temperature Figure 4 Offset Voltage vs Common-Mode Voltage Figure 5, Figure 6 Offset Voltage vs Power Supply Figure 7 Open-Loop Gain and Phase vs Frequency Figure 8 Closed-Loop Gain vs Frequency Figure 9 IB and IOS vs Common-Mode Voltage Figure 10 Input Bias Current vs Temperature Figure 11 Output Voltage Swing vs Output Current (Maximum Supply) Figure 12 CMRR and PSRR vs Frequency (Referred-to-Input) Figure 13 CMRR vs Temperature Figure 14, Figure 15 PSRR vs Temperature Figure 16 0.1-Hz to 10-Hz Noise Figure 17 Input Voltage Noise Spectral Density vs Frequency Figure 18 THD+N Ratio vs Frequency Figure 19 THD+N vs Output Amplitude Figure 20 Quiescent Current vs Supply Voltage Figure 21 Quiescent Current vs Temperature Figure 22 Open-Loop Gain vs Temperature Figure 23 Open-Loop Output Impedance vs Frequency Figure 24 Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 25, Figure 26 No Phase Reversal Figure 27 Positive Overload Recovery Figure 28 Negative Overload Recovery Figure 29 Small-Signal Step Response (100 mV) Figure 30, Figure 31 Large-Signal Step Response Figure 32, Figure 33 Large-Signal Settling Time (10-V Positive Step) Figure 34 Large-Signal Settling Time (10-V Negative Step) Figure 35 Short-Circuit Current vs Temperature Figure 36 Maximum Output Voltage vs Frequency Figure 37 EMIRR IN+ vs Frequency Figure 38 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 40 Data Taken From 3 Unique Fab Lots Data Taken From 3 Unique Fab Lots Percentage of Amplifiers (%) 16 14 12 10 8 6 4 35 30 25 20 15 10 5 2 15 5 Typical Units Shown VS = ±18 V VOS (mV) 0.09 0 -5 -5 -10 -10 -15 -2.5 -15 -55 -35 -15 5 25 45 65 85 105 125 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 VCM (V) Temperature (°C) Figure 4. OFFSET VOLTAGE vs TEMPERATURE Figure 5. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 15 5 Typical Units Shown VS = ±18 V 5 Typical Units Shown VSUPPLY = ±2 V to ±18 V 10 5 VOS (mV) 5 VOS (mV) 0.08 5 0 10 0.07 5 Typical Units Shown VS = ±2 V 10 5 15 0.06 Figure 3. OFFSET VOLTAGE DRIFT DISTRIBUTION 15 VOS (mV) 0.05 Offset Voltage Drift (mV/°C) Figure 2. OFFSET VOLTAGE PRODUCTION DISTRIBUTION 10 0.04 0.01 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 Offset Voltage (mV) 0.1 0 0 0.03 Percentage of Amplifiers (%) 18 0.02 20 0 0 -5 -5 -10 -10 -15 -15 -20 -15 -10 -5 0 5 10 15 20 0 VCM (V) 2 4 6 8 10 12 14 16 18 20 VSUPPLY (V) Figure 6. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE Figure 7. OFFSET VOLTAGE vs POWER SUPPLY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 9 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 140 25 0 GBW = 2MHz Dominant Pole @7mHz 120 Gain 20 Phase 90 60 40 Gain (dB) 10 80 Phase (ƒ) Gain (dB) 15 45 100 5 0 -5 135 20 -10 0 G = 10 G = +1 G = -1 -15 ±20 1 10 100 1k 10k 100k 1M 180 10M -20 10k C007 100k 1M 10M Frequency (Hz) Figure 8. OPEN-LOOP GAIN AND PHASE vs FREQUENCY Figure 9. CLOSED-LOOP GAIN vs FREQUENCY 4000 500 IB+ 400 IB- 300 IOS IB- 3000 IOS Input Bias Current (pA) IB and IOS (pA) IB+ 200 100 0 -100 2000 1000 0 -1000 -200 -2000 -300 -20 -15 -10 0 -5 5 10 15 -55 20 -35 -15 25 45 65 85 105 125 Figure 11. INPUT BIAS CURRENT vs TEMPERATURE 160 (V+) + 2 (V+) + 1 (V+) (V+) - 1 (V+) - 2 (V+) - 3 (V+) - 4 (V-) + 4 (V-) + 3 (V-) + 2 (V-) + 1 (V-) (V-) - 1 (V-) - 2 Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) Output Voltage (V) Figure 10. IB AND IOS vs COMMON-MODE VOLTAGE -40°C +25°C +125°C 140 120 100 80 60 40 +PSRR -PSRR CMRR 20 0 0 2 4 6 8 10 12 14 16 18 20 22 24 1 10 100 1k 10k 100k 1M Frequency (Hz) Output Current (mA) Figure 12. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (Maximum Supply) 10 5 Temperature (°C) VCM (V) Figure 13. CMRR AND PSRR vs FREQUENCY (Referred-to-Input) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) 40 Common-Mode Rejection Ratio (mV/V) Common-Mode Rejection Ratio (mV/V) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. (V-) < VCM < (V+) - 1.5 V 35 (V-) + 0.5 V < VCM < (V+) - 1.5 V 30 VSUPPLY = ±2 V 25 20 15 10 5 0 8 (V-) < VCM < (V+) - 1.5 V 7 (V-) + 0.5 V < VCM < (V+) - 1.5 V 6 VSUPPLY = ±18 V 5 4 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 -55 -35 -15 5 25 45 65 85 105 Temperature (°C) Temperature (°C) Figure 14. CMRR vs TEMPERATURE Figure 15. CMRR vs TEMPERATURE 125 5 Typical Units Shown VSUPPLY = ±2 V to ±18 V 0.6 +3*sigma 0.4 50nV/div Power-Supply Rejection Ratio (mV/V) 1 0.8 0.2 0 -0.2 -0.4 -3*sigma 3*Sigma Noise = 172nVPP Peak-to-Peak Noise = VRMS*6.6 = 250nV -0.6 -0.8 Time (1s/div) -1 C016 -55 -35 -15 5 25 45 65 85 105 125 Temperature (°C) Figure 16. PSRR vs TEMPERATURE Figure 17. 0.1-Hz TO 10-Hz NOISE Total Harmonic Distortion + Noise (%) 0.01 10 -80 VOUT = 1 VRMS BW = 80 kHz 0.001 -100 0.0001 -120 G = +1, RL = 10 kW G = -1, RL = 10 kW 0.00001 1 0.1 1 10 100 1k 10k 100k 10 Frequency (Hz) Figure 18. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 100 1k 10k -140 20k Frequency (Hz) Figure 19. THD+N RATIO vs FREQUENCY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 Total Harmonic Distortion + Noise (dB) Voltage Noise Density (nV/ÖHz) 100 11 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 0.01 -80 0.001 -100 0.0001 -120 G = +1, RL = 10 kW G = -1, RL = 10 kW 0.00001 0.01 0.5 0.48 0.46 0.44 IQ (mA) Total Harmonic Distortion + Noise (%) -60 BW = 80 kHz Total Harmonic Distortion + Noise (dB) 0.1 1 10 0.4 0.38 0.36 0.34 0.32 -140 0.1 0.42 Specified Supply-Voltage Range 0.3 20 0 Output Amplitude (VRMS) 3 16 20 24 28 32 36 VSUPPLY = 4 V, RL = 10 kW VS = ±18 V VS = ±2 V VSUPPLY = 36 V, RL = 10 kW 2.5 0.44 2 AOL (mV/V) IQ (mA) 12 Figure 21. QUIESCENT CURRENT vs SUPPLY VOLTAGE 0.5 0.46 8 Supply Voltage (V) Figure 20. THD+N vs OUTPUT AMPLITUDE 0.48 4 0.42 0.4 0.38 1.5 1 0.36 0.34 0.5 0.32 0 0.3 -55 -35 -15 5 25 45 65 85 105 125 -55 -35 5 -15 Temperature (°C) 25 45 65 85 105 125 Temperature (°C) Figure 22. QUIESCENT CURRENT vs TEMPERATURE Figure 23. OPEN-LOOP GAIN vs TEMPERATURE 40 10k RL = 10 kW 35 RISO = 0 W 30 Overshoot (%) ZO (W) 1k 100 10 RISO = 25 W 25 RISO = 50 W 20 15 RISO Device 1 -18 V 5 RL CL 0 0.1 1 10 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Frequency (Hz) Figure 24. OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY 12 G = +1 +18 V 10 Submit Documentation Feedback Figure 25. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100-mV Output Step) Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 40 RISO = 0 W 35 Device RISO = 50 W 30 25 -18 V 37 VPP Sine Wave (±18.5 V) 5 V/div Overshoot (%) +18 V RISO = 25 W 20 15 RI = 10 kW 10 RF = 10 kW G = -1 +18 V VIN VOUT RISO Device 5 CL RL = RF = 10 kW -18 V 0 0 Time (100 ms/div) 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Figure 26. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100-mV Output Step) Figure 27. NO PHASE REVERSAL VIN VOUT 20 kW 20 kW +18 V Device 5 V/div 5 V/div 2 kW VOUT VIN TOR -18 V 2 kW +18 V TOR VOUT Device VIN -18 V G = -10 G = -10 VOUT VIN Time (5 ms/div) Time (5 ms/div) Figure 28. POSITIVE OVERLOAD RECOVERY Figure 29. NEGATIVE OVERLOAD RECOVERY +18 V RL = RF = 2 kW CL = 10 pF 20 mV/div 20 mV/div RL = 10 kW CL = 10 pF G = +1 RI = 2 kW RF = 2 kW +18 V Device Device -18 V RL CL CL -18 V G = -1 Time (20 ms/div) Time (1 ms/div) Figure 30. SMALL-SIGNAL STEP RESPONSE (100 mV) Figure 31. SMALL-SIGNAL STEP RESPONSE (100 mV) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 13 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. G = +1 RL = 10 kW CL = 10 pF 5 V/div 5 V/div G = -1 RL = 10 kW CL = 10 pF Time (50 ms/div) Time (50 ms/div) Figure 32. LARGE-SIGNAL STEP RESPONSE 10 G = -1 8 6 4 12-Bit Settling 2 0 -2 (±1/2 LSB = ±0.024%) -4 -6 -8 Output D From Final Value (mV) Output D From Final Value (mV) 10 Figure 33. LARGE-SIGNAL STEP RESPONSE -10 G = -1 8 6 4 12-Bit Settling 2 0 -2 (±1/2 LSB = ±0.024%) -4 -6 -8 -10 0 10 20 30 40 50 60 0 10 20 Time (ms) 30 40 50 60 Time (ms) Figure 34. LARGE-SIGNAL SETTLING TIME (10-V Positive Step) Figure 35. LARGE-SIGNAL SETTLING TIME (10-V Negative Step) 30 15 20 12.5 Output Voltage (VPP) VS = ±15 V ISC (mA) 10 ISC, Source 0 ISC, Sink -10 10 Maximum output voltage without slew-rate induced distortion. 7.5 VS = ±5 V 5 2.5 -20 VS = ±2.25 V 0 -30 -55 -35 -15 5 25 45 65 85 105 125 1k Figure 36. SHORT-CIRCUIT CURRENT vs TEMPERATURE 14 10k 100k 1M 10M Frequency (Hz) Temperature (°C) Figure 37. MAXIMUM OUTPUT VOLTAGE vs FREQUENCY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 160 140 EMIRR IN+ (dB) 120 100 80 60 40 20 0 10M 100M 1G 10G Frequency (Hz) Figure 38. EMIRR IN+ vs FREQUENCY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 15 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION The OPA188 operational amplifier combines precision offset and drift with excellent overall performance, making the device ideal for many precision applications. The precision offset drift of only 0.085 µV per degree Celsius provides stability over the entire temperature range. In addition, the device offers excellent overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. OPERATING CHARACTERISTICS The OPA188 is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics section. EMI REJECTION The OPA188 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI interference from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPA188 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 39 shows the results of this testing on the OPA188. Table 3 shows the EMIRR IN+ values for the OPA188 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 3 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the Application Report EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from www.ti.com. 160 140 EMIRR IN+ (dB) 120 100 80 60 40 20 0 10M 100M 1G 10G Frequency (Hz) Figure 39. EMIRR Testing Table 3. OPA188 EMIRR IN+ for Frequencies of Interest 16 FREQUENCY APPLICATION/ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 62.2 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 74.7 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 100.7 dB 2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, Sband (2 GHz to 4 GHz) 102.4 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 104.8 dB 5.0 GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 100.3 dB Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 GENERAL LAYOUT GUIDELINES For best operational performance of the device, good printed circuit board (PCB) layout practices are recommended. Including: • Low-ESR, 0.1-µF ceramic bypass capacitors should be connected between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-supply applications. • In order to reduce parasitic coupling, run the input traces as far away from the supply lines as possible. • A ground plane helps distribute heat and reduces EMI noise pickup. • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. PHASE-REVERSAL PROTECTION The OPA188 has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPA188 input prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 40. +18 V Device 5 V/div -18 V 37 VPP Sine Wave (±18.5 V) VIN VOUT Time (100 ms/div) Figure 40. No Phase Reversal INPUT BIAS CURRENT CLOCK FEEDTHROUGH Zero-drift amplifiers, such as the OPA188, use switching on their inputs to correct for the intrinsic offset and drift of the amplifier. Charge injection from the integrated switches on the inputs can introduce very short transients in the input bias current of the amplifier. The extremely short duration of these pulses prevents them from being amplified, however they may be coupled to the output of the amplifier through the feedback network. The most effective method to prevent transients in the input bias current from producing additional noise at the amplifier output is to use a low-pass filter such as an RC network. INTERNAL OFFSET CORRECTION The OPA188 op amp uses an auto-calibration technique with a time-continuous 750-kHz op amp in the signal path. This amplifier is zero-corrected every 3 μs using a proprietary technique. Upon power-up, the amplifier requires approximately 100 μs to achieve the specified VOS accuracy. This design has no aliasing or flicker noise. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 17 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com CAPACITIVE LOAD AND STABILITY The device dynamic characteristics are optimized for a range of common operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the amplifier phase margin and can lead to gain peaking or oscillations. As a result, larger capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Figure 41 and Figure 42 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. Also, refer to the Applications Report, Feedback Plots Define Op Amp AC Performance (SBOA015), available for download from www.ti.com, for details of analysis techniques and application circuits. 40 40 RL = 10 kW RISO = 0 W 35 35 RISO = 0 W RISO = 25 W 25 RISO = 25 W RISO = 50 W 30 RISO = 50 W 20 15 G = +1 +18 V RISO 10 -18 V 25 20 15 RI = 10 kW 10 Device 5 Overshoot (%) Overshoot (%) 30 RL RF = 10 kW G = -1 +18 V RISO CL Device 5 CL RL = RF = 10 kW -18 V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 Capacitive Load (pF) 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Figure 41. Small-Signal Overshoot versus Capacitive Load (100-mV Output Step) Figure 42. Small-Signal Overshoot versus Capacitive Load (100-mV Output Step) ELECTRICAL OVERSTRESS Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. See Figure 43 for an illustration of the ESD circuits contained in the OPA188 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse while discharging through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the protection circuitry is then dissipated as heat. When an ESD voltage develops across two or more amplifier device pins, current flows through one or more steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA188 but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level. When the operational amplifier connects into a circuit (such as the one Figure 43 depicts), the ESD protection components are intended to remain inactive and do not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device. 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 Figure 43 shows a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA. If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. Another common question involves what happens to the amplifier if an input signal is applied to the input while the power supplies +VS or –VS are at 0 V. Again, this question depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source via the current-steering diodes. This state is not a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path. If there is any uncertainty about the ability of the supply to absorb this current, external zener diodes may be added to the supply pins, as shown in Figure 43. The zener voltage must be selected such that the diode does not turn on during normal operation. However, the zener voltage should be low enough so that the zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. (2) TVS RF V+ +VS OPA188 RI ESD CurrentSteering Diodes IN (3) RS +IN Op Amp Core Edge-Triggered ESD Absorption Circuit ID VIN OUT RL (1) V- VS (2) TVS (1) VIN = +VS + 500 mV. (2) TVS: +VS(max) > VTVSBR (min) > +VS. (3) Suggested value is approximately 1 kΩ. Figure 43. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application The OPA188 input terminals are protected from excessive differential voltage with back-to-back diodes, as shown in Figure 43. In most circuit applications, the input protection circuitry has no consequence. However, in low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the signal input current. This input series resistor degrades the low-noise performance of the OPA188. Figure 43 shows an example configuration that implements a current-limiting feedback resistor. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 19 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com APPLICATION EXAMPLES The following application examples highlight only a few of the circuits where the OPA188 can be used. TINA-TI™ (Free Download Software) Using a TINA-TI SPICE-Based Analog Simulation Program with the OPA188 TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer users the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. Figure 44 shows an example of how the OPA188 can be used as a high-voltage, high-impedance front-end for a precision, discreet instrumentation amplifier with attenuation. The INA159 provides the attenuation that allows this circuit to easily interface with 3.3-V or 5-V analog-to-digital converters (ADCs). Click the following link download the TINA-TI file: Discreet INA. 15 V U2 VOUTP OPA188 5V VDIFF / 2 VCM 10 -15 V Ref 1 Ref 2 RG 500 W + R5 10 kW R7 10 kW U1 INA159 (1) VOUT Sense -VDIFF / 2 -15 V U3 OPA188 VOUTN 15 V (1) VOUT = VDIFF × (41 / 5) + (Ref 1) / 2. Figure 44. Discrete INA + Attenuation for ADC with 3.3-V Supply 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 Figure 45 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI file: Bridge Amplifier Circuit. 15V R1 15V R R R OPA188 VOUT + R R1 VREF Figure 45. Bridge Amplifier Figure 46 shows the OPA188 configured in a low-side current-sensing application. The load current (ILOAD) creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the OPA188, with a gain of 201. The load current is set from 0 A to 500 mA, which corresponds to an output voltage range from 0 V to 10 V. The output range can be adjusted by changing the shunt resistor or gain of the configuration. Click the following link to download the TINA-TI file: Current-Sensing Circuit. V Load 15V + OPA188 ILOAD RSHUNT VOUT VOUT= ILOAD*RSHUNT(1+RF/RIN) VOUT / ILOAD= 1V/49.75mA 100m RIN RF 100 20k CF 150pF Figure 46. Low-Side Current Monitor Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 21 OPA188 SBOS642A – MARCH 2013 – REVISED MARCH 2013 www.ti.com Figure 47 shows the OPA188 configured as a precision programmable power supply using the 16-bit, voltage output DAC8581 and the OPA548 high-current amplifier. This application amplifies the digital-to-analog converter (DAC) voltage by a value of five and handles a large variety of capacitive and current loads. The OPA188 in the front-end provides precision and low drift across a wide range of inputs and conditions. Click the following link to download the TINA-TI file: Programmable Power-Supply Circuit. C1 150pF R1 10k R2 1k R4 40k C2 500nF 30V 15V R3 10k OPA548 + DAC8581 VOUT + OPA188 VOUT = ± 25V -30V -15V Input = ± 5V Figure 47. Programmable Power Supply Refer to the Applications Report, Analog linearization of resistance temperature detectors (SLYT442) for an indepth analysis of Figure 48. Click the following link to download the TINA-TI file: RTD Amplifier with Linearization. +15 V (5 V) Out REF5050 In 1 mF 1 mF R2 49.1 kW R3 60.4 kW R1 4.99 kW OPA188 VOUT 0°C = 0 V 200°C = 5 V R5 (1) 105.8 kW RTD Pt100 R4 1 kW (1) R5 provides positive-varying excitation to linearize output. Figure 48. RTD Amplifier with Linearization 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 OPA188 www.ti.com SBOS642A – MARCH 2013 – REVISED MARCH 2013 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (March 2013) to Revision A • Page Changed document status to Production Data ..................................................................................................................... 1 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA188 23 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA188AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA188 OPA188AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QXZ OPA188AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QXZ OPA188AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QXX OPA188AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QXX OPA188AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA188 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jan-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ OPA188AIDBVR SOT-23 3000 180.0 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.4 3.23 3.17 1.37 4.0 W Pin1 (mm) Quadrant 8.0 Q3 OPA188AIDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA188AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA188AIDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA188AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jan-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA188AIDBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 OPA188AIDBVT SOT-23 DBV 5 250 202.0 201.0 28.0 OPA188AIDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 OPA188AIDGKT VSSOP DGK 8 250 202.0 201.0 28.0 OPA188AIDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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