PROFET® BTS 840 S2
Smart High-Side Power Switch
Two Channels: 2 x 30mΩ
Current Sense
Product Summary
Vbb(on)
Active channels:
On-state Resistance
RON
Load Current (ISO)
IL(ISO)
Current Limitation
IL(SCr)
Package
Operating Voltage
one
30mΩ
12A
24A
5.0...34V
two parallel
15mΩ
24A
24A
P-DSO-20-12 (Power SO 20)
General Description
•
•
N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input,
diagnostic feedback and proportional load current sense monolithically integrated in Smart SIPMOS
technology.
Providing embedded protective functions
Applications
•
•
•
•
µC compatible high-side power switch with diagnostic feedback for 12V and 24V grounded loads
All types of resistive, inductive and capacitve loads
Most suitable for loads with high inrush currents, so as lamps
Replaces electromechanical relays, fuses and discrete circuits
Basic Functions
•
•
•
•
CMOS compatible input
Undervoltage and overvoltage shutdown with auto-restart and hysteresis
Fast demagnetization of inductive loads
Logic ground independent from load ground
Protection Functions
•
•
•
•
•
•
•
•
Short circuit protection
Overload protection
Current limitation
Thermal shutdown
Overvoltage protection (including load dump) with external
resistor
Reverse battery protection with external resistor
Loss of ground and loss of Vbb protection
Electrostatic discharge protection (ESD)
Diagnostic Functions
•
•
•
•
Proportinal load current sense
Diagnostic feedback with open drain output
Open load detection in OFF-state with external resistor
Feedback of thermal shutdown in ON-state
Infineon technologies
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Vbb
IN1
ST1
IS1
Logic
Channel
1
IN2
ST2
IS2
Logic
Channel
2
PROFET
GND
OUT 1
Load 1
OUT 2
Load 2
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BTS 840 S2
Functional diagram
overvoltage
protection
internal
voltage supply
logic
gate
control
+
charge
pump
current limit
VBB
clamp for
inductive load
OUT1
temperature
sensor
IN1
ESD
ST1
GND1
Current
sense
IS1
GND1
IN2
LOAD
RO1
Open load
detection
Channel 1
Control and protection circuit
of
channel 2
ST2
IS2
GND2
OUT2
PROFET
Pin Definitions and Functions
Pin
1,10,
11,12,
Symbol
Vbb
3
7
16,17,
18,19
12,13,
14,15
IN1
IN2
OUT1
4
8
2
6
5
9
ST1
ST2
GND1
GND2
IS1
IS2
Heatslug
Vbb
OUT2
Pin configuration
Function
Positive power supply voltage. For high
current applications the heat slug should be
used as Vbb connection.
Input 1,2, activates channel 1,2 in case of
logic high signal
Output 1,2, protected high-side power output
of channel 1,2. All pins of each output have to
be connected in parallel for operation
according ths spec (e.g. kilis). Design the
wiring for the max. short circuit current
Diagnostic feedback 1,2 of channel 1,2
open drain, invers to input level
Ground 1,2 of chip channel 1,2
(top view)
Vbb
GND1
IN1
ST1
IS1
GND2
IN2
ST2
IS2
Vbb
1•
2
3
4
5
6
Vbb
7
8
9
10
Heat slug
20
19
18
17
16
15
14
13
12
11
Vbb
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
Vbb
Sense current output 1,2; proportional to the
load current, zero in the case of current
limitation of the load current
Positiv powersupply voltage. Good way to
design a very low thermal resistance.
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2003-Oct-01
BTS 840 S2
Maximum Ratings at Tj = 25°C unless otherwise specified
Parameter
Symbol
Supply voltage (overvoltage protection see page 5)
Supply voltage for full short circuit protection
Tj,start = -40 ...+150°C
Load current (Short-circuit current, see page 5)
Load dump protection1) VLoadDump = VA + Vs, VA = 13.5 V
RI2) = 2 Ω, td = 200 ms; IN = low or high,
each channel loaded with RL = 1.0 Ω,
Operating temperature range
Storage temperature range
Power dissipation (DC)4)
Ta = 25°C:
(all channels active)
Ta = 85°C:
Maximal switchable inductance, single pulse
Vbb = 12V, Tj,start = 150°C4),
IL = 4 A, EAS = 1.13J, 0 Ω
one channel:
IL = 12 A, EAS = 430mJ, 0 Ω
one channel:
IL = 24 A, EAS = 800mJ, 0 Ω
two parallel channels:
Vbb
Vbb
Values
Unit
43
34
V
V
IL
VLoad dump3)
self-limited
60
A
V
Tj
Tstg
Ptot
-40 ...+150
-55 ...+150
3.8
2.0
°C
100
4.4
2.0
mH
1.0
4.0
8.0
kV
-10 ... +16
±2.0
±5.0
±14
V
mA
ZL
W
see diagrams on page 10
Electrostatic discharge capability (ESD)
IN: VESD
(Human Body Model)
ST, IS:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
Input voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
Current through current sense pin (DC)
VIN
IIN
IST
IIS
see internal circuit diagram page 9
1)
2)
3)
4)
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins a 150Ω
resistor for the GND connection is recommended.
RI = internal resistance of the load dump test pulse generator
VLoad dump is set up without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air.
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BTS 840 S2
Thermal Characteristics
Parameter and Conditions
Symbol
min
Thermal resistance
junction -case
junction - ambient4)
each channel: Rthjs
one channel active: Rthja
all channels active:
Values
typ
max
Unit
1
---
K/W
Values
min
typ
max
Unit
----
-37
30
Electrical Characteristics
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT); IL = 5 A
each channel,
Tj = 25°C: RON
Tj = 150°C:
--
30
60
14
15
--
50
--
mV
11
22
12
24
--
A
--
--
8
mA
25
25
70
80
150
200
µs
dV/dton
0.1
--
1
V/µs
-dV/dtoff
0.1
--
1
V/µs
two parallel channels, Tj = 25°C:
Output voltage drop limitation at small load
currents, see page 14
IL = 0.5 A
mΩ
27
54
VON(NL)
Tj =-40...+150°C:
Nominal load current, ISO Norm
one channel active: IL(NOM)
two parallel channels active:
ISO 10483-1, 6.7: Von =0.5V Tc = 85°C
Output current while GND disconnected or pulled up5); IL(GNDhigh)
Vbb = 30 V, VIN = 0,
see diagram page 10
Turn-on time6)
Turn-off time
RL = 12 Ω
Slew rate on 6)
10 to 30% VOUT, RL = 12 Ω:
Slew rate off 6)
70 to 40% VOUT, RL = 12 Ω:
5)
6)
IN
IN
to 90% VOUT: ton
to 10% VOUT: toff
not subject to production test, specified by design
See timing diagram on page 11.
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BTS 840 S2
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Values
min
typ
max
Operating Parameters
Operating voltage7)
Undervoltage shutdown
Undervoltage restart
Vbb(on)
Vbb(under)
Tj =-40...+25°C: Vbb(u rst)
Tj =+150°C:
Undervoltage restart of charge pump
see diagram page 13
Tj =-40...+25°C: Vbb(ucp)
Tj =150°C:
Undervoltage hysteresis
∆Vbb(under)
5.0
3.2
--
--4.5
34
5.0
5.5
6.0
V
V
V
----
4.7
-0.5
6.5
7.0
--
V
Overvoltage shutdown
Overvoltage restart
Overvoltage hysteresis
Overvoltage protection8)
34
33
-41
43
----
--1
-47
8
24
--
43
---52
30
50
20
V
V
V
V
---
1.2
2.4
3
6
mA
48
40
31
56
50
37
65
58
45
A
---
24
24
---
A
--
4.0
--
ms
∆Vbb(under) = Vbb(u rst) - Vbb(under)
Vbb(over)
Vbb(o rst)
∆Vbb(over)
Tj =-40: Vbb(AZ)
Ibb=40 mA
Tj =+25...+150°C:
Standby current9)
Tj =-40°C...25°C: Ibb(off)
VIN = 0
Tj =150°C:
Leakage output current (included in Ibb(off)); VIN = 0 IL(off)
Operating current 10), VIN = 5V,
IGND = IGND1 + IGND2,
one channel on: IGND
two channels on:
Unit
V
µA
µA
Protection Functions11)
Current limit, (see timing diagrams, page 12)
Tj =-40°C: IL(lim)
Tj =25°C:
Tj =+150°C:
Repetitive short circuit current limit,
Tj = Tjt
each channel IL(SCr)
two parallel channels
(see timing diagrams, page 12)
Initial short circuit shutdown time
Tj,start =25°C: toff(SC)
(see timing diagrams on page 12)
At supply voltage increase up to Vbb= 4.7 V typ without charge pump, VOUT ≈Vbb - 2 V
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 Ω
resistor in the GND connection is recommended). See also VON(CL) in table of protection functions and
circuit diagram page 9.
9) Measured with load; for the whole device; all channels off
10) Add I , if I
ST
ST > 0
11) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not
designed for continuous repetitive operation.
7)
8)
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BTS 840 S2
Parameter and Conditions, each of the two channels
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Values
min
typ
max
Output clamp (inductive load switch off)12)
at VON(CL) = Vbb - VOUT, IL= 40 mA
Tj =-40°C: VON(CL)
Tj =25°C...150°C:
Thermal overload trip temperature
Tjt
Thermal hysteresis
∆Tjt
41
43
150
--
-47
-10
-52
---
°C
K
-Vbb
-VON
---
-600
32
--
V
mV
= -40°C, IL = 5 A: kILIS
Tj= -40°C, IL= 0.5 A:
4350
3100
4800
4800
5800
7800
4350
3800
4800
4800
5350
6300
5.4
6.1
6.9
V
IIS(LL)
IIS(LH)
IIS(SH) 16)
0
0
0
----
1
15
10
µA
tson(IS)
--
--
300
µs
Reverse Battery
Reverse battery voltage 13)
Drain-source diode voltage (Vout > Vbb)
IL = - 4.0 A, Tj = +150°C
Symbol
Unit
V
Diagnostic Characteristics
Current sense ratio14), static on-condition,
VIS = 0...5 V, Vbb(on) = 6.515)...27V,
Tj
kILIS = IL / IIS
Tj= 25...+150°C, IL= 5 A:
Tj= 25...+150°C, IL = 0.5 A:
Current sense output voltage limitation
Tj = -40 ...+150°C
IIS = 0, IL = 5 A:
Current sense leakage/offset current
Tj = -40 ...+150°C
VIN=0, VIS = 0, IL = 0:
VIN=5 V, VIS = 0, IL = 0:
VIN=5 V, VIS = 0, VOUT = 0 (short circuit)
Current sense settling time to IIS static±10% after
positive input slope16), IL = 0
5A
12)
13)
14)
15)
16)
VIS(lim)
If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
VON(CL)
Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Power dissipation is higher compared to normal operating
conditions due to the voltage drop across the drain-source diode. The temperature protection is not active
during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and
circuit page 9).
This range for the current sense ratio refers to all devices. The accuracy of the kILIS can be raised at least by
a factor of two by matching the value of kILIS for every single device.
In the case of current limitation the sense current IIS is zero and the diagnostic feedback potential VST is
High. See figure 2c, page 12.
Valid if Vbb(u rst) was exceeded before.
not subject to production test, specified by design
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BTS 840 S2
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Values
min
typ
max
Unit
Current sense settling time to 10% of IIS static after
negative input slope17) , IL = 5
0A
tsoff(IS)
--
30
100
µs
Current sense rise time (60% to 90%) after change
of load current17) , IL = 2.5
tslc(IS)
5A
--
10
--
µs
VOUT(OL)
2
3
4
V
RO
5
15
40
kΩ
RI
3.0
4.5
7.0
kΩ
VIN(T+)
VIN(T-)
∆ VIN(T)
IIN(off)
IIN(on)
td(ST OL3)
-1.5
-1
20
--
--0.5
-50
400
3.5
--50
90
--
V
V
V
µA
µA
µs
tdon(ST)
--
13
--
µs
tdoff(ST)
--
1
--
µs
5.4
----
6.1
----
6.9
0.4
0.7
2
V
Open load detection voltage18) (off-condition)
Internal output pull down
(pin 16,17,18,19 to 2 resp. 12,13,14,15 to 6), VOUT=5 V
Input and Status Feedback19)
Input resistance
(see circuit page 9)
Input turn-on threshold voltage
Input turn-off threshold voltage
Input threshold hysteresis
Off state input current
VIN = 0.4 V:
On state input current
VIN = 5 V:
Delay time for status with open load
after Input neg. slope (see diagram page 14)
Status delay after positive input slope17)
Status delay after negative input slope17)
Status output (open drain)
Zener limit voltage Tj =-40...+150°C, IST = +1.6 mA: VST(high)
ST low voltage
Tj =-40...+25°C, IST = +1.6 mA: VST(low)
Tj = +150°C, IST = +1.6 mA:
Status leakage current, VST = 5 V,
Tj=25 ... +150°C: IST(high)
µA
17)
not subject to production test, specified by design
External pull up resistor required for open load detection in off state.
19) If ground resistors R
GND are used, add the voltage drop across these resistors.
18)
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BTS 840 S2
Truth Table
Input 1
Output 1
Status 1
Input 2
Output 2
Status 2
level
level
level
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
L20)
L
L
H
H
H
L
H
H
H
H
H
H
L21)
L
H (L24))
L
H
L
H
L
H
Normal
operation
Currentlimitation
Short circuit to
GND
Overtemperature
Short circuit to
Vbb
Open load
Undervoltage
Overvoltage
L23)
H
L
L
L
L
L
Current
Sense 1
Current
Sense 2
IIS
0
nominal
0
0
0
0
0
0
0
<nominal 22)
0
0
0
0
0
0
0
Negative output
voltage clamp
L = "Low" Level
X = don't care
Z = high impedance, potential depends on external circuit
H = "High" Level
Status signal after the time delay shown in the diagrams (see fig 5. page 13)
Parallel switching of channel 1 and 2 is possible by connecting the inputs and outputs in parallel. The status
outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor. The current
sense outputs IS1 and IS2 have to be connected with a single pull-down resistor.
Terms
V
Ibb
bb
I IN1
Leadframe
3
I ST1
4
I IS1
IN1
ST1
V
V
IN1 ST1
IS1
V IS1 5
R
VON1
Vbb
OUT1
17,18
I L1
Leadframe
7
I ST2
PROFET
Chip 1
8
I IS2
GND1
VOUT1
2
GND1
I IN2
I
GND1
IN2
ST2
V
V
IN2 ST2
IS2
V IS2 9
VON2
Vbb
OUT2
13,14
I L2
PROFET
Chip 2
GND2
R
GND2
VOUT2
6
I
GND2
Leadframe (Vbb) is connected to pin 1,10,11,20
External RGND optional; two resistors RGND1, RGND2 = 150 Ω or a single resistor RGND = 75 Ω for reverse
battery protection up to the max. operating voltage.
20)
21)
22)
23)
24)
The voltage drop over the power transistor is Vbb-VOUT > 3V typ. Under this condition the sense current IIS is
zero
An external short of output to Vbb, in the off state, causes an internal current from output to ground. If RGND
is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious.
Low ohmic short to Vbb may reduce the output current IL and therefore also the sense current IIS.
Power Transistor off, high impedance
with external resistor between VBB and OUT
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BTS 840 S2
Input circuit (ESD protection), IN1 or IN2
Inductive and overvoltage output clamp,
OUT1 or OUT2
R
IN
I
+Vbb
VZ
ESD-ZD I
I
I
V
GND
ON
OUT
The use of ESD zener diodes as voltage clamp at DC
conditions is not recommended.
Status output, ST1 or ST2
Power GND
VON clamped to VON(CL) = 47 V typ.
+5V
R ST(ON)
Overvoltage and reverse batt. Protection
ST
For each channel
+ 5V
ESDZD
GND
+ Vbb
R ST
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 375 Ω
at 1.6 mA. The use of ESD zener diodes as voltage clamp at
DC conditions is not recommended.
V
IN
RI
Logic
ST
RV
Z2
IS
OUT
R IS
V
Current sense output, IS1 or IS2
PROFET
Z1
GND
R GND
V
IS
Signal GND
IS
R
Load GND
VZ1 = 6.1 V typ., VZ2 = 47 V typ., RGND = 150 Ω,
RST=15kΩ, RI=4.5kΩ typ., RIS=1kΩ, RV=15kΩ,
In case of reverse battery the current has to be limited
by the load. Temperature protection is not active
I
IS
ESD-ZD
R Load
IS
GND
Open-load detection OUT1 or OUT2
ESD-Zener diode: 6.1 V typ., max 14 mA;
RIS = 1 kΩ nominal
OFF-state diagnostic condition:
VOUT > 3 V typ.; IN low
V
R
bb
EXT
OFF
Out
ST
Logic
R
V
OUT
O
Signal GND
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BTS 840 S2
Inductive load switch-off energy
dissipation, each channel
GND disconnect, each channel
E bb
E AS
Vbb
IN
IN
OUT
PROFET
ST
PROFET
GND
V
bb
V
IN
V
ELoad
Vbb
=
L
ST
V
GND
ST
OUT
GND
ZL
{
R
Any kind of load. In case of IN = high is VOUT ≈ VIN - VIN(T+).
Due to VGND > 0, no VST = low signal available.
L
2
EL = 1/2·L·I L
each channel
While demagnetizing load inductance, the energy
dissipated in PROFET is
EAS= Ebb + EL - ER= VON(CL)·iL(t) dt,
Vbb
IN
PROFET
with an approximate solution for RL > 0 Ω:
OUT
EAS=
ST
GND
V
bb
ER
Energy stored in load inductance:
GND disconnect with GND pull up
V
EL
V
IN ST
V
IL· L
(V + |VOUT(CL)|)
2·RL bb
ln (1+ |V
IL·RL
OUT(CL)|
)
Maximum allowable load inductance for
a single switch off (one channel)4)
GND
L = f (IL ); Tj,start = 150°C, Vbb = 12 V, RL = 0 Ω
Any kind of load. If VGND > VIN - VIN(T+) device stays off
Due to VGND > 0, no VST = low signal available.
ZL [mH]
100
Vbb disconnect with energized inductive
load, each channel
high
10
Vbb
IN
PROFET
OUT
ST
GND
1
V
bb
For inductive load currents up to the limits defined by ZL
(max. ratings and diagram on page 10) each switch is
protected against loss of Vbb.
0.1
Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load all the load current
flows through the GND connection.
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4
6
8
10
12 14
16 18
20
22
24
IL [A]
2003-Oct-01
BTS 840 S2
Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and
channel 2
Figure 1a: Switching a resistive load,
change of load current in on-condition:
Figure 2a: Switching a resistive load,
turn-on/off time and slew rate definition:
IN
IN
ST
t don(ST)
VOUT
t doff(ST)
90%
VOUT
t on
t on
IL
dV/dtoff
t off
t slc(IS)
Load 1
dV/dton
t slc(IS)
10%
t
off
IL
Load 2
IIS
t son(IS)
t soff(IS)
t
t
The sense signal is not valid during settling time after turn or
change of load current.
Figure 2b: Switching a lamp:
Figure 1b: Vbb turn on:
IN1
IN
IN2
ST
V bb
V
V
OUT1
V
OUT
OUT2
I
ST1 open drain
t
ST2 open drain
t
The initial peak current should be limited by the lamp and not by
the current limit of the device.
proper turn on under all conditions
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2003-Oct-01
BTS 840 S2
Figure 2c: Switching a lamp with current limit:
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
IN
IN1
ST
I
other channel: normal operation
L1
I
VOUT
L(lim)
I
IL
L(SCr)
t
off(SC)
IS 1 = 0
IIS
ST 1
t
t
Heating up of the chip may require several milliseconds, depending
on external conditions
Figure 2d: Switching an inductive load
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
IN
IN1/2
ST
I
L1
+I
L2
2xIL(lim)
V
OUT
I
I
L(SCr)
L
I L(OL)
t
t
off(SC)
S 1= IS 2 = 0
*) if the time constant of load is too large, open-load-status may
occur
ST 1/2
t
ST1 and ST2 have to be configured as a 'Wired OR' function
ST1/2 with a single pull-up resistor.
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BTS 840 S2
Figure 6a: Undervoltage:
Figure 4a: Overtemperature:
Reset if Tj <Tjt
IN
IN
not defined
ST
ST
V
bb
IL
Vbb(u cp)
V
bb(under)
I
I IS
TJ
Vbb(u rst)
L
IIS
t
t
Figure 6b: Undervoltage restart of charge pump
Figure 5a: Open load: detection (with REXT),
turn on/off to open load
VON(CL)
Von
IN
td(ST OL3)
ST
offstate
on-state
V
VOUT
V
bb(u rst)
V
I
L
open load
I IS
V
V
offstate
bb(over)
bb(o rst)
bb(u cp)
bb(under)
V bb
t
charge pump starts at Vbb(ucp) =4.7 V typ.
Infineon technologies
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BTS 840 S2
Figure 7a: Overvoltage:
Figure 8b: Current sense ratio:
IN
15000
k ILIS
ST
VON(CL)
Vbb
V
bb(over)
V
bb(o rst)
10000
IL
5000
I IS
t
[A] I L
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Figure 8a: Current sense versus load current25::
1.3
[mA]
1.2
Figure 9a: Output voltage drop versus load current:
I IS
1.1
VON
[V]
1
0.9
0.2
0.8
RON
0.7
0.6
0.5
0.4
0.1
0.3
0.2
0.1
IL
0
0
1
2
3
4
VON(NL)
5 [A] 6
IL
0.0
25
This range for the current sense ratio refers to all
devices. The accuracy of the kILIS can be raised at
least by a factor of two by matching the value of
kILIS for every single device.
Infineon technologies
14
0
1
2
3
4
5
6
7 [A] 8
2003-Oct-01
BTS 840 S2
Package and Ordering Code
Published by
Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81669 München
© Infineon Technologies AG 2001
All Rights Reserved.
Standard: P-DSO-20-12 (Power SO 20)
Sales Code
BTS 840
Ordering Code
Q67060-S7013
All dimensions in millimetres
Attention please!
The information herein is given to describe certain components and
shall not be considered as a guarantee of characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited
to warranties of non-infringement, regarding circuits, descriptions
and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions
and prices please contact your nearest Infineon Technologies Office
in Germany or our Infineon Technologies Representatives worldwide
(see address list).
Warnings
Due to technical requirements components may contain dangerous
substances. For information on the types in question please contact
your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support
devices or systems with the express written approval of Infineon
Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system, or
to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the
human body, or to support and/or maintain and sustain and/or
protect human life. If they fail, it is reasonable to assume that the
health of the user or other persons may be endangered.
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2003-Oct-01