INFINEON TLF50251EL

TLF50251EL
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Data Sheet
Rev. 1.0, 2013-06-19
Automotive Power
2.2 MHz Step-Down Regulator 500 mA, 5 V
Low quiescent current
TLF50251EL
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TLF50251EL
Overview
500 mA step down voltage regulator
5 V Output voltage
± 2% output voltage tolerance
Low quiescent current (less than 45µA at nominal battery voltage)
Integrated power transistor
Current mode PWM regulation
PFM mode for light load current
Input voltage range from 4.75V to 45V
2.2 MHz switching frequency
100% Duty cycle
Synchronization input
Very low shutdown current consumption (<2 µA)
Soft-start function
Reset generator
Input undervoltage lockout
Suited for automotive applications: Tj = -40 °C to +150 °C
Green Product (RoHS compliant)
AEC Qualified
PG-SSOP-14
Description
The TLF50251EL is a high frequency PWM step-down DC/DC converter with an integrated PMOS power switch,
packaged in a small PG-SSOP-14 with exposed pad. The wide input voltage range from 4.75 to 45 V makes the
TLF50251EL suitable for a wide variety of applications. The device is designed to be used under harsh automotive
environmental conditions.
The switching frequency of nominal 2.2 MHz allows the use of small and cost-effective inductors and capacitors,
resulting in a low, predictable output voltage ripple and in minimized consumption of board space.
In light load condition the device operates in Pulse Frequency Modulation (PFM) to optimize the efficiency.
Between the single pulses, all internal controlling circuitry is switched off to reduce the internal power consumption.
Type
Package
Marking
TLF50251EL
PG-SSOP-14
TLF50251
Data Sheet
2
Rev. 1.0, 2013-06-19
TLF50251EL
Overview
The TLF50251EL includes protection features such as a cycle-by-cycle current limitation, over-temperature
shutdown and input under voltage lockout. The enable function, in shutdown mode with less than 2 µA current
consumption, enables easy power management in battery-powered systems.
The voltage regulation loop provides an excellent line and load regulation, the stability of the loop is ensured by
an internal compensation network. This compensation network combined with a current mode regulation control
guarantees a highly effective line transient rejection. During start-up the integrated soft-start limits the inrush
current peak and prevents from an output voltage overshoot.
Data Sheet
3
Rev. 1.0, 2013-06-19
TLF50251EL
Block Diagram
2
Block Diagram
VS
13
TLF50251EL
Over
Temperature
Shutdown
EN
Enable
14
Buck
Converter
FREQ
5
SYNC
4
11
SWO
Oscillator
INT.
SUPPLY
Bandgap
Reference
7
FB
6
RTADJ
1
RO
Soft Start
Ramp
Generator
Figure 1
Data Sheet
N.C.
3
N.C.
2
Reset
Generator
8
9
10
12
N.C.
GND
GND
N.C.
Block Diagram
4
Rev. 1.0, 2013-06-19
TLF50251EL
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
RO
1
N .C .
TLF50251E L
14
EN
2
13
VS
N .C .
3
12
N .C .
S YN C
4
11
SW O
FR E Q
5
10
GND
R TA D J
6
9
GND
FB
7
8
N .C .
P G -S SO P 14
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol Function
1
RO
Reset Output
Provides the reset output signal. Open collector output, connect a pull up resistor to VCC or
another voltage source, if feature is used, if not, leave open.
2
N.C.
Not Connected.
Internally not connected. Leave open or connect to GND.
3
N.C.
Not Connected.
Internally not connected. Leave open or connect to GND.
4
SYNC
Synchronization Input
Connect to an external clock signal in order to synchronize/adjust the switching frequency. This
feature is not functionally in PFM mode.
5
FREQ
Frequency Adjustment Pin
Connect an external resistor to GND to adjust the switching frequency, do not leave open. In
case the synchronization option is used, the resistor must be dimensioned close to the desired
synchronization frequency.
6
RTADJ
Reset Threshold Adjust Pin
Connect an external resistor divider to adjust the Reset threshold. If function is not used, connect
to VCC .
7
FB
Feedback Input
Connect this pin directly to the output capacitor. Also input for internal power supply. The internal
power supply is taken from the output voltage.
8
N.C.
Not Connected.
Internally not connected. Leave open or connect to GND.
9
GND
Ground
Connect this pin directly with low inductive and broad trace to ground, do not leave open.
Data Sheet
5
Rev. 1.0, 2013-06-19
TLF50251EL
Pin Configuration
Pin
Symbol Function
10
GND
Ground
Connect this pin directly with low inductive and broad trace to ground, do not leave open.
11
SWO
Buck Switch Output
Drain of the integrated power-PMOS transistor. Connect directly to the cathode of the catch
diode and the buck circuit inductance.
12
N.C.
Not Connected.
Internally not connected. Leave open or connect to GND.
13
VS
Supply Voltage Input
Connect to supply voltage source.
14
EN
Enable Input
Switch to high level to enable the device, switch to low level to disable the device.
Exposed Pad
Data Sheet
Connect to heatsink area and GND by low inductance wiring.
6
Rev. 1.0, 2013-06-19
TLF50251EL
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Unit
Conditions
Max.
Voltages
4.1.1
Enable input
4.1.2
Synchronization input
VEN
VSYNC
-40
45
V
–
-0.3
5.5
V
–
6.2
V
t < 10s 2)
5.5
V
–
6.2
V
t < 10s 2)
5.5
V
–
6.2
V
t < 10s 2)
5.5
V
–
6.2
V
t < 10s 2)
5.5
V
–
6.2
V
t < 10s 2)
4.1.3
4.1.4
Reset threshold adjust pin
VRTADJ
-0.3
4.1.5
4.1.6
Reset output
VRO
-0.3
4.1.7
4.1.8
Feedback Input
VFB
-0.3
4.1.9
4.1.10
Frequency adjustment pin
VFREQ
-0.3
4.1.11
4.1.12
Buck switch output
4.1.13
Supply voltage input
VSWO
VVS
-2.0
VVS + 0.3
V
–
-0.3
45
V
–
Tj
Tstg
-40
150
°C
–
-55
150
°C
–
VESD
VESD
VESD
-2
2
kV
HBM
-500
500
V
CDM 3)
-750
750
V
CDM 3)
Temperatures
4.1.14
Junction temperature
4.1.15
Storage temperature
ESD Susceptibility
4.1.16
ESD resistivity
4.1.17
ESD resistivity to GND
4.1.18
ESD resistivity corner pins to GND
1) Not subject to production test, specified by design
2) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001.
3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
7
Rev. 1.0, 2013-06-19
TLF50251EL
General Product Characteristics
4.2
Functional Range
Pos.
Parameter
Symbol
4.2.1
Supply voltage
4.2.2
Buck inductor
4.2.3
Buck capacitor
4.2.4
Buck capacitor ESR
4.2.5
Junction temperature
VS
LBU
CBU1
ESRBU1
Tj
Limit Values
Unit
Conditions
Min.
Max.
4.75
45
V
–
3.3
22
µH
–
10
50
µF
–
0.015
0.100
Ω
– 1)
-40
150
°C
–
1) See section ““Application Information” on Page 26” for loop compensation requirements and refer to Application Note
for dimensioning the output filter.
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Pos.
Parameter
Symbol
4.3.1
Junction to case1)
RthJC
RthJA
RthJA
RthJA
4.3.2
Junction to ambient
4.3.3
4.3.4
1) 2)
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
10
–
K/W
–
–
47
–
K/W
2s2p
–
54
–
K/W
1s0p + 600 mm2
–
64
–
K/W
1s0p + 300 mm2
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink
area at natural convection on FR4 board.
Data Sheet
8
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
5
Buck Regulator
5.1
Description
The TLF50251EL is a monolithic current mode step down converter with adjustable switching frequency fOSC. It
is capable to operate either in Pulse Width Modulation (PWM) or in Pulse Frequency Modulation (PFM) Mode.
5.1.1
Regulator Loop
Power stage:
The supply voltage is connected to pin VS. Between pin VS and pin SWO there is an internal shunt resistor and
the internal PMOS power stage. The PMOS is driven by the driver stage.
Regulator Block:
The feedback signal VFB is connected to pin FB. Between pin FB and pin GND is an internal resistor divider. An
error amplifier and a comparator are connected to this resistor divider: the error amplifier EA-gmV, which is
controlling the output voltage in PWM mode, and the PFM comparator, which will switch the TLF50251EL into PFM
mode and trigger the pulses. The error amplifier EA-gmV is connected to the PWM comparator. The regulation
loop operates in current mode: the output current of EA-gmV is subtracted from the sum of the current loop CSgmI and the slope compensation ISLOPE. The result is evaluated by PWM Comp (a current comparator). The output
of PWM Comp defines duty cycle (pulse-width-modulated signal) in PWM mode.
The Slope Compensation added to the signal from the error amplifier EA-gmV to the PWM Comparator ensures
that no sub harmonics will occur on the input current.
The PWM comparator output and the PFM comparator output are connected to the PWM /PFM logic.
An external resistor at pin FREQ is required to set the switching frequency (for details please refer to chapter 8
Module Oscillator). The TLF50251EL may also be synchronized to an external frequency. In this case an external
clock signal should be connected to pin SYNC. The frequency setting resistor at pin FREQ is still necessary, it has
to be selected according to the desired synchronization frequency (for details please refer to chapter 8 Module
Oscillator).
The TLF50251EL can only be synchronized to an external frequency source in PWM mode, this function does not
work in PFM mode.
The clock manager is clocking the PWM/PFM logic. The PWM/PFM logic is triggering the driver to apply pulses to
the internal PMOS power stage.
Safety Features:
The shunt resistor in line with the internal PMOS power stage (between pin VS and the power stage) is connected
to a current sense amplifier CS-gml. It detects the voltage above the shunt resistor. The amplifier creates a signal
which shuts the pulse down in case that the shunt voltage exceeds the reference limit. The current limitation acts
as a cycle-by-cycle limitation. Cycle-by-cycle limitation means, that every pulse is switched off as soon as the
current through the PMOS exceeds the buck peak over current limit IBUOC. The next pulse starts and will also be
switched off as soon as the current limit is exceeded again. This results in a lowered output voltage whilst the
output current is limited to a certain value.
Data Sheet
9
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
Input undervoltage shutdown: If the input voltage is below the input undervoltage shutdown threshold VS,off the
device will shut down.
Output overvoltage protection: if the output voltage exceeds the PFM threshold the device will switch from PWM
to PFM. Pulses will then be generated only depending on the value of the output voltage VCC.
Soft start function: an integrated soft start function of duration tstart ensures, that the inrush current will be limited.
After an over-temperature shutdown the regulator always restarts with a soft start.
Over-temperature shutdown: an internal temperature sensor detects the temperature of the device. It will be
switched off if the junction temperature exceeds the over temperature shutdown threshold Tj,sd and restart with a
certain hysteresis Tj,sd_hyst (for details please refer to Chapter 7, Enable and Thermal Shutdown).
Biasing:
The internal biasing is taken from pin VS as well as from pin FB (connected to VCC) (for details please refer to
Chapter 7, Enable and Thermal Shutdown). Thus the power consumption from the supply voltage VS can be
minimized.
VS
+
VBG
CS-gmI
PFM
Comparator
+
FB
-
+
-
PWM Comp
EA-gmV
PWM
PFM
Logic
GateD
Driver
SWO
SYNC_IN
FREQ
Clock
Manager
CK_A
SoftStart
Slope
Comp.
CLK
GND
Figure 3
Data Sheet
Block Diagram Buck Regulator
10
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
5.1.2
PWM (Pulse Width Modulation) Mode
Under normal conditions the TLF50251EL will operate with a constant switching frequency fOSC in PWM mode.
The ratio between switch-on-time TON and switch-off-time TOFF is mainly determined by the ratio between the input
voltage VS and the output voltage VCC and is influenced by the output current ICC.
In PWM mode the device may operate with 100% duty cycle, in this case the internal PMOS is constantly
conducting current. The current limitation feature is operating under this condition.
If the switch-on-time TON should theoretically be below the minimum threshold TON,min (due to low load or due to
the ratio between input voltage VS and output voltage VCC depending on the switching frequency), it will be reduced
to the minimum value switch-on-time TON,min and stay there. As a consequence the output voltage VCC will
increase. The PFM comparator detects the PFM threshold and will then switch the device into PFM mode. There
is no possibility to disable the PFM function.
5.1.3
PFM (Pulse Frequency Modulation) Mode
To optimize the efficiency and to reduce the current consumption, the TLF50251EL automatically switches to PFM
mode under low load conditions. In PFM mode the internal power stage including the driver stage is switched off
and will only be switched on for applying pulses to charge the output capacitor. The pulses will be created by
monitoring the voltage of the output filter capacitor COUT. Thus in PFM mode the repetition time of pulses depend
on the output current and/or the ratio between input voltage VS and output voltage VCC.
Transition from PWM to PFM:
Figure 4 is showing the transition from Pulse Width Modulation to Pulse Frequency Modulation under the
assumption, that the input voltage VS will be constant and only the output current ICC will vary. The diagram shows
the principle, in reality the signals might look slightly different. The diagram is without scale in respect of time,
voltage and current values.
Starting from left of the figure a certain output current, here named i1, is applied to the regulator output. This results
in a duty cycle D1 with the on-time TON1 of the internal power stage. The switching frequency fOSC is constant as
set by the frequency setting resistor RFREQ. The regulator is in PWM mode, the output voltage is VREF_PWM which
is equal to VFB in PWM mode.
At point t1 the output current decreases from i1 to a lower i2. This results in a duty cycle D2 with the on-time TON2
of the internal power stage. Due to the reduced output load the on-time TON2 is shorter (the regulator is in
Discontinuous Conduction Mode DCM) than TON1. The switching frequency fOSC is constant as set by the
frequency setting resistor RFREQ. The regulator is still in PWM mode, the output voltage is VREF_PWM which is equal
to VFB in PWM mode. In Continuous Conduction Mode CCM the variation from TON1 to TON2 will be very small due
to smaller conduction losses.
At point t2 the output current decreases again from i2 to a lower i3. As a consequence the on-time TON will be
reduced also. The output current i3 is so low, that the on-time TON3 would be smaller than the TON,min. The regulator
does not allow a on-time smaller than TON,min. Therefore we can say that the output current i3 is under the
imaginary current threshold for transition from PWM to PFM iPWM/PFM. With the pulse staying at on-time TON,min the
output voltage VCC will rise. The regulator is still in PWM mode, but the output voltage rises.
Data Sheet
11
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
At point t3 after a normal time period TPWM as adjusted by the frequency setting resistor RFREQ, a further pulse of
the duration TON,min is applied, the output voltage VCC keeps on rising. The regulator is still in PWM mode.
At point t4 the output voltage VCC touches (or exceeds) the voltage threshold for transition from PWM to PFM
VPWM/PFM. The regulator is now switching internally from PWM to PFM. In PFM mode the power consumption of
the internal blocks is reduced. The reference for the output voltage VCC is switched from VREF_PWM (which is equal
to VFB in PWM mode) to VREF_PFM (which is equal to VFB in PFM mode). The reference for VFB in PFM mode is
higher than the reference in PWM mode to avoid voltage dumps at the output voltage VCC due to sudden load
steps and to give the regulator more reaction time to switch back to PWM mode.
The regulator is now in PFM mode, the output voltage is VREF_PFM which is equal to VFB (or slightly higher) in PFM
mode.
Output current
The output voltage VCC is monitored and as soon as it touches the PFM reference voltage VREF_PFM a pulse of the
on-time TON,min is triggered. The time between two pulses is depending on the discharging of the output capacitor
COUT.
i1
i2
iPWM/PFM
i3
Switching signal
time
D1
D2
D3
TON2
TON1
TON,min
time
TPWM
Output voltage
TPWM
TPWM
Switch to PFM mode
VPWM/PFM
VREF_PFM
VREF_PWM
time
t1
Figure 4
Data Sheet
t2
t3
t4
PWM to PFM Transition (Timing Diagram)
12
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
Transition from PFM to PWM:
Figure 5 is showing the transition from Pulse Frequency Modulation to Pulse Width Modulation under the
assumption, that the input voltage VS will be constant, and only the output current ICC will vary. The diagram shows
the principle, in reality the signals might look slightly different. The diagram is without scale in respect of time,
voltage and current values.
Starting from left of the figure a certain output current, here named i3, is applied to the regulator output. i3 shall be
below the imaginary current threshold for transition from PFM to PWM iPFM/PWM. The regulator is in PFM mode,
the output voltage is VREF_PFM, which is equal to VFB in PFM mode (or slightly higher).
Pulses of the duration TON,min are triggered whenever the output voltage VCC touches the PFM reference voltage
VREF_PFM.
At point t5 the output current increases from i3 to a higher i2, that shall be above the imaginary current threshold
for transition from PFM to PWM iPFM/PWM. Due to the higher output current more pulses of the duration TON,min have
to be triggered, the frequency of these pulses is monitored. The frequency of these pulses increases until it is
higher than the switching frequency fOSC set by the frequency setting resistor RFREQ. The regulator is still in PFM
mode
Output current
At point t6 the frequency monitoring detects that the frequency of the PFM pulses is being higher than the
frequency threshold for transition from PFM to PWM fPFM/PWM. Therefore the regulator switches back to PWM
mode. This results in a certain duty cycle D2 with the on-time TON2 of the internal power stage. The time period
TPWM is as adjusted by the frequency setting resistor RFREQ.
i2
iPFM/PWM
i3
Switching signal
time
D2
TON,min
TON,min
TPWM
TON2
Output voltage
time
Switch to PWM mode
VPWM/PFM
VREF_PFM
VREF_PWM
time
t5
Figure 5
Data Sheet
t6
PFM to PWM Transition (Timing Diagram)
13
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
Frequency Variation during PWM/PFM Transition:
Figure 6 is showing the transition from Pulse Frequency Modulation to Pulse Width Modulation (and vice versa)
in relation to output current and switching frequency. The diagram shows the principle, in reality the signals might
be slightly different. The diagram is without scale in respect of frequency and current values.
The transition from PWM to PFM is shown in a grey line. Starting from right the switching frequency fPWM is
constant as set by the frequency setting resistor RFREQ. The output current ICC is decreasing.
As soon as the output current ICC is below the imaginary current threshold for transition from PWM to PFM
iPWM/PFM, the regulator will be switched from PWM to PFM mode depending on the output voltage VCC. With the
output current ICC decreasing, the switching frequency will also decrease, as the pulses are triggered by
monitoring the output voltage VCC at capacitor COUT.
The transition from PFM to PWM is shown in a black line. Starting from left the switching frequency is increasing
with the increasing output current ICC.
As soon as the switching frequency is crossing the frequency threshold for transition from PFM to PWM fPFM/PWM
(which is above the switching frequency fOSC set by the frequency setting resistor RFREQ) the regulator will switch
from PFM to PWM.
Switching Frequency (log.scale)
t
PWM to PFM
PFM to PWM
fPFM/PWM
fPWM
iPWM/PFM
Figure 6
Data Sheet
iPFM/PWM
Output Current
(log.scale)
PWM <-> PFM Transitions
14
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
5.2
Electrical Characteristics
Electrical Characteristics: Buck Regulator
VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified)
Pos.
5.2.1
Parameter
Output voltage
Symbol
VFB
Limit Values
Min.
Typ.
Max.
4.90
5.00
5.10
Unit
Conditions
V
VEN = 5.0V
7 V < VS < 12V
100 mA < ICC < 610 mA
PWM Mode
5.2.2
Output voltage
VFB
4.90
5.10
5.30
V
VEN = 5.0V
10V < VS < 35V
ICC = 100 µA
PFM Mode
5.2.3
Power stage on-resistance
Ron
–
1.5
2.3
Ω
tested at 100 mA,
VS = 7.0V
–
5.2.4
Buck peak over current limit
IBUOC
0.85
–
1.7
A
5.2.5
Current transition rise/fall time
–
100
–
mA/ns
1)
5.2.6
Maximum duty cycle
–
–
100
%
2)
5.2.7
Minimum switch on-time
–
100
–
ns
1)
5.2.8
Minimum switch off- Time
–
200
–
ns
1)
5.2.9
Soft start ramp
tR
Dmax
TON,min
TOFF,min
tstart
300
450
750
µs
5.2.10
Input under voltage shutdown
threshold
VS,off
3.75
–
–
V
VFB rising from 5% to
95% of VFB,nom
VS decreasing
5.2.11
Input voltage startup threshold
–
–
4.75
V
VS increasing
5.2.12
Input under voltage shutdown
hysteresis
VS,on
VS,hyst
130
300
–
mV
–
5.2.13
Voltage threshold for transition
from PWM to PFM
VPWM/PFM –
–
5.3
V
1)
5.2.14
Frequency ratio for transition from
PFM to PWM
fPFM/PWM/ –
fosc
1.20
–
–
1)
PFM mode
1) Specified by design. Not subject to production test.
2) Consider “Chapter 4.2, Functional Range”.
Data Sheet
15
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
5.3
Performance Graphs
Typical Performance Characteristics
Load Regulation PWM Mode
VS = 12 V; TJ = + 25°C
5,100
5,075
5,075
5,050
5,050
5,025
5,025
650
50
550
4,900
450
4,900
650
4,925
550
4,925
450
4,950
350
4,950
250
4,975
150
4,975
350
5,000
250
5,000
150
VFB (V)
5,100
50
VFB (V)
Load Regulation PWM Mode
VS = 12 V; TJ = - 43 °C
Icc (mA)
Icc (mA)
Load Regulation PWM Mode
VS = 12 V; TJ = + 150°C
5,100
5,075
5,050
VFB (V)
5,025
5,000
4,975
4,950
4,925
650
550
450
350
250
150
50
4,900
Icc (mA)
Data Sheet
16
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
Typical Performance Characteristics
Line Regulation PFM Mode
Line Regulation PFM Mode
ICC = 100 µA; TJ = + 25°C
5,128
5,112
5,112
5,096
5,096
5,08
5,08
45
40
35
Power Stage On Resistance: Black TJ = + 25°C
Light Grey TJ = - 43 °C, Dark Grey TJ = + 150 °C
Line Regulation PFM Mode
ICC = 100 µA; TJ = + 150°C
1,400
5,128
5,112
1,200
5,096
1,000
5,08
VS - Vswo (V)
5,064
5,048
0,800
0,600
0,400
5,032
5,016
0,7
0,6
0,5
0,4
0,3
VS (V)
0,2
0,000
45
40
35
30
25
20
15
10
5
5
0,1
0,200
0
VFB (V)
30
VS (V)
VS (V)
Data Sheet
25
45
5
5
40
5
35
5,016
30
5,016
25
5,032
20
5,032
15
5,048
10
5,048
20
5,064
15
5,064
10
VFB (V)
5,128
5
VFB (V)
ICC = 100 µA; TJ = - 43°C
Iswo(A)
17
Rev. 1.0, 2013-06-19
TLF50251EL
Buck Regulator
Efficiency for
VS = 13 V, fOSC = 1.65 MHz, LOUT = 4.7 µH
Efficiency for
VS = 13 V, fOSC = 1.65 MHz, LOUT = 10 µH
90,00%
90,00%
80,00%
80,00%
70,00%
70,00%
60,00%
60,00%
50,00%
50,00%
40,00%
40,00%
30,00%
30,00%
20,00%
20,00%
10,00%
0,00%
10,00%
0
100
200
300
400
ICC (mA)
500
0
600
100
200
300
400
500
ICC (mA)
Efficiency for
Efficiency for
VS = 13 V, fOSC = 2.2 MHz, LOUT = 4.7 µH
VS = 13 V, fOSC = 2.2 MHz, LOUT = 10 µH
90,00%
90,00%
80,00%
80,00%
600
70,00%
70,00%
60,00%
60,00%
50,00%
50,00%
40,00%
40,00%
30,00%
30,00%
20,00%
20,00%
10,00%
0,00%
10,00%
0
Data Sheet
100
200
300
400
ICC (mA)
500
0
600
18
100
200
300
ICC (mA)
400
500
600
Rev. 1.0, 2013-06-19
TLF50251EL
Reset
6
Reset
6.1
Description Reset Function
Principle:
The reset function supervises the value of the regulator output voltage VCC. The result is monitored by the status
of pin RO. A high level at pin RO means that the output voltage VCC is above the desired reset threshold. A low
level at pin RO means that the output voltage VCC is below the desired reset threshold. The reset function does
not work, if the supply (VFB) voltage is below 1 V.
Adjustment of reset threshold:
The reset generator consists of an internal comparator with a reset threshold VRO,T. By adding an external resistor
divider between the output voltage VCC and ground (GND) and connecting the point between the upper (R1) and
lower (R2) resistor to pin RTADJ the desired reset threshold VRT (where the reset generator indicates an under
voltage) might be adjusted.
If reset function is not used please connect pin RTADJ to VCC.
+ R2-⎞ = V
Desired reset threshold = V RO, T ⎛ R1
-------------------RT
⎝ R2 ⎠
Operation mode (please refer to Figure 7):
The reset generator starts operating as soon as the regulator is activated by supplying the device with an input
(battery) voltage higher than the input voltage startup threshold VS,ON and a valid high signal VEN,hi at pin EN.
The pin RO is low at this time.
When the regulator starts to operate, VCC ramps up and passes the desired reset threshold. The reset delay time
tRD is the time duration between that point and pin RO turning to high level.
The reset reaction time tRR is the maximum duration or time, the output voltage VCC may dip below the desired
reset threshold, before a reset is indicated and pin RO is pulled to low level. This is implemented to avoid wrong
reset triggering by short “glitches” on the output voltage VCC. If the output voltage VCC dips below the desired reset
threshold VRT for more than tRR , tRR is also the time until pin RO is pulled below VRO,L.
A voltage dip at the output voltage VCC leads to a low level at pin RO under the following condition:
+ R2-⎞ ( for t > t )
V CC < V RO, T ⎛ R1
-------------------RR
⎝ R2 ⎠
In case the pin RO is pulled to low level, it stays low for the time until the output voltage VCC is higher than the
desired reset threshold VRT plus the reset delay time tRD.
Data Sheet
19
Rev. 1.0, 2013-06-19
TLF50251EL
Reset
Reset output pin (please refer to Figure 7):
The reset output is an open collector structure. As soon as a reset condition occurs, the pin is pulled to ground. A
pull up resistor (R4) connected to VCC or another voltage source is necessary. If the supply (VFB) voltage is below
1 V the open collector structure does no longer pull pin RO to ground. In this case pin RO goes up to the pull-up
voltage (if not supplied by voltage VCC).
V
< tRR
(related to RTADJ)
VRT
tRR
tRR
VRO
tRD
t
tRD
VROH
VROL
t
Figure 7
•
•
Reset Function and Timing Diagram
ROH:= Reset Output High Level, depending on voltage sourcing the pull-up resistor at pin RO
ROL:= Reset Output Low Level, Reset signal valid.
The recommended maximum value
for the sum of both resistors R1 and R2 of the external resistor divider is 1.2 MΩ
Data Sheet
20
Rev. 1.0, 2013-06-19
TLF50251EL
Reset
6.2
Electrical Characteristics Reset Function
Electrical Characteristics: Reset
VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
Reset Output RO
6.2.1
Output voltage low
VRO,L
–
0.2
0.4
V
6.2.2
Sink current limit
IR,S,MAX
1
–
–
mA
6.2.3
Leakage current
–
–
1
µA
6.2.4
Output undervoltage
threshold decreasing
IRO,L,MAX
VRO,T
VCC ≥ 1V; VRTADJ < 0.9V,
IRO = 1 mA
VCC = 5V; VRTADJ < 0.9V,
VRO = 0.4V
VRO = 5V
0.96
1.00
1.04
V
–
6.2.5
Output undervoltage
hysteresis
VRO,T,Hyst
50
–
150
mV
Output voltage decreasing
6.2.6
Pin RTADJ input current
0.1
1
µA
VRTADJ = 1.2V
6.2.7
Delay time
6.2.8
Reset reaction time
IRTADJ,MAX -1
tRD
6
tRR
2
Data Sheet
21
8
10
ms
–
–
10
µs
Output voltage decreasing
Rev. 1.0, 2013-06-19
TLF50251EL
Enable and Thermal Shutdown
7
Enable and Thermal Shutdown
7.1
Description
A valid high level at pin EN (VEN,hi) turns the regulator on, a valid low level at pin EN (VEN,lo) turns the regulator off.
In off state the current consumption of the device is less than 2µA. An integrated pull down resistor at pin EN
(REN,INT) ensures, that the device is switched off, if pin EN is left open.
The integrated thermal shutdown function turns off the power switch in case of overtemperature. The typ. junction
shutdown temperature is 175°C, with a min. of 155°C. After cooling down, the IC will automatically restart with a
soft start into normal operation. The thermal shutdown is an integrated protection function designed to prevent IC
destruction when operating under fault conditions. It should not be used for normal operation.
7.2
Electrical Characteristics Module Enable, Bias and Thermal Shutdown
Electrical Characteristics: Enable, Bias and Thermal Shutdown
VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
VEN = 0V;
Tj < 105°C; VS = 16V
VEN = 5.0V; VS = 16V;
VCC = 5.4V;
Tj < 105°C;
Min.
Typ.
Max.
–
0.1
2
µA
–
60
µA
Enable EN
Iq,OFF
7.2.1
Current consumption, shut
down mode
7.2.2
Current consumption of VCC Iq,ON,V_CC –
PFM mode
7.2.3
Current consumption of VS
Iq,ON,V_S
–
15
20
µA
VEN = 5.0V; VS = 16V;
VCC = 5.4V;
Tj < 105°C;
PFM mode
7.2.4
Enable high signal valid
7.2.5
Enable low signal valid
7.2.6
Enable hysteresis
7.2.7
Enable high input current
7.2.8
Enable low input current
7.2.9
Enable, internal resistor to
GND
VEN,hi
VEN,lo
VEN,HY
IEN,hi
IEN,lo
REN,INT
3.0
–
–
V
–
–
–
0.8
V
–
50
200
400
mV
–
–
–
3
µA
–
0.1
1
µA
7
12
20
ΜΩ
VEN = 16V
VEN = 0.5V
VEN = 3V
Internal Over Temperature Protection
7.2.10
Over temperature shutdown Tj,sd
155
175
195
°C
1)
7.2.11
Over temperature shutdown Tj,sd_hyst
hysteresis
-
15
–
K
1)
1) Specified by design. Not subject to production test.
Data Sheet
23
Rev. 1.0, 2013-06-19
TLF50251EL
Oscillator
8
Oscillator
8.1
Description
The oscillator supplies the device with a constant frequency. The power switch will be switched on and off with a
constant frequency fOSC. The time period TPWM is derived from this frequency and some safety functions are
synchronized to this frequency.
The oscillator frequency can be set by connecting an external resistor RFREQ between pin FREQ and GND using
the following table (selected values, for more precise setting please refer to Figure 8 below).
Frequency Setting Resistor
8.1.1
Oscillator frequency
8.1.2
Frequency adjusting resistor
fosc
RFREQ
2400
2250
1800
1330
1100
kHz
39
43
56
82
100
kΩ
2,5
Switching Frequency [MHz]
2,35
2,2
2,05
1,9
1,75
1,6
1,45
1,3
1,15
1
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
Resistor at Freq pin [kΩ]
Figure 8
Switching Frequency fOSC versus Frequency setting Resistor RFREQ.
The turn-on frequency can optionally be set externally via the SYNC pin. In this case the synchronization of the
PWM-on signal refers to the falling edge of the SYNC-pin input signal. In case the synchronization to an external
clock signal is not needed, the SYNC pin should be connected to ground. The frequency setting resistor RFREQ is
also necessary for SYNC option and must be dimensioned according to the desired synchronization frequency
(the ratio between synchronization and internal frequency has to be less than or equal to 1).
The synchronization function is not available in PFM mode.
Data Sheet
24
Rev. 1.0, 2013-06-19
TLF50251EL
Oscillator
8.2
Electrical Characteristics Module Oscillator
Electrical Characteristics: Module Oscillator
VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
fosc
2025
2250
2475
kHz
VSYNC = 0V;
RFREQ = 43kΩ
fsync
VSYNC,H
VSYNC,L
RSYNC,INT
tSYNC,H, min
tSYNC,L,min
1500
–
2200
kHz
–
2.9
–
–
V
1)
–
–
0.8
V
1)
0.15
0.25
0.40
MΩ
VSYNC = 5V
25
–
–
ns
–
25
–
–
ns
–
Frequency Setting FREQ
8.2.1
Oscillator frequency spread
Synchronization SYNC
8.2.2
Synchronization capture range
8.2.3
SYNC signal high level valid
8.2.4
SYNC signal low level valid
8.2.5
SYNC input internal pull-down
8.2.6
SYNC signal minimum high time
8.2.7
SYNC signal minimum low time
1) Synchronization of PWM-on signal to falling edge.
Data Sheet
25
Rev. 1.0, 2013-06-19
TLF50251EL
Application Information
9
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
LIN
DIN
VS
CIN1
CIN2
LIN, CIN1 and CIN3 recommended for
suppression of EME,
DIN depending on application
CIN3
VS
TLF50251EL
Over
Temperature
Shutdown
EN
Enable
LOUT
Buck
Converter
SWO
VCC
FREQ
Oscillator
INT.
SUPPLY
SYNC
R5
DCATCH
COUT
FB
Bandgap
Reference
Soft Start
Ramp
Generator
R1
R4
RTADJ
N.C.
Reset
Generator
N.C.
To µP
RO
R2
N.C.
Figure 9
GND
GND N.C.
Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real application
Part-No.
C IN2
C IN3
C OUT
D CATCH
LOUT
R1
R2
R4
R5
Figure 10
Data Sheet
Value
47µF/50V
100nF/50V
10µF/25V
1A/100V
10µH
330 kΩ
100 kΩ
100 kΩ
43 kΩ
Type
electrolytic
ceramic
ceramic
10BQ100 Schottky
MSS1278 T
0.25 W
0.25 W
0.25 W
0.25 W
Manufacturer
AVX
AVX
AVX
International Rectifier
Coilcraft
Panasonic
Panasonic
Panasonic
Panasonic
Remark
For improving EME
1 A current capability
4.7 µH also possible
V RT set to 4.3 V
V RT set to 4.3 V
fOSC set to 2.2 MHz
Bill of Material for Application Diagram
26
Rev. 1.0, 2013-06-19
TLF50251EL
Application Information
9.1
General Layout recommendations
Introduction:
A switch mode step down converter is a potential source of electromagnetic disturbances which may affect the
environment as well as the device itself and cause sporadic malfunction up to damages depending on the amount
of noise.
In principal we may consider the following basic effects:
•
•
•
radiated magnetic fields caused by circular currents, occurring mostly with the switching frequency and their
harmonics;
radiated electric fields, often caused by (voltage) oscillations;
conducted disturbances (voltage spikes or oscillations) on the lines, mostly input and output lines.
Radiated magnetic fields:
Radiated magnetic fields are caused by circular currents occurring in so called “current windows”. These circular
currents are alternating currents which are driven by the switching transistor. The alternating current in these
windows are driving magnetic fields. The amount of magnetic emissions is mainly depending on the amplitude of
the alternating current and the size of the so-called “window” (this is the area, which is defined by the circular
current paths.
We can divide into two windows:
•
•
the input current “window” (path consisting of CIN2, CIN3, LOUT and COUT): Only the alternate content of the input
current IS is considered;
the output current “window” (path consisting of DCATCH , LOUT and COUT): Output current ripple ΔI.
The area of these “windows” has to be kept as small as possible, with the relating elements placed next to each
others as close as possible. It is highly recommended to use a ground plane as a single layer which covers the
complete regulator area with all components shown in the application diagram. All connections to ground shall be
as short as possible.
Radiated electric fields:
Radiated electric fields are caused by voltage oscillations occurring by stray inductances and stray capacitances
at the connection between internal power stage (pin SWO), freewheeling diode DCATCH, and output capacitor COUT.
They are also of course influenced by the commutation of the current from the internal power stage to the
freewheeling diode DCATCH. Their frequencies might be above 100 MHz. Therefore, it is recommended to use a
fast Schottky diode and to keep the connections in this area as low inductive as possible. This can be achieved
by using short and broad connections and by arranging the related parts as close as possible. Following the
recommendation of using a ground layer these low inductive connections will form together with the ground layer
small capacitances which are desirable to damp the slope of these oscillations. The oscillations use connections
or wires as antennas, this effect can also be minimized by the short and broad connections.
Data Sheet
27
Rev. 1.0, 2013-06-19
TLF50251EL
Application Information
Conducted disturbances:
Conducted disturbances are voltage spikes or voltage oscillations, occurring permanently or by occasion mostly
on the input or output connections. Comparable to the radiated electric fields they are caused by voltage stage,
freewheeling diode DCATCH, and output capacitor COUT.
Their frequencies might be above 100 MHz. They are super positioned to the input and output voltage and might
therefore disturb other components of the application.
The countermeasures against conducted disturbances are similar to the radiated electric fields:
•
•
•
•
it is recommended to use short and thick connections between the single parts of the converter;
all parts shall be mounted close together;
additional filter capacitors (ceramic, with low ESR i.e CIN3 in the application diagram) in parallel to the output
and input capacitor and as close as possible to the switching parts. Input and load current must be forced to
pass these devices, do not connect them via thin lines. Recommended values from 10nF to 220nF;
for the input filter a so called π – Filter for maximum suppression might be necessary, which requires additional
capacitors on the input.
9.1.1
Additional information
Please contact us:
•
•
•
for information regarding the Pin FMEA;
for existing application notes with more detailed information about the possibilities of this device;
for further information you may contact http://www.infineon.com/
Data Sheet
28
Rev. 1.0, 2013-06-19
TLF50251EL
Package Outlines
10
Package Outlines
0.15 M C A-B D 14x
0.64 ±0.25
1
8
1
7
0.2
M
D 8x
Bottom View
3 ±0.2
A
14
6 ±0.2
D
Exposed
Diepad
B
0.1 C A-B 2x
14
7
8
2.65 ±0.2
0.25 ±0.05 2)
0.08 C
8˚ MAX.
C
0.65
0.1 C D
0.19 +0.06
1.7 MAX.
Stand Off
(1.45)
0 ... 0.1
0.35 x 45˚
3.9 ±0.11)
4.9 ±0.11)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion
PG-SSOP-14-1,-2,-3-PO V02
Figure 11
Package Outline PG-SSOP-14
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further package information, please visit our website:
http://www.infineon.com/packages.
Data Sheet
29
Dimensions in mm
Rev. 1.0, 2013-06-19
TLF50251EL
Revision History
11
Revision History
Rev
Version
Date
Rev 1.0
2011-11-02 Initial data sheet
Data Sheet
Changes
30
Rev. 1.0, 2013-06-19
Edition 2013-06-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
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