74LVC138A-Q100 3-to-8 line decoder/demultiplexer; inverting Rev. 1 — 4 April 2013 Product data sheet 1. General description The 74LVC138A-Q100 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2). When the inputs are enabled, it provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected. There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 74LVC138A-Q100 devices and one inverter. The 74LVC138A-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Mutually exclusive outputs Output drive capability 50 transmission lines at 125 C Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC138AD-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LVC138APW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74LVC138ABQ-Q100 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal-enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm SOT763-1 4. Functional diagram DX 1 A0 1 Y0 A1 Y1 14 3 A2 Y2 13 Y3 12 E1 Y4 11 E2 Y5 10 E3 Y6 9 Y7 7 4 5 6 3 G 0 7 2 2 3 4 4 & 5 5 6 6 7 14 1 13 2 12 3 1 1 2 2 4 3 11 4 10 4 9 5 7 0 6 & 5 6 EN 7 15 14 13 12 11 10 9 7 mna371 Logic symbol Fig 2. (b) IEC logic symbol Y0 15 1 A0 Y1 14 2 A1 Y2 13 3 A2 Y3 12 Y4 11 Y5 10 Y6 9 Y7 7 3-to-8 DECODER 4 X/Y 15 (a) mna370 Fig 1. 1 2 15 2 0 0 ENABLE EXITING E1 5 E2 6 E3 mna372 Fig 3. Functional diagram 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 2 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 5. Pinning information 5.1 Pinning /9&$4 $ WHUPLQDO LQGH[DUHD 9&& /9&$4 9&& $ < $ < $ < $ < ( < ( < ( < ( < < < < *1' < *1' < < ( < < *1' ( $ DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO16 and TSSOP16 Fig 5. Pin configuration for DHVQFN16 5.2 Pin description Table 2. Pin description Symbol Pin Description A0 1 address input A1 2 address input A2 3 address input E1 4 enable input (active LOW) E2 5 enable input (active LOW) E3 6 enable input (active HIGH) GND 8 ground (0 V) Y[0:7] 15, 14, 13, 12, 11, 10, 9, 7 output VCC 16 supply voltage 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 3 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 6. Functional description Function table [1] Table 3. Input Output E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H X X X X X H H H H H H H H X H X X X X H H H H H H H H X X L X X X H H H H H H H H L L H L L L L H H H H H H H H L L H L H H H H H H L H L H H L H H H H H H H L H H H L H H H H L L H H H H H L H H H H L H H H H H H L H H L H H H H H H H H L H H H H H H H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO > VCC or VO < 0 V [2] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA 0.5 VCC + 0.5 V VO output voltage output HIGH or LOW state IO output current VO = 0 V to VCC - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO16 packages: above 70 C the value of PD derates linearly with 8 mW/K. For TSSOP16 packages: above 60 C the value of PD derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C the value of PD derates linearly with 4.5 mW/K. 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 4 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V 0 - VCC V 40 - +125 C VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V functional VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate output HIGH or LOW state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Product data sheet 40 C to +125 C Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35 VCC - 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V IO = 100 A; VCC = 1.65 V to 3.6 V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V VI = VIH or VIL VI = VIH or VIL IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V 0.1 5 - 20 A input leakage VCC = 3.6 V; VI = 5.5 V or GND current 74LVC138A_Q100 Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 5 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Typ[1] Min 40 C to +125 C Max Min Unit Max ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC 0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 4.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions Min Max Min Max - 14 - - - ns VCC = 1.65 V to 1.95 V 0.5 5.2 11.5 0.5 12.7 ns VCC = 2.3 V to 2.7 V 1.5 3.0 6.5 1.5 7.3 ns VCC = 2.7 V 1.5 3.2 6.8 1.5 8.5 ns VCC = 3.0 V to 3.6 V 1.0 2.7 5.8 1.0 7.5 ns - 14 - - - ns An to Yn; see Figure 6 [2] VCC = 1.2 V E3 to Yn; see Figure 6 [2] VCC = 1.2 V VCC = 1.65 V to 1.95 V 1.0 5.5 11.4 1.0 12.5 ns VCC = 2.3 V to 2.7 V 1.5 3.2 6.5 1.5 7.1 ns VCC = 2.7 V 1.5 3.3 6.8 1.5 8.5 ns 1.0 2.9 5.8 1.0 7.5 ns - 15 - - - ns VCC = 1.65 V to 1.95 V 1.0 5.6 11.5 1.0 12.8 ns VCC = 2.3 V to 2.7 V 1.8 3.3 6.5 1.8 7.3 ns VCC = 2.7 V 1.5 3.4 6.4 1.5 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.9 5.8 1.0 7.5 ns - - 1.0 - 1.5 ns VCC = 3.0 V to 3.6 V En to Yn; see Figure 7 [2] VCC = 1.2 V tsk(o) output skew time 74LVC138A_Q100 Product data sheet 40 C to +125 C Unit Typ[1] [3] All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 6 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter 40 C to +85 C Conditions Min CPD [1] power dissipation capacitance 40 C to +125 C Unit Typ[1] Max Min Max [4] VI = GND to VCC VCC = 1.65 V to 1.95 V - 9.9 - pF VCC = 2.3 V to 2.7 V - 15.8 - pF VCC = 3.0 V to 3.6 V - 21.1 - pF Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching (CL VCC2 fo) = sum of outputs 11. Waveforms VCC VCC An, E3 input E1, E2 VM GND GND tPHL tPHL tPLH Yn output VM VM VOL VOL tTHL tTHL tTLH mna373 Fig 6. tPLH VOH VOH Yn output VM input tTLH mna374 VM = 1.5 V at VCC 2.7 V; VM = 1.5 V at VCC 2.7 V; VM = 0.5 VCC at VCC < 2.7 V; VM = 0.5 VCC at VCC < 2.7 V; VOL and VOH are typical output voltage levels that occur with the output load. VOL and VOH are typical output voltage levels that occur with the output load. The inputs An, E3 to outputs Yn propagation delays 74LVC138A_Q100 Product data sheet Fig 7. The inputs En to outputs Yn propagation delays All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 7 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Table 8. Test circuit for measuring switching times Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC 2 ns 30 pF 1 k 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k 2.3 V to 2.7 V VCC 2 ns 30 pF 500 2.7 V 2.7 V 2.5 ns 50 pF 500 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 8 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 9 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 10. Package outline SOT403-1 (TSSOP16) 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 10 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 11. Package outline SOT763-1 (DHVQFN16) 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 11 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 13. Abbreviations Table 9. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC138A_Q100 v.1 20130404 Product data sheet - - 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 12 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC138A_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 13 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC138A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 April 2013 © NXP B.V. 2013. All rights reserved. 14 of 15 74LVC138A-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 April 2013 Document identifier: 74LVC138A_Q100