PHILIPS 74LVC06APW

INTEGRATED CIRCUITS
DATA SHEET
74LVC06A
Hex inverter with open-drain
outputs
Product specification
File under Integrated Circuits, IC24
2000 Mar 07
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
FEATURES
DESCRIPTION
• 5 V tolerant inputs and outputs (open drain) for
interfacing with 5 V logic
The 74LVC06A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
• Wide supply voltage range from 1.65 to 5.5 V
• CMOS low power consumption
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 to 5 V environment.
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
The 74LVC06A provides six inverting buffers.
• Complies with JEDEC standard no. 8-1A.
The outputs of the 74LVC06A devices are open drain and
can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH
wired-AND functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
tPLZ/tPZL
propagation delay nA to nY
CI
input capacitance
CPD
power dissipation capacitance per gate
CONDITIONS
TYP.
CL = 50 pF; VCC = 3.3 V
2.3
5.0
pF
VI = GND to VCC; note 1
8.0
pF
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nA
nY
L
Z
H
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high impedance OFF-state.
2000 Mar 07
2
UNIT
ns
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
−40 to +85 °C
14
SO
plastic
SOT108-1
14
TSSOP
plastic
SOT402-1
74LVC06AD
74LVC06APW
PINNING
PIN
SYMBOL
DESCRIPTION
1, 3, 5, 9, 11 and 13
1A to 6A
data inputs
2, 4, 6, 8, 10 and 12
1Y to 6Y
data outputs
7
GND
ground (0 V)
14
VCC
DC supply voltage
handbook, halfpage
1
1A
1Y 2
3
2A
2Y 4
5
3A
3Y 6
9
4A
4Y 8
11
5A
5Y 10
13
6A
6Y 12
handbook, halfpage
1A
1
14 VCC
1Y
2
13 6A
2A
3
12 6Y
2Y
4
3A
5
10 5Y
3Y
6
9
4A
GND
7
8
4Y
06
11 5A
MNA524
MNA525
Fig.1 Pin configuration.
2000 Mar 07
Fig.2 Logic symbol.
3
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
handbook, halfpage
1A
2A
3A
4A
1
1
2
3
1
4
5
1
6
9
1
8
74LVC06A
1Y
2Y
Y
handbook, halfpage
3Y
A
4Y
GND
MNA527
5A
6A
11
1
10
13
1
12
5Y
6Y
MNA526
Fig.3 IEC logic symbol.
2000 Mar 07
Fig.4 Logic diagram (one gate).
4
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN.
VCC
DC supply voltage
VI
DC input voltage
VO
DC output voltage
Tamb
operating ambient temperature
tr,tf
input rise and fall ratios
MAX.
1.65
5.5
V
0
5.5
V
active mode
0
VCC
V
high-impedance mode
0
5.5
V
−40
+85
°C
VCC = 1.65 to 2.7 V
0
20
ns/V
VCC = 2.7 to 5.5 V
0
10
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−0.5
+6.5
V
−
−50
mA
VCC
DC supply voltage
IIK
DC input diode current
VI < 0
VI
DC input voltage
note 1
−0.5
+6.5
V
IOK
DC output clamping diode current
VO < 0
−
−50
mA
VO
DC output voltage
active mode; note 1
−0.5
VCC + 0.5 V
high-impedance mode;
note 1
−0.5
+6.5
V
VO = 0 to VCC
IO
DC output sink current
−
50
mA
ICC, IGND
DC VCC or GND current
−
±100
mA
Tstg
storage temperature
−65
+150
°C
Ptot
power dissipation per package
SO package
above 70 °C derate linearly
with 8 mW/K
−
500
mW
TSSOP package
above 60 °C derate linearly
with 5.5 mW/K
−
500
mW
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2000 Mar 07
5
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITIONS
SYMBOL
VCC (V)
OTHER
VIH
VIL
VOL
−40 to +85
PARAMETER
HIGH-level input voltage
LOW-level input voltage
LOW-level output
voltage
MIN.
TYP.(1)
UNIT
MAX.
1.65 to 1.95
VCC
−
−
V
2.3 to 2.7
1.7
−
−
V
2.7 to 3.6
2.0
−
−
V
4.5 to 5.5
0.7 × VCC
−
−
V
1.65 to 1.95
−
−
GND
V
2.3 to 2.7
−
−
0.7
V
2.7 to 3.6
−
−
0.8
V
4.5 to 5.5
−
−
0.30 × VCC
V
VI = VIH or VIL
IO = 100 µA
1.65 to 5.5
−
−
0.20
V
IO = 4 mA
1.65
−
−
0.45
V
IO = 8 mA
2.3
−
−
0.3
V
IO = 12 mA
2.7
−
−
0.4
V
IO = 24 mA
3.0
−
−
0.55
V
IO = 32 mA
4.5
−
−
0.55
V
II
input leakage current
3.6
−
±0.1
±5
µA
IOZ
3-state output OFF-state VI = VIH or VIL;
current
VO = 5.5 V or GND
3.6
−
0.1
±10
µA
Ioff
power-off leakage
current
0.0
−
±0.1
±10
µA
ICC
quiescent supply current VI = VCC or GND;
IO = 0
5.5
−
0.1
10
µA
∆ICC
additional quiescent
supply current per input
pin
2.3 to 5.5
−
5
500
µA
VI = 5.5 V or GND
VI or VO = 6.5 V
VI = VCC − 0.6 V;
IO = 0
Note
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2000 Mar 07
6
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
AC CHARACTERISTICS
GND = 0 V; VCC ≤ 2.7 V and tr = tf ≤ 2 ns; VCC ≥ 2.7 V and tr = tf ≤ 2.5 ns.
Tamb (°C)
TEST CONDITIONS
SYMBOL
WAVEFORMS
tPLZ/tPZL
−40 to +85
PARAMETER
propagation delay nA to nY
see Figs 5 and 6
VCC (V)
MIN.
UNIT
TYP.(1)
MAX.
1.65 to 1.95
−
2.9
−
ns
2.3 to 2.7
0.5
1.8
3.1
ns
2.7
0.5
2.5
3.9
ns
3.0 to 3.6
0.5
2.3
3.7
ns
4.5 to 5.5
0.5
1.7
3.4
ns
Note
1. All typical values are measured at Tamb = 25 °C and at VCC respectively 1.8, 2.5, 2.7, 3.3 and 5.0 V.
AC WAVEFORMS
VI
handbook, full pagewidth
VM
nA input
GND
t PLZ
t PZL
VCC
nY output
VM
VX
VOL
MNA529
VCC
VM
VX
<2.7 V
0.5 × VCC
≥2.7 to 3.6 V
1.5 V
VOL + 0.3 V
≥4.5 to 5.5 V
0.5 × VCC
VOL + 0.3 V
VOL + 0.15 V
Fig.5 The input nA to output nY propagation delays.
2000 Mar 07
7
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
Vext
handbook, full pagewidth
VCC
PULSE
GENERATOR
VI
RL
VO
D.U.T.
CL
RT
MNA530
VCC
1.65 to 1.95 V
Vext
VI
CL
RL
2 × VCC
VCC
30 pF
1 kΩ
2.3 to 2.7 V
2 × VCC
VCC
30 pF
500 Ω
2.7 V
6V
2.7 V
50 pF
500 Ω
3.3 to 3.6 V
6V
2.7 V
50 pF
500 Ω
4.5 to 5.5 V
2 × VCC
VCC
50 pF
500 Ω
Fig.6 Load circuitry for switching times.
2000 Mar 07
8
RL
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.050
0.028
0.024
0.01
0.01
0.004
0.028
0.012
inches 0.069
0.244
0.039
0.041
0.228
0.016
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
2000 Mar 07
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-05-22
99-12-27
9
o
8
0o
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
2000 Mar 07
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-04-04
99-12-27
MO-153
10
o
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Mar 07
11
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Mar 07
12
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
NOTES
2000 Mar 07
13
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
NOTES
2000 Mar 07
14
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
NOTES
2000 Mar 07
15
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Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
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Printed in The Netherlands
245004/01/pp16
Date of release: 2000
Mar 07
Document order number:
9397 750 06736