PD - 97457 IRF6794MPbF IRF6794MTRPbF HEXFET® Power MOSFET plus Schottky Diode Typical values (unless otherwise specified) RoHs Compliant Containing No Lead and Bromide VDSS VGS RDS(on) RDS(on) l Integrated Monolithic Schottky Diode 25V max ±20V max 1.3mΩ@ 10V 2.3mΩ@ 4.5V l Low Profile (<0.7 mm) l Dual Sided Cooling Compatible Qg tot Qgd Qgs2 Qrr Qoss Vgs(th) l Low Package Inductance 31nC 11nC 4.4nC 51nC 27nC 1.8V l Optimized for High Frequency Switching l Ideal for CPU Core DC-DC Converters l Optimized for Sync. FET socket of Sync. Buck Converter l Low Conduction and Switching Losses l Compatible with existing Surface Mount Techniques l 100% Rg tested DirectFET ISOMETRIC MX Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details) l SQ SX ST MQ MT MX MP Description The IRF6794MPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques. Application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%. The IRF6794MPbF balances industry leading on-state resistance while minimizing gate charge along with low gate resistance to reduce both conduction and switching losses. This part contains an integrated Schottky diode to reduce the Qrr of the body drain diode further reducing the losses in a Synchronous Buck circuit. The reduced losses make this product ideal for high frequency/high efficiency DC-DC converters that power high current loads such as the latest generation of microprocessors. The IRF6794MPbF has been optimized for parameters that are critical in synchronous buck converter’s Sync FET sockets. Absolute Maximum Ratings Parameter VDS Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V g Pulsed Drain Current Single Pulse Avalanche Energy Avalanche Current g e e f h VGS, Gate-to-Source Voltage (V) VGS ID @ TA = 25°C ID @ TA = 70°C ID @ TC = 25°C IDM EAS IAR Typical RDS(on) (mΩ) 5 ID = 32A 4 3 TJ = 125°C 2 1 TJ = 25°C 0 2 4 6 8 10 12 14 16 18 VGS, Gate -to -Source Voltage (V) Fig 1. Typical On-Resistance vs. Gate Voltage Notes: Click on this section to link to the appropriate technical paper. Click on this section to link to the DirectFET Website. Surface mounted on 1 in. square Cu board, steady state. www.irf.com Max. Units 25 ±20 32 25 200 250 200 26 V A mJ A 14.0 ID= 26A 12.0 VDS = 20V VDS = 13V 10.0 8.0 6.0 4.0 2.0 0.0 0 20 40 60 80 QG Total Gate Charge (nC) Fig 2. Typical Total Gate Charge vs. Gate-to-Source Voltage TC measured with thermocouple mounted to top (Drain) of part. Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.65mH, RG = 25Ω, IAS = 26A. 1 2/12/10 IRF6794MTRPbF Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Drain-to-Source Breakdown Voltage 25 ––– ––– ΔΒVDSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 14 ––– RDS(on) Static Drain-to-Source On-Resistance ––– 1.3 1.7 VGS(th) Gate Threshold Voltage ––– 2.3 3.0 1.35 1.8 2.35 V VGS = 4.5V, ID = 26A V Gate Threshold Voltage Coefficient ––– -4.7 ––– IDSS Drain-to-Source Leakage Current ––– ––– 500 ––– ––– 5.0 mA ––– ––– 100 nA gfs Qg Qgs1 Gate-to-Source Forward Leakage VGS = 0V, ID = 1.0mA mV/°C Reference to 25°C, ID = 10mA mΩ VGS = 10V, ID = 32A ΔVGS(th)/ΔTJ IGSS Conditions Typ. Max. Units BVDSS i i VDS = VGS, ID = 100µA mV/°C VDS = VGS, ID = 10mA µA VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V Gate-to-Source Reverse Leakage ––– ––– -100 Forward Transconductance 110 ––– ––– Total Gate Charge ––– 31 47 Pre-Vth Gate-to-Source Charge ––– 7.8 ––– VDS = 13V VGS = 4.5V S VDS = 13V, ID = 26A Qgs2 Post-Vth Gate-to-Source Charge ––– 4.4 ––– Qgd Gate-to-Drain Charge ––– 11 ––– ID = 26A Qgodr Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– 7.8 ––– See Fig. 15 Qsw ––– 15 ––– Qoss Output Charge ––– 27 ––– nC RG Gate Resistance ––– 0.30 ––– Ω nC VDS = 16V, VGS = 0V i VDD = 13V, VGS = 4.5V td(on) Turn-On Delay Time ––– 15 ––– tr Rise Time ––– 25 ––– td(off) Turn-Off Delay Time ––– 9.7 ––– RG = 1.8Ω tf Fall Time ––– 9.6 ––– Ciss Input Capacitance ––– 4420 ––– See Fig. 17 VGS = 0V Coss Output Capacitance ––– 1260 ––– Crss Reverse Transfer Capacitance ––– 530 ––– ns pF ID = 26A VDS = 13V ƒ = 1.0MHz Diode Characteristics Parameter IS Continuous Source Current Min. ––– Typ. Max. Units ––– ISM VSD A Pulsed Source Current (Body Diode) MOSFET symbol 32 (Body Diode) g Diode Forward Voltage ––– ––– ––– ––– Conditions showing the 250 integral reverse 0.75 V p-n junction diode. TJ = 25°C, IS = 26A, VGS = 0V trr Reverse Recovery Time ––– 27 41 ns TJ = 25°C, IF = 26A Qrr Reverse Recovery Charge ––– 51 77 nC di/dt = 370A/µs i i Notes: Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 www.irf.com IRF6794MTRPbF Absolute Maximum Ratings e e f Max. Units 2.8 1.8 100 270 -40 to + 150 W Parameter Power Dissipation Power Dissipation Power Dissipation Peak Soldering Temperature Operating Junction and Storage Temperature Range PD @TA = 25°C PD @TA = 70°C PD @TC = 25°C TP TJ TSTG °C Thermal Resistance Parameter el jl kl fl RθJA RθJA RθJA RθJC RθJ-PCB Typ. Max. Units ––– 12.5 20 ––– 1.0 45 ––– ––– 1.2 ––– °C/W Junction-to-Ambient Junction-to-Ambient Junction-to-Ambient Junction-to-Case Junction-to-PCB Mounted Linear Derating Factor e 0.022 W/°C Thermal Response ( Z thJA ) 100 10 D = 0.50 0.20 0.10 0.05 1 0.02 0.01 τJ 0.1 R1 R1 τJ τ1 R2 R2 R3 R3 R4 R4 τA τ2 τ1 τ2 τ3 τ4 τ3 Ci= τi/Ri Ci= τi/Ri 0.01 0.001 1E-006 0.0001 0.001 τA τi (sec) 0.9810 0.000229 3.1819 0.014154 22.8717 1.0333 17.9602 40.9 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 τ4 Ri (°C/W) 0.01 0.1 1 10 100 1000 t1 , Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Notes: Used double sided cooling , mounting pad with large heatsink. Mounted on minimum footprint full size board with metalized back and with small clip heatsink. Surface mounted on 1 in. square Cu (still air). www.irf.com Rθ is measured at TJ of approximately 90°C. Mounted to a PCB with small clip heatsink (still air) Mounted on minimum footprint full size board with metalized back and with small clip heatsink (still air) 3 IRF6794MTRPbF 1000 1000 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 10V 5.0V 4.5V 3.5V 3.3V 3.0V 2.8V 2.6V 10 1 2.6V 100 BOTTOM 10 2.6V ≤60µs PULSE WIDTH ≤60µs PULSE WIDTH Tj = 150°C Tj = 25°C 0.1 1 0.1 1 10 100 0.1 VDS , Drain-to-Source Voltage (V) 1 10 100 VDS , Drain-to-Source Voltage (V) Fig 4. Typical Output Characteristics Fig 5. Typical Output Characteristics 1.6 1000 Typical RDS(on) (Normalized) ID = 32A ID, Drain-to-Source Current(A) VGS 10V 5.0V 4.5V 3.5V 3.3V 3.0V 2.8V 2.6V 100 TJ = 150°C TJ = 25°C TJ = -40°C 10 1 VGS = 10V VGS = 4.5V 1.4 1.2 1.0 0.8 VDS = 15V ≤60µs PULSE WIDTH 0.6 0.1 1.5 2.0 2.5 3.0 3.5 4.0 -60 -40 -20 0 4.5 VGS, Gate-to-Source Voltage (V) Fig 6. Typical Transfer Characteristics Fig 7. Normalized On-Resistance vs. Temperature 14 100000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd TJ = 25°C 12 Typical RDS (on) (mΩ) Coss = Cds + Cgd C, Capacitance(pF) 20 40 60 80 100 120 140 160 TJ , Junction Temperature (°C) 10000 Ciss Coss 1000 Crss 10 8 Vgs = 3.5V Vgs = 4.0V Vgs = 4.5V Vgs = 5.0V Vgs = 7.0V Vgs = 8.0V Vgs = 10V Vgs = 15V 6 4 2 0 100 1 10 100 VDS , Drain-to-Source Voltage (V) Fig 8. Typical Capacitance vs.Drain-to-Source Voltage 4 0 25 50 75 100 125 150 175 200 ID, Drain Current (A) Fig 9. Typical On-Resistance vs. Drain Current and Gate Voltage www.irf.com IRF6794MTRPbF 10000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 100 10 TJ = 150°C TJ = 25°C TJ = -40°C 1 VGS = 0V OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100 100µsec 10 DC 1 TA = 25°C Tj = 150°C Single Pulse 0.1 10msec 0.01 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0.1 1.0 10.0 100.0 VDS , Drain-toSource Voltage (V) VSD, Source-to-Drain Voltage (V) Fig 10. Typical Source-Drain Diode Forward Voltage Fig 11. Maximum Safe Operating Area Typical VGS(th) Gate threshold Voltage (V) 200 160 ID, Drain Current (A) 1msec 120 80 40 3.0 2.5 ID = 10mA 2.0 1.5 1.0 0 25 50 75 100 125 -75 -50 -25 150 0 25 50 75 100 125 150 TJ , Temperature ( °C ) TC , Case Temperature (°C) Fig 12. Maximum Drain Current vs. Case Temperature Fig 13. Typical Threshold Voltage vs. Junction Temperature EAS , Single Pulse Avalanche Energy (mJ) 900 ID 2.5A 3.5A BOTTOM 25A 800 TOP 700 600 500 400 300 200 100 0 25 50 75 100 125 150 Starting TJ , Junction Temperature (°C) Fig 14. Maximum Avalanche Energy vs. Drain Current www.irf.com 5 IRF6794MTRPbF Id Vds Vgs L D VCC DUT G 0 Vgs(th) S 20K 1K Qgodr Fig 15a. Gate Charge Test Circuit Qgd Qgs2 Qgs1 Fig 15b. Gate Charge Waveform V(BR)DSS 15V DRIVER L VDS V RGSG tp D.U.T + - VDD IAS 20V A 0.01Ω tp I AS Fig 16b. Unclamped Inductive Waveforms Fig 16a. Unclamped Inductive Test Circuit VDS VGS RG RD VDS 90% D.U.T. + - V DD VGS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 10% VGS td(on) Fig 17a. Switching Time Test Circuit 6 tr t d(off) tf Fig 17b. Switching Time Waveforms www.irf.com IRF6794MTRPbF Driver Gate Drive D.U.T P.W. + + - - RG * • • • • *** D.U.T. ISD Waveform Reverse Recovery Current + dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer D= Period V DD ** + Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent - Ripple ≤ 5% * Use P-Channel Driver for P-Channel Measurements ** Reverse Polarity for P-Channel ISD *** VGS = 5V for Logic Level Devices Fig 18. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs DirectFET Board Footprint, MX Outline (Medium Size Can, X-Designation). Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. G = GATE D = DRAIN S = SOURCE D D S G S D www.irf.com D 7 IRF6794MTRPbF DirectFET Outline Dimension, MX Outline (Medium Size Can, X-Designation). Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. DIMENSIONS METRIC CODE A B C D E F G H J K L M R P MIN 6.25 4.80 3.85 0.35 0.68 0.68 1.38 0.80 0.38 0.88 2.28 0.616 0.020 0.08 MAX 6.35 5.05 3.95 0.45 0.72 0.72 1.42 0.84 0.42 1.01 2.41 0.676 0.080 0.17 IMPERIAL MIN 0.246 0.189 0.152 0.014 0.027 0.027 0.054 0.032 0.015 0.035 0.090 0.0235 0.0008 0.003 MAX 0.250 0.201 0.156 0.018 0.028 0.028 0.056 0.033 0.017 0.039 0.095 0.0274 0.0031 0.007 DirectFET Part Marking 8 www.irf.com IRF6794MTRPbF DirectFET Tape & Reel Dimension (Showing component orientation). Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/09 www.irf.com 9