PHILIPS TDA9952

INTEGRATED CIRCUITS
DATA SHEET
TDA9952
10-bit, 3.0 V, 25 Msps
analog-to-digital interface for
CCD cameras
Preliminary specification
Supersedes data of 2001 Jul 04
2002 Aug 21
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
FEATURES
GENERAL DESCRIPTION
• Sample rate = 25 Msps;10-bit resolution
The TDA9952 is a 10-bit analog-to-digital interface for
CCD cameras. The device consists of a Correlated Double
Sampling (CDS) circuit, a digitally Programmable Gain
Amplifier (PGA), a black level clamp and a 10-bit
Analog-to-Digital Converter (ADC).
• Single 3.0 V supply operation (2.2 to 3.6 V operation for
the digital outputs)
• Low power consumption: only 115 mW at 2.7 V
• Power consumption in standby mode: 4.5 mW
(typical value)
An internal CDS input buffer is incorporated in order to
avoid using an external buffer that would consume more
power and therefore optimizing the application for low
noise, low power working.
• Programmable gain amplifier:
gain range = 36 dB in 0.1 dB steps
• Correlated double sampling
• Internal input buffer for the correlated double sampling
The PGA gain, the ADC clamp level and other settings are
controlled via a 3-wire serial digital interface.
• Fully programmable via a 3-wire serial interface
An additional DAC is provided for system controls.
• 8-bit DAC included for external analog settings
The TDA9952 operates from a single 3 V power supply
(2.7 V minimum) and dissipates 135 mW (typical value).
• TTL-compatible inputs and CMOS-compatible outputs.
APPLICATIONS
• Video camcorders
• Digital still cameras
• PC-cameras.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
NAME
TDA9952HL
LQFP48
TDA9952HN
HVQFN48
2002 Aug 21
DESCRIPTION
VERSION
plastic low profile quad flat package; 48 leads;
body 7 × 7 × 1.4 mm
SOT313-2
plastic, heatsink very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
SOT619-1
2
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
2.7
3.0
3.6
V
VCCD
digital supply voltage
2.7
3.0
3.6
V
VCCO
digital outputs supply voltage
2.2
2.5
3.6
V
ICCA
analog supply current
all clamps active
−
43
−
mA
ICCD
digital supply current
fpix = 25 MHz
−
2.0
−
mA
ICCO
digital outputs supply current
fpix = 25 MHz; CL = 10 pF;
−
input ramp response time is 800 µs
0.5
−
mA
ADCres
ADC resolution
Vi(CDS)(p-p)
maximum CDS input voltage
(peak-to-peak value)
fpix(max)
maximum pixel rate
fpix(min)
minimum pixel rate
−
10
−
bits
VCC = 2.85 V
650
−
−
mV
VCC ≥ 3.0 V
800
−
−
mV
25
−
−
MHz
OCCD(max) = ±100 mV
−
−
1
MHz
OCCD(max) = ±200 mV
−
−
2
MHz
DRPGA
PGA dynamic range
−
36
−
dB
Ntot(rms)
total noise from CDS input to
ADC output (RMS value)
PGA code = 00; see Fig.8
−
0.4
−
LSB
Ein(rms)
equivalent input noise voltage
(RMS value)
PGA code = 383
−
145
−
µV
Ptot
total power consumption
VCCA = VCCD = 3 V; VCCO = 2.5 V
−
135
−
mW
VCCA = VCCD = 2.7 V; VCCO = 2.2 V
−
115
−
mW
standby mode
−
4.5
−
mW
2002 Aug 21
3
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45
46
AGND1
1
VCCA6
2
41
BLK
AGND6 CLPOB CLPDM
40
44
43
48
CLK
47
OE
39
22
21
CDS CLOCK GENERATOR
37
CPCDS1
38
8
VCCA2
AGND2
IN
36
9
35
7
input buffer
34
3
33
PGA
CORRELATED
DOUBLE
SAMPLING
4
BLACK
LEVEL
SHIFT
SHIFT
4
n.c.
BLANKING
25,
26
DATA
FLIPFLOP
32
OUTPUT
BUFFER
31
30
10-bit ADC
29
CLAMP
28
27
VCCA3
AGND3
OGND2
VCCO2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Vref
14
9-BIT
REGISTER
5
6-BIT
REGISTER
24
OFD DAC
23
11
8-BIT
REGISTER
12
6
13
SERIAL
INTERFACE
INIT-ONPOWER
15
16
VCCA4
VCCA5
19
18
17
REGULATOR
20
10
OGND1
VCCO1
DCLPC
42
FCE629
AGND4
AGND5
SEN
STDBY
TDA9952
Fig.1 Block diagram.
SCLK SDATA VSYNC
Preliminary specification
TEST
handbook, full pagewidth
OFDOUT
VCCD1
TDA9952
CLAMP
CPCDS2
DGND1
Philips Semiconductors
VCCA1
SHD
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
BLOCK DIAGRAM
2002 Aug 21
SHP
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
PINNING
SYMBOL
PIN
DESCRIPTION
VCCA1
1
analog supply voltage1
AGND1
2
analog ground 1
AGND2
3
analog ground 2
IN
4
input signal from CCD
AGND3
5
analog ground 3
AGND4
6
analog ground 4
VCCA2
7
analog supply voltage 2
CPCDS1
8
clamp storage capacitor pin 1
CPCDS2
9
clamp storage capacitor pin 2
DCLPC
10
regulator decoupling pin
OFDOUT
11
analog output of the additional 8-bit control DAC
TEST
12
test mode input pin (should be connected to AGND5)
AGND5
13
analog ground 5
VCCA3
14
analog supply voltage 3
VCCA4
15
analog supply voltage 4
VCCA5
16
analog supply voltage 5
SDATA
17
serial data input for serial interface control
SCLK
18
serial clock input for serial interface
SEN
19
strobe pin for serial interface
VSYNC
20
vertical sync pulse input
VCCD1
21
digital supply voltage 1
DGND1
22
digital ground 1
VCCO1
23
digital output supply voltage 1
OGND1
24
digital output ground 1
n.c.
25
not connected
n.c.
26
not connected
D0
27
ADC digital output 0 (LSB)
D1
28
ADC digital output 1
D2
29
ADC digital output 2
D3
30
ADC digital output 3
D4
31
ADC digital output 4
D5
32
ADC digital output 5
D6
33
ADC digital output 6
D7
34
ADC digital output 7
D8
35
ADC digital output 8
D9
36
ADC digital output 9 (MSB)
OGND2
37
digital output ground 2
VCCO2
38
digital output supply voltage 2
OE
39
output enable control input (LOW: outputs active; HIGH: outputs in high-impedance)
AGND6
40
analog ground 6
2002 Aug 21
5
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
SYMBOL
TDA9952
PIN
DESCRIPTION
45
preset sample-and-hold pulse input
SHD
46
data sample-and-hold pulse input
CLK
47
data clock input
CLPDM
48
clamp pulse input at dummy pixel
43 BLK
handbook, full pagewidth
37 OGND2
SHP
38 VCCO2
clamp pulse input at optical black
39 OE
44
40 AGND6
CLPOB
41 VCCA6
blanking control input
42 STDBY
standby mode control input (LOW: TDA9952 active; HIGH: TDA9952 standby)
43
44 CLPOB
42
BLK
45 SHP
STDBY
46 SHD
analog supply voltage 6
47 CLK
41
48 CLPDM
VCCA6
VCCA1
1
36 D9
AGND1
2
35 D8
AGND2
3
34 D7
IN
4
33 D6
AGND3
5
32 D5
AGND4
6
31 D4
TDA9952HL
VCCA2
7
30 D3
CPCDS1
8
29 D2
CPCDS2
9
28 D1
DCLPC 10
27 D0
Note: the HVQFN package pin configuration is identical.
Fig.2 Pin configuration.
2002 Aug 21
6
OGND1 24
VCCO1 23
DGND1 22
VCCD1 21
VSYNC 20
SEN 19
SCLK 18
SDATA 17
VCCA5 16
25 n.c.
VCCA4 15
TEST 12
VCCA3 14
26 n.c.
AGND5 13
OFDOUT 11
FCE483
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCCA
analog supply voltage
note 1
−0.3
+4.5
V
VCCD
digital supply voltage
note 1
−0.3
+4.5
V
VCCO
digital outputs supply voltage
note 1
−0.3
+4.5
V
∆VCC
supply voltage difference
between VCCA and VCCD
−0.5
+0.5
V
between VCCA and VCCO
−0.5
+1.2
V
−0.5
+1.2
V
−0.3
+6.5
V
between VCCD and VCCO
Vi
input voltage
Io
data output current
−
±10
mA
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−20
+75
°C
Tj
junction temperature
−
150
°C
referenced to AGND
Note
1. All supplies are connected together.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
2002 Aug 21
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
7
in free air
VALUE
UNIT
76
K/W
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
CHARACTERISTICS
VCCA = VCCD = 3.0 V; VCCO = 2.5 V; fpix = 25 MHz; Tamb = −20 to +75 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
2.7
VCCD
digital supply voltage
2.7
3.0
3.6
V
VCCO
digital outputs supply
voltage
2.2
2.5
3.6
V
ICCA
analog supply current
−
43
−
mA
ICCD
digital supply current
−
2.0
−
mA
ICCO
digital outputs supply
current
CL = 10 pF on all data
outputs; input ramp of
800 µs duration
−
0.5
−
mA
Ptot
total power consumption
VCCA = VCCD = 3 V;
VCCO = 2.5 V
−
135
−
mW
VCCA = VCCD = 2.7 V;
VCCO = 2.2 V
−
115
−
mW
standby mode
−
4.5
−
mW
0
−
0.8
V
all clamps active
3.0
3.6
V
Digital inputs
PINS SHP, SHD AND CLK (REFERENCED TO DGND)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
Ii
input current
Ci
input capacitance
0 ≤ Vi ≤ 5.5 V
2.0
−
5.5
V
−3
−
+3
µA
−
−
2
pF
PINS CLPDM, CLPOB, SEN, SCLK, SDATA STBY, OE, BLK AND VSYNC
VIL
LOW-level input voltage
0
−
0.8
V
VIH
HIGH-level input voltage
2.0
−
5.5
V
Ii
input current
−2
−
+2
µA
15
−
−
pixels
−
15
−
mS
0 ≤ Vi ≤ 5.5 V
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp)
clamp active pulse width in PGA code = 383 for
number of pixels
maximum 6 LSB error for a
CPCDS capacitance
of 1 µF; clamp code = 32
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS)
2002 Aug 21
CDS input clamp
transconductance
8
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
SYMBOL
PARAMETER
TDA9952
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
maximum CDS input
voltage (peak-to-peak
value)
VCC = 2.85 V
650
−
−
mV
VCC ≥ 3.0 V
800
−
−
mV
−
−
1.5
V
−
−
3
µA
−
2
−
pF
Vreset(max)
maximum CDS input reset
pulse
Ii(IN)
input current into pin IN
Ci
input capacitance
tCDS(min)
CDS control pulses
minimum active time
Vi(CDS)(p-p) = 800 mV;
black-to-white transition in
1 pixel with 98.5% Vi
recovery
11
−
−
ns
th(IN;SHP)
CDS input hold time
(pin IN) compared to
control pulse SHP
Figs 3 and 4
3
−
−
ns
th(IN;SHD)
CDS input hold time
(pin IN) compared to
control pulse SHD
Figs 3 and 4
3
−
−
ns
at floating gate level
Programmable Gain Amplifier (PGA)
DRPGA
PGA dynamic range
−
36
−
dB
∆GPGA
PGA gain step
0.08
0.10
0.12
dB
−
±0.5
±0.9
LSB
−
10
−
bits
25
−
−
MHz
OCCD(max) = ±100 mV
−
−
1
MHz
OCCD(max) = ±200 mV
−
−
2
MHz
ADC
DNL
differential non linearity
ADCres
ADC resolution
ramp input
Total chain characteristics (CDS + PGA + ADC)
fpix(max)
maximum pixel rate
fpix(min)
minimum pixel rate
OCCD(max)
maximum offset voltage
between CCD floating
level and CCD dark pixel
level
−200
−
+200
mV
tCLKH
CLK pulse width HIGH
15
−
−
ns
tCLKL
CLK pulse width LOW
15
−
−
ns
td(SHD;CLK)
time delay between
SHD and CLK
Figs 3 and 4
−
10
−
ns
tsu(BLK;SHD)
set-up time of BLK
compared to SHD
Figs 3 and 4
5
−
−
ns
Vi(IN)
video input voltage for
ADC full-scale output
PGA code = 00
−
800
−
mV
PGA code = 383
−
12.7
−
mV
2002 Aug 21
9
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
SYMBOL
Ntot(rms)
PARAMETER
TDA9952
CONDITIONS
total noise from CDS input Fig.8; note 1
to ADC output
PGA code = 00
(RMS value)
PGA code = 96
MIN.
TYP.
MAX.
UNIT
−
0.4
−
LSB
−
0.6
−
LSB
PGA code = 383
−
145
−
µV
PGA code = 96
−
170
−
µV
VOFDOUT(p-p) output voltage
(peak-to-peak value)
RL = 1 MΩ
−
1.0
−
V
VOFDOUT(0)
DC output voltage for
code 0
Fig.5
−
VAGND
−
V
VOFDOUT(255) DC output voltage for
code 255
Fig.5
−
VAGND + 1.0 −
V
−
250
−
ppm/K
−
2000
−
Ω
−
−
100
µA
Ein(rms)
equivalent input noise
voltage (RMS value)
Digital-to-Analog Converter (OFD DAC)
TCDAC
DAC output temperature
coefficient
ZOFDOUT
DAC output impedance
IOFDOUT
DAC output current drive
static
Digital outputs fpix = 25 MHz; CL = 10 pF; see Figs 3 and 4
VOH
HIGH-level output voltage
IOH = −1 mA
VCCO − 0.5
−
VCCO
V
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.5
V
IOZ
output current in 3-state
mode
0.5 V < Vo < VCCO
−20
−
+20
µA
th(o)
output hold time
5
td(o)
output delay time
−
−
ns
VCCO = 3.6 V; VCCD = 3.6 V −
10
13
ns
VCCO = 2.5 V; VCCD = 3.0 V −
12
15
ns
VCCO = 2.2 V; VCCD = 2.7 V −
CL
output load capacitance
13
16
ns
−
−
20
pF
10
−
−
MHz
Serial interface
fSCLK(max)
maximum clock frequency
of serial interface
Note
1. Noise figure includes the internal input buffer circuit.
2002 Aug 21
10
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N+1
N
N+2
N+3
N+4
N+5
tCDS(min)
2.0 V
SHP
0.8 V
th(IN;SHP)
tCDS(min)
2.0 V
2.0 V
SHD
0.8 V
0.8 V
th(IN;SHD)
tCLKH
11
2.0 V
2.0 V
Philips Semiconductors
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
2002 Aug 21
IN
CLK
0.8 V
0.8 V
td(SHD;CLK)
DATA
N−4
N−3
50%
N−2
N−1
N
ADC CLAMP
CODE
th(o)
td(o)
2.0 V
BLK
handbook, full pagewidth
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
TDA9952
SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at falling edge.
Recommended placement for CLK rising edge is between the falling edge of SHD and the rising edge of SHP.
Preliminary specification
MGU673
tsu(BLK;SHD)
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N+1
N
N+2
N+3
N+4
N+5
2.0 V
SHP
0.8 V
tCDS(min)
th(IN;SHP)
2.0 V
2.0 V
SHD
0.8 V
0.8 V
tCDS(min)
th(IN;SHD)
12
2.0 V
2.0 V
Philips Semiconductors
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
2002 Aug 21
IN
CLK
0.8 V
0.8 V
tCLKL
DATA
N−4
td(SHD;CLK)
N−3
50%
N−2
N−1
N
ADC CLAMP
CODE
th(o)
td(o)
BLK
SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at rising edge.
Recommended placement for CLK falling edge is between the rising edge of SHD and the falling edge of SHP.
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
Preliminary specification
MGU672
tsu(BLK;SHD)
TDA9952
handbook, full pagewidth
0.8 V
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
handbook, halfpage
TDA9952
FCE486
1.0
OFDOUT DAC
voltage
output
(V)
0
255
0
OFDOUT control DAC input code
Fig.5 DAC voltage output as a function of DAC input code.
CLPOB
WINDOW
handbook, full pagewidth
D[9:0]
(digital outputs)
VIDEO
OPTICAL BLACK
CLPDM
WINDOW
HORIZONTAL FLYBACK
DUMMY
VIDEO
CLPOB
(active HIGH)
CLPDM
(active HIGH)
BLK
(active HIGH)
BLK window
FCE487
Fig.6 Line frequency timing diagram.
2002 Aug 21
13
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
MGU671
42
TOTAL
gain
(dB) 36
handbook, halfpage
37.9
30
24
18
12
6
1.9
0
0
64
128
192
256
320
384 448 511
PGA input code
PGAcode
Gain ( dB ) = 1.9 + 36 ×  ---------------------------- [ dB ]


383
Full-scale at the ADC input is reached at Vi(CDS)(p-p) = 800 mV; PGA code 0.
Fig.7 Total gain from CDS input to ADC input as a function of PGA control code.
FCE489
14
tot(rms)
(LSB)
12
handbook,
halfpage
N
10
8
6
4
2
0
0
64
128
192
256
320
383
PGA code
Noise measurement at ADC outputs:
Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 25 Mpixels with line of 1024 pixels
whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this,
the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into account because there is no input.
Fig.8 Typical total noise performance as a function of PGA gain.
2002 Aug 21
14
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
SERIAL INTERFACE
SDATA
handbook,
full pagewidth
SHIFT REGISTER
SD0
SD1
SD2 SD3
SD5 SD6
SD4
SD7 SD8 SD9 SD10 SD11 A0
SCLK
12
OFDOUT DAC
LATCHES
9
PGA GAIN
LATCHES
6
8-bit DAC
ADC CLAMP
LATCHES
CONTROL PULSE
POLARITY
LATCHES
FLIP-FLOP
FLIP-FLOP
PGA control
ADC clamp
control
control pulses
polarity settings
CONDITIONING
VSYNC
FCE490
First logical layer (DFF) is clocked by first falling SCLK edge after rising SEN edge.
Second logical layer is clocked by LOAD signal; this signal depends on VSYNC signal.
If vertical sync signal is not available, VSYNC should be connected to SEN.
Fig.9 Serial interface block diagram.
2002 Aug 21
A3
10
LOAD
FLIP-FLOP
A2
LATCH
SELECTION
SEN
8
A1
MSB
LSB
15
VSYNC
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
tsu2
handbook, full pagewidth
thd4
MSB
SDATA
A3
A2
A1
A0
SD11 SD10
SD9
SD8
SD7
SD6
LSB
SD5
SD4
SD3
SD2
SD1
SD0
SCLK
SEN
tsu1
tsu3
thd5
thd6
VSYNC
FCE491
tsu1 = tsu2 = tsu3 = 10 ns (minimum); thd4 = thd5 = thd6 = 10 ns (minimum).
Fig.10 Loading sequence of control input data via the serial interface.
2002 Aug 21
16
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
Table 1
TDA9952
Serial interface programming
ADDRESS BITS
DATA BITS SD11 TO SD0
A3
A2
A1
A0
0
0
0
0
PGA gain control (SD8 to SD0)
0
0
0
1
DAC OFDOUT output control (SD7 to SD0)
0
0
1
0
ADC clamp reference control (SD5 to SD0); from code 0 to 63
0
0
1
1
control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) polarity settings;
SD2, SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see
Tables 3 and 4
other addresses
Table 2
test modes (not to be used in normal applications)
Polarity settings
PIN
DATA BIT
ACTIVE EDGE OR LEVEL
SHP and SHD
SD4
1 = HIGH; 0 = LOW
CLK
SD5
1 = rising; 0 = falling
CLPDM
SD0
1 = HIGH; 0 = LOW
CLPOB
SD1
1 = HIGH; 0 = LOW
BLK
SD3
1 = HIGH; 0 = LOW
VSYNC
SD8
0 = rising; 1 = falling
Table 3
Standby control using pin STDBY or serial interface
DATA BIT SD7
PIN STDBY
ICCA + ICCD (typical)
1
HIGH
1.5 mA
LOW
45 mA
HIGH
45 mA
LOW
1.5 mA
0
Table 4
Output enable selection using output enable pin OE or serial interface)
DATA BIT SD6
1
0
PIN OE
ADC DIGITAL OUTPUTS D9 TO D0
LOW
active binary
HIGH
high-impedance
LOW
high-impedance
HIGH
active binary
When power supplies increase from zero, an init-on-power block initializes the circuit as follows:
• PGA gain code is set to 000
• Clamp code is set to 00
• All polarity settings are set to logic 1
• Input OFD is set to logic 0.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
APPLICATION INFORMATION
VCCD
handbook, full pagewidth
VCCA
VCCD
VCCO
100 nF
100 nF
OGND2
OE
VCCO2
AGND6
VCCA6
STDBY
BLK
SHP
(2)
CLPOB
1 µF
SHD
CLPDM
CCD(1)(2)
CLK
(2)
48 47 46 45 44 43 42 41 40 39 38 37
VCCA1
VCCA
AGND1
100 nF
AGND2
IN
AGND3
AGND4
VCCA2
VCCA
CPCDS1
100 nF
1 µF
CPCDS2
1 µF
DCPLC
1 µF OFDOUT
TEST
1
36
2
35
3
34
4
33
5
32
6
31
TDA9952
7
30
8
29
9
28
10
27
11
26
12
25
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c
n.c
100 nF
VCCA
serial
interface
(3)
100 nF
VCCD
OGND1
VCCO1
DGND1
VCCD1
VSYNC
SEN
SCLK
SDATA
VCCA5
VCCA4
VCCA3
AGND5
13 14 15 16 17 18 19 20 21 22 23 24
100 nF
VCCO
FCE757
(1) As an internal input buffer is incorporated, depending on the CCD output impedance, an external input buffer may not be necessary and
consequently power savings can be made.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN; SHP) and th(IN; SHD) (see Chapter “Characteristics”).
(3) Pins SEN and VSYNC should be connected together when the vertical sync signal is not available.
Fig.11 Application diagram.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
handbook, full pagewidth
TDA9952
(1)
CCD
10-bit
data bus
TDA9952
DIGITAL
SIGNAL
PROCESSOR
MGU674
clamp
signals
clock
signals
PULSE
PATTERN
GENERATOR
HORIZONTAL
AND VERTICAL
DRIVER
(1) The external input buffer can be omitted for CCDs with low output impedance; for CCDs with high output impedance, a small current (around 1 mA)
is needed.
Fig.12 Typical imaging application.
Power and grounding recommendations
In a two-ground system, in order to minimize the noise
through the package and die parasitics, the following
recommendation must be implemented:
Care should be taken to minimize the noise when
designing a printed-circuit board for applications such as
PC cameras, surveillance cameras, camcorders and
digital still cameras.
• The ground pin associated with the digital outputs must
be connected to the digital ground plane and special
care should be taken to avoid feedthrough in the analog
ground plane. The analog and digital ground planes
must be connected together with an inductor as closely
as possible to the IC in order for them to have the same
DC voltage.
For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be taken into account, particularly with respect to
power and ground connections.
• The digital output pins and their associated lines should
be shielded by the digital ground plane which can then
be used as a return path for digital signals.
The connections between the CCD interface and the CDS
input should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analog and digital supplies provide the best
performance. If it is not possible to do this on the board
then the analog supply pins must be decoupled effectively
from the digital supply pins. The decoupling capacitors
must be placed as close as possible to the IC package.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
PACKAGE OUTLINES
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
2002 Aug 21
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
20
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
HVQFN48: plastic, heatsink very thin quad flat package; no leads;
48 terminals; body 7 x 7 x 0.85 mm
A
B
D
SOT619-1
terminal 1
index area
A
A4
E
detail X
C
e1
1/2 e
e
13
y
y1 C
∅v M C A B
b
∅w M C
24
L
25
12
e
e2
Eh
1/2 e
pin 1 index
1
36
48
37
Dh
X
0
2.5
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max.
mm
5 mm
A4
max.
b
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
0.80
0.35
0.18
7.05
6.95
5.25
4.95
7.05
6.95
5.25
4.95
0.5
5.5
5.5
0.50
0.30
0.2
1.00
w
0.1
y
y1
0.05
0.1
Note
1. Plastic or metal protrusions of 0.076 mm maximum per side are not included.
OUTLINE
VERSION
SOT619-1
2002 Aug 21
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
01-06-07
01-08-08
MO-220
21
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
SOLDERING
TDA9952
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Aug 21
22
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Aug 21
23
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Aug 21
24
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
NOTES
2002 Aug 21
25
TDA9952
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
NOTES
2002 Aug 21
26
TDA9952
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
NOTES
2002 Aug 21
27
TDA9952
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA74
© Koninklijke Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/04/pp28
Date of release: 2002
Aug 21
Document order number:
9397 750 09672