INTEGRATED CIRCUITS DATA SHEET TDA6502; TDA6502A; TDA6503; TDA6503A 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners Preliminary specification Supersedes data of 2000 Jan 24 File under Integrated Circuits, IC02 2000 Mar 16 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners CONTENTS TDA6502; TDA6502A; TDA6503; TDA6503A 13 TEST AND APPLICATION INFORMATION 13.1 13.2 13.3 13.4 13.5 13.6.1 13.6.2 13.6.3 Test circuits Measurement circuit Tuning amplifier Crystal oscillator Examples of I2C-bus data format sequences for TDA6502 and TDA6503 Write sequences to register C2 Read sequences from register C3 Examples of 3-wire bus data format sequences for TDA6502 and TDA6503 18-bit sequence 19-bit sequence 27-bit sequence 14 INTERNAL PIN CONFIGURATION 15 PACKAGE OUTLINE 16 SOLDERING 16.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 3.1 3.2 I2C-bus format 3-wire bus format 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.3 8.3.1 Control mode selection I2C-bus data format I2C-bus address selection Write mode Read mode Power-on reset 3-wire bus data format Power-on reset 9 LIMITING VALUES 16.2 16.3 16.4 10 THERMAL CHARACTERISTICS 17 DEFINITIONS 11 CHARACTERISTICS 18 LIFE SUPPORT APPLICATIONS TIMING CHARACTERISTICS 19 PURCHASE OF PHILIPS I2C COMPONENTS 12 2000 Mar 16 13.5.1 13.5.2 13.6 2 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 1 TDA6502; TDA6502A; TDA6503; TDA6503A FEATURES • Single-chip 5 V mixer/oscillator and synthesizer for cable TV and VCR tuners • Pin-to-pin compatible with TDA6402, TDA6402A, TDA6403 and TDA6403A • Universal bus protocol (I2C-bus or 3-wire bus) – Bus protocol for 18 or 19-bit transmission (3-wire bus) 2 • Cable tuners for TV and VCR (switched concept for VHF). – Extra protocol for 27-bit transmission (test modes and features for 3-wire bus) – Address + 4 data bytes transmission (I2C-bus ‘write’ mode) 3 GENERAL DESCRIPTION The TDA6502, TDA6502A, TDA6503 and TDA6503A are programmable 2-band mixers/oscillators and synthesizers intended for VHF/UHF TV and VCR tuners (see Fig.1). – Address + 1 status byte (I2C-bus ‘read’ mode) – 4 independent I2C-bus addresses. • 1 PMOS buffer for UHF band selection (25 mA) Partitioning of the bands is the responsibility of the customer providing VHF is below 500 MHz and UHF is below 900 MHz. • 3 PMOS buffers for general purpose, e.g. 2 VHF sub-bands, FM sound trap (25 mA) • 33 V tuning voltage output The devices include two double balanced mixers and two oscillators for the VHF and UHF band respectively, an IF amplifier and a PLL synthesizer. The VHF band can be split-up into two sub-bands using a proper oscillator application and a switchable inductor. • In-lock detector • 5-step analog-to-digital converter (3 bits in I2C-bus mode) • 15-bit programmable divider Two pins are available between the mixer output and the IF amplifier input to enable IF filtering for improved signal handling. • Programmable reference divider ratio (64, 80 or 128) • Programmable charge pump current (60 or 280 µA) • Varicap drive disable The port register provides four PMOS ports. Band selection is provided by port register UHF. When port register UHF is ‘on’, the UHF mixer-oscillator is active and the VHF band is switched off. When port register UHF is ‘off’, the VHF mixer-oscillator is active and the UHF band is off. Port registers VHFL and VHFH are used to select the VHF sub-bands. Port register FMST is a general purpose port, that can be used to switch an FM sound trap. When the ports are used, the sum of the drain currents has to be limited to 30 mA. • Balanced mixer with a common emitter input for VHF (single input) • Balanced mixer with a common base input for UHF (balanced input) • 2-pin common emitter oscillator for VHF • 4-pin common emitter oscillator for UHF • IF preamplifier with asymmetrical 75 Ω output impedance able to drive loads from 75 Ω upwards • Low power The synthesizer consists of a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase comparator (phase/frequency detector) combined with a charge pump which drives the tuning amplifier, including the 33 V output at pin VT. Depending on the reference divider ratio (64, 80 or 128), the phase comparator operates at 62.5, 50 or 31.25 kHz with a 4 MHz crystal. • Low radiation • Small size • The TDA6502A and TDA6503A differ from the TDA6502 and TDA6503 by the UHF port protocol in the I2C-bus mode (see Tables 3 and 4). 2000 Mar 16 APPLICATIONS 3 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners Table 1 Depending on the voltage applied to pin SW (see Table 2) the device is operating in the I2C-bus mode or 3-wire bus mode. In the 3-wire bus mode, pin LOCK/ADC is the ‘lock’ output of the PLL and is at LOW level when the PLL is locked. Lock detector bit FL of the status byte is set to logic 1 when the loop is locked and is read on the SDA line during a READ operation in I2C-bus mode only. I2C-bus format Five serial bytes (including the address byte) are required to address the device, select the VCO frequency, program the four ports, set the charge pump current and set the reference divider ratio. The device has four independent I2C-bus addresses which can be selected by applying a specific voltage to pin CE/AS. 3-wire bus format Data is transmitted to the device during a HIGH level on pin CE/AS (enable line). The device is accessible with 18-bit and 19-bit data formats (see Figs 4 and 5). The first four bits are used to program the PMOS ports and the remaining bits control the programmable divider. A 27-bit data format (see Fig.6) may also be used to set the charge pump current, the reference divider ratio and the test modes. It is not allowed to address the device with words whose length is different from 18, 19 or 27 bits. 2000 Mar 16 DATA WORD REFERENCE DIVIDER(1) FREQUENCY STEP 18-bit 64 62.50 kHz 19-bit 128 31.25 kHz 27-bit programmable programmable 1. The selection of the reference divider is given by an automatic identification of the data word length. When the 27-bit format is used, the reference divider is controlled by bits RSA and RSB (see Table 8). More details are given in Section 8.3. In the test mode, in both I2C-bus mode and 3-wire bus mode, pin LOCK/ADC is used as a test output for fREF and 1⁄ f 2 DIV. 3.2 Data word length for 3-wire bus format Note In the I2C-bus mode only, pin LOCK/ADC is the ADC input for digital AFC control. The ADC code is read during a READ operation on the I2C-bus. 3.1 TDA6502; TDA6502A; TDA6503; TDA6503A 4 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 4 QUICK REFERENCE DATA Measured over full voltage and temperature ranges. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage operating 4.5 5 5.5 V ICC supply current all PMOS ports are off; VCC = 5V − 71 − mA fXTAL crystal oscillator frequency − 4.0 − MHz Io(PMOS) PMOS port output current note 1 − − 30 mA Ptot total power dissipation note 2 − − 520 mW Tstg IC storage temperature −40 − +150 °C Tamb ambient temperature −20 − +85 °C fRF RF frequency VHF band 40 − 800 MHz UHF band 200 − 900 MHz VHF band − 20 − dB UHF band − 32 − dB VHF band − 7.5 − dB UHF band − 7 − dB VHF band − 110 − dBµV UHF band − 110 − dBµV GV voltage gain NF noise figure Vo output voltage (causing 1% cross modulation in channel) Notes 1. One buffer ‘on’, Io = 25 mA; two buffers ‘on’, maximum sum of Io = 30 mA. 2. The power dissipation is calculated as follows: 2 ( 0.5 × 33V ) P tot = V CC × ( I CC – I o ) + V P(sat) × I o + --------------------------------22 kΩ where: VP(sat) = output saturation voltage on the buffer output Io = source current for one buffer output. 5 ORDERING INFORMATION TYPE NUMBER TDA6502; TDA6502A; TDA6503; TDA6503A 2000 Mar 16 PACKAGE NAME DESCRIPTION VERSION SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 5 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 6 TDA6502; TDA6502A; TDA6503; TDA6503A BLOCK DIAGRAM VCC IFFIL1 IFFIL2 handbook, full pagewidth 5 (24) 6 (23) VHFIN 19 (10) (5) 24 3 (26) VHF OSCILLATOR VHF MIXER RF INPUT VHF BS BS BS (7) 22 (6) 23 RFGND UHFIN1 UHFIN2 4 (25) TDA6502 TDA6502A (TDA6503) (TDA6503A) IF PREAMPLIFIER (9) 20 (1) 28 1 (28) (2) 27 RF INPUT UHF 2 (27) UHF MIXER BS UHF OSCILLATOR (4) 25 BS BS (3) 26 (13) 16 XTAL 18 (11) XTAL OSCILLATOR 4 MHz REFERENCE DIVIDER 64, 80, 128 RSA fREF FL CL DA SW 14 (15) 13 (16) 11 (18) SCL SDA SW CHARGE PUMP UHFOSCOC2 UHFOSCOC1 UHFOSCIB1 CP T0, T1, T2 CP FL I2C-bus / 3-WIRE BUS TRANSCEIVER CE/AS CONTROL REGISTER CP T2 T1 fREF 1/2fDIV T0 RSA RSB OS PORT REGISTER 12 (17) UHF VHFH VHFL FMST GATE BS (8) 21 T0, T1, T2 15 (14) 9 (20) 8 (21) 7 (22) 10 (19) FCE527 PVHFH LOCK/ADC PUHF The pin numbers in parenthesis represent the TDA6503 and TDA6503A. Fig.1 Block diagram. 2000 Mar 16 UHFOSCIB2 OS 15-BIT FREQUENCY REGISTER 3-BIT ADC IFOUT OPAMP fDIV FL CE/AS OSCGND VT IN-LOCK DETECTOR POWER-DOWN DETECTOR VHFOSCIB (12) 17 PHASE COMPARATOR RSB 15-BIT PROGRAMMABLE DIVIDER VHFOSCOC 6 FMST PVHFL GND Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 7 TDA6502; TDA6502A; TDA6503; TDA6503A PINNING PIN SYMBOL UHFIN1 TDA6502; TDA6502A TDA6503; TDA6503A 1 28 DESCRIPTION UHF RF input 1 UHFIN2 2 27 UHF RF input 2 VHFIN 3 26 VHF RF input RFGND 4 25 RF ground IFFIL1 5 24 IF filter output 1 IFFIL2 6 23 IF filter output 2 PVHFL 7 22 PMOS port output, general purpose (e.g. VHF low sub-band) PVHFH 8 21 PMOS port output, general purpose (e.g. VHF high sub-band) PUHF 9 20 PMOS port output, UHF band FMST 10 19 PMOS port output, general purpose (e.g. FM sound trap) SW 11 18 bus format selection input: I2C-bus mode or 3-wire bus mode CE/AS 12 17 chip enable input in 3-wire bus mode or address selection input in I2C-bus mode DA 13 16 serial data input/output CL 14 15 serial clock input LOCK/ADC 15 14 lock detector output in 3-wire bus mode or ADC input in I2C-bus mode CP 16 13 charge pump output VT 17 12 tuning voltage output XTAL 18 11 crystal oscillator input VCC 19 10 supply voltage IFOUT 20 9 IF output GND 21 8 digital ground VHFOSCIB 22 7 VHF oscillator input base OSCGND 23 6 oscillator ground VHFOSCOC 24 5 VHF oscillator output collector UHFOSCIB1 25 4 UHF oscillator input 1 (base) UHFOSCOC1 26 3 UHF oscillator output 1 (collector) UHFOSCOC2 27 2 UHF oscillator output 2 (collector) UHFOSCIB2 28 1 UHF oscillator input 2 (base) 2000 Mar 16 7 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A handbook, halfpage handbook, halfpage UHFIN1 1 28 UHFOSCIB2 UHFOSCIB2 1 28 UHFIN1 UHFIN2 2 27 UHFOSCOC2 UHFOSCOC2 2 27 UHFIN2 VHFIN 3 26 UHFOSCOC1 UHFOSCOC1 3 26 VHFIN RFGND 4 25 UHFOSCIB1 UHFOSCIB1 4 25 RFGND IFFIL1 5 24 VHFOSCOC VHFOSCOC 5 24 IFFIL1 IFFIL2 6 23 OSCGND OSCGND 6 23 IFFIL2 PVHFL 7 VHFOSCIB 7 PVHFH 8 GND 8 PUHF 9 IFOUT 9 20 PUHF 19 VCC VCC 10 19 FMST 18 XTAL XTAL 11 VHFOSCIB TDA6502 22 TDA6502A 21 GND 20 IFOUT FMST 10 SW 11 22 PVHFL TDA6503 TDA6503A 21 PVHFH 18 SW CE/AS 12 17 VT VT 12 17 CE/AS DA 13 16 CP CP 13 16 DA CL 14 15 LOCK/ADC LOCK/ADC 14 15 CL FCE571 FCE570 Fig.2 8 Pin configuration for TDA6502 and TDA6502A. Fig.3 Pin configuration for TDA6503 and TDA6503A. FUNCTIONAL DESCRIPTION 8.1 Control mode selection The device is controlled via the I2C-bus or the 3-wire bus, depending on the voltage applied to pin SW (see Table 2). A LOW level on pin SW enables the I2C-bus: pins CE/AS, DA and CL are used as address selection (AS), serial data (SDA) and serial clock (SCL) input respectively. A HIGH level on pin SW enables the 3-wire bus: pins CE/AS, DA and CL are used as chip enable (CE), data and clock inputs respectively. Table 2 Bus format selection PIN I2C-BUS MODE 3-WIRE BUS MODE TDA6502; TDA6502A TDA6503; TDA6503A SW 11 18 LOW-level voltage or ground HIGH-level voltage or open-circuit CE/AS 12 17 address selection input enable input DA 13 16 serial data input data input CL 14 15 serial clock input clock input LOCK/ADC 15 14 ADC input or test output lock detector output or test output SYMBOL 2000 Mar 16 8 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 8.2 The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission (address byte + 4 data bytes). The device can also be partially programmed providing that the first data byte following the address byte is divider byte DB1 or the control byte CB. I2C-bus data format 8.2.1 I2C-BUS ADDRESS SELECTION The module address contains programmable address bits MA1 and MA0 (see Tables 3, 4 and 9) which offer the possibility of having several synthesizers (up to 4) in one system by applying a specific voltage on pin CE/AS. The relationship between bits MA1 and MA0 and the input voltage applied to pin CE/AS is given in Table 6. 8.2.2 The first bit of byte DB1 indicates whether frequency data (first bit = 0) or control and band-switch data (first bit = 1) will follow. Until an I2C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to re-address the device. WRITE MODE The write mode is defined by the address byte ADB with bit R/W = 0 (see Tables 3 and 4). The frequency register is loaded after the 8th clock pulse of byte DB2, the control register is loaded after the 8th clock pulse of the byte CB and the band-switch register is loaded after the 8th clock pulse of byte BB. Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are needed to fully program the device. Table 3 TDA6502; TDA6502A; TDA6503; TDA6503A I2C-bus data format for write mode of TDA6502 and TDA6503 BITS NAME BYTE MSB Address byte ADB Divider byte 1 Divider byte 2 LSB MA0 R/W = 0 N10 N9 N8 N2 N1 N0 T0 RSA RSB OS FMST PUHF PVHFH PVHFL 1 1 0 0 0 MA1 DB1 0 N14 N13 N12 N11 DB2 N7 N6 N5 N4 N3 Control byte CB 1 CP T2 T1 Band-switch byte BB X X X X Table 4 I2C-bus data format for write mode of TDA6502A and TDA6503A BIT NAME BYTE MSB LSB Address byte ADB 1 1 0 0 0 MA1 MA0 R/W = 0 Divider byte 1 DB1 0 N14 N13 N12 N11 N10 N9 N8 Divider byte 2 DB2 N7 N6 N5 N4 N3 N2 N1 N0 Control byte CB 1 CP T2 T1 T0 RSA RSB OS Band-switch byte BB X X X X PUHF FMST PVHFH PVHFL 2000 Mar 16 9 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners Table 5 TDA6502; TDA6502A; TDA6503; TDA6503A Description of the bits used in Tables 3 and 4 BIT DESCRIPTION MA1 and MA0 programmable address bits (see Table 6) R/W logic 0 for write mode N14 to N0 programmable divider bits: N = N14 × 214 + N13 × 213 + ... + N1 × 21 + N0 CP charge pump current control bit: logic 0: charge pump current is 60 µA logic 1: charge pump current is 280 µA (default) T2, T1 and T0 test bits (see Table 7) RSA and RSB reference divider ratio select bits (see Table 8) OS tuning amplifier control bit: logic 0: tuning voltage is ‘on’ (during normal operating) logic 1: tuning voltage is ‘off’; high-impedance output of pin VT (default) PVHFL, PVHFH, PUHF and FMST PMOS ports control bits: logic 0: corresponding buffer is ‘off’ (default) logic 1: corresponding buffer is ‘on’ X don’t care Table 6 Address selection bits (I2C-bus mode) MA1 MA0 0 0 0 V to 0.1VCC 0 1 0.2VCC to 0.3VCC or open-circuit 1 0 0.4VCC to 0.6VCC 1 1 0.9VCC to 1.0VCC Table 7 VOLTAGE APPLIED TO PIN CE/AS Test mode bits T2 T1 T0 TEST MODE 0 0 0 normal mode 0 0 1 normal mode (note 1) 0 1 X charge pump is off 1 1 0 charge pump is sinking current 1 1 1 charge pump is sourcing current 1 0 0 1 0 1 fREF is available on pin LOCK/ADC (note 2) 1⁄ f 2 DIV is available on pin LOCK/ADC (note 2) Notes 1. This is the default mode at Power-on reset. 2. The ADC input cannot be used when these test modes are active; see Section 8.2.3 for more information. 2000 Mar 16 10 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners Table 8 TDA6502; TDA6502A; TDA6503; TDA6503A Reference divider ratio select bits RSA RSB REFERENCE DIVIDER RATIO FREQUENCY STEP (kHz) X 0 80 50 0 1 128 31.25 1 1 64 62.5 8.2.3 READ MODE The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9). After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the microcontroller to generate a STOP condition. Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1) A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC information to the microcontroller of the IF section of the television. Table 9 Read data format BIT NAME Address byte Status byte BYTE MSB(1) LSB ADB 1 1 0 0 0 MA1 MA0 R/W = 1 SB POR FL R 1 1 A2 A1 A0 Note 1. MSB is transmitted first. Table 10 Description of the bits used in Table 9 BIT DESCRIPTION MA1 and MA0 programmable address bits (see Table 6) R/W logic 1 for read mode POR Power-on reset flag: logic 0: at power-off logic 1: at power-on FL in-lock flag: logic 0: loop is not locked logic 1: loop is locked R ready flag: logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked logic 1: in other conditions A2, A1 and A0 2000 Mar 16 digital outputs of the 5-level ADC (see Table 11) 11 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A Table 11 Digital outputs for analog input levels (note 1) A2 A1 A0 VOLTAGE APPLIED TO PIN LOCK/ADC 0 0 0 0 to 0.15VCC 0 0 1 0.15VCC to 0.30VCC 0 1 0 0.30VCC to 0.45VCC 0 1 1 0.45VCC to 0.60VCC 1 0 0 0.60VCC to 1.00VCC Note 1. Accuracy is ±0.03 × VCC. 8.2.4 POWER-ON RESET The power-on detection threshold voltage VPOR is set to 3.2 V at room temperature. Below this threshold the device is reset to the power-on state. At power-on state the following actions take place: • The charge pump current is set to 280 µA • The tuning voltage output is disabled • The test bits T2, T1 and T0 are set to logic ‘001’ • The divider bit RSB is set to logic 1 • Port register UHF is ‘off’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the VHF oscillator and the VHF mixer are switched on. Port registers VHFL and VHFH are ‘off’, which means that the VHF tank circuit is operating in the VHF low sub-band. The tuning amplifier is switched off until the first transmission. In that case, the tank circuit is supplied with the maximum tuning voltage. The oscillator is therefore operating at the end of the VHF low sub-band. Table 12 Default setting of the bits at Power-on reset BITS NAME BYTE MSB LSB Address byte ADB 1 1 0 0 0 MA1 MA0 X Divider byte 1 DB1 0 X X X X X X X Divider byte 2 DB2 X X X X X X X X Control byte CB 1 1 0 0 1 X 1 1 Band switch byte BB X X X X 0 0 0 0 2000 Mar 16 12 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 8.3 8.3.1 3-wire bus data format TDA6502; TDA6502A; TDA6503; TDA6503A POWER-ON RESET During a HIGH level on pin CE/AS (enable line), the data is clocked into the data register at the HIGH-to-LOW transition of the clock (see Figs 4 and 5). The power-on detection threshold voltage VPOR is set to 3.2 V at room temperature. Below this threshold the device is reset to the power-on state. The first four bits control the PMOS ports and are loaded into the internal band-switch register on the 5th rising edge of the clock pulse. At power-on state the following actions take place: The frequency bits are loaded into the frequency register at the HIGH-to-LOW transition of the enable line when an 18-bit or 19-bit data word is transmitted. When a 27-bit data word is transmitted, the frequency bits are loaded into the frequency register on the 20th rising edge of the clock pulse and the control bits at the HIGH-to-LOW transition of the enable line (see Fig.6). • The divider bit RSB is set to logic 1 • The charge pump current is set to 280 µA • The test bits T2, T1 and T0 are set to logic ‘001’ • The tuning voltage output is disabled • The tuning amplifier control bit OS is automatically reset to logic 0 in 18-bit and 19-bit modes when the first data word is received to allow normal operation • Port register UHF is ‘off’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the VHF oscillator and the VHF mixer are switched on. Port registers VHFL and VHFH are ‘off’, which means that the VHF tank circuit is operating in the VHF low sub-band. The tuning amplifier is switched off until the first transmission. In that case, the tank circuit is supplied with the maximum tuning voltage. The oscillator is therefore operating at the end of the VHF low sub-band In this control mode the reference divider is given by bits RSA and RSB (see Table 8). The test bits T2, T1 and T0, the charge pump bit CP, the ratio select bit RSB and bit OS can only be selected or changed with a 27-bit transmission. They remain programmed if an 18-bit or 19-bit transmission occurs. Only bit RSA is controlled by the transmission length when the 18-bit or 19-bit format is used. When an 18-bit data word is transmitted, the most significant bit of the divider (bit N14) is internally set to logic 0 and bit RSA is set to logic 1. When a 19-bit data word is transmitted, bit RSA is set to logic 0. • The reference divider ratio is set to 64 or 128 if the first sequence to the device has 18 bits or 19 bits; if the sequence has 27 bits, the reference divider ratio is set by bits RSA and RSB (see Table 8). It is not allowed to address the devices with words whose length is different from 18, 19 or 27 bits. A data word of less than 18 bits will not affect the frequency register of the device. The definition of the bits is unchanged compared to the I2C-bus mode. 2000 Mar 16 13 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A handbook, full pagewidth INVALID DATA BAND-SWITCH DATA FMST PUHF FREQUENCY DATA INVALID DATA PVHFL PVHFH N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 DA 1 4 5 18 CL CE LOAD BAND-SWITCH REGISTER LOAD FREQUENCY REGISTER FCE572 Fig.4 18-bit data format (bit RSA = 1). handbook, full pagewidth INVALID BAND-SWITCH DATA DATA FMST PUHF FREQUENCY DATA INVALID DATA PVHFL PVHFH N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 DA 1 4 5 19 CL CE LOAD BAND-SWITCH REGISTER LOAD FREQUENCY REGISTER FCE573 Fig.5 19-bit data format (bit RSA = 0). 2000 Mar 16 14 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners handbook, fullINVALID pagewidth BAND-SWITCH DATA DATA FMST PUHF TDA6502; TDA6502A; TDA6503; TDA6503A FREQUENCY DATA INVALID DATA TEST AND FEATURES DATA PVHFL PVHFH N14 N13 N12 N2 N1 N0 X 19 20 CP T2 T1 T0 RSA RSB OS DA 1 4 5 27 CL CE LOAD BAND-SWITCH REGISTER LOAD FREQUENCY REGISTER LOAD CONTROL REGISTER FCE574 Fig.6 27-bit data format; test and features mode. 2000 Mar 16 15 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); note 1. PIN SYMBOL VCC PARAMETER TDA6502; TDA6503; TDA6502A TDA6503A 19 10 MIN. −0.3 DC supply voltage OVS pulse time is 1 s; maximum current is − 1A MAX. UNIT +6 V 8 V VPn 7 to 10 19 to 22 PMOS port output voltage −0.3 VCC +0.3 V IPn 7 to 10 19 to 22 PMOS port output current −1 +30 mA VCP 16 13 charge pump output voltage −0.3 VCC +0.3 V VSW 11 18 bus format selection input voltage −0.3 VCC+ 0.3 V VVT 17 12 tuning voltage output −0.3 +35 V VLOCK/ADC 15 14 lock/ADC output/input voltage −0.3 VCC +0.3 V VCL 14 15 serial clock input voltage −0.3 +6 V VDA 13 16 serial data input/output voltage −0.3 +6 V IDA 13 16 data output current −1 +10 mA VCE/AS 12 17 chip enable/address selection input voltage −0.3 +6 V VXTAL 18 11 crystal input voltage −0.3 VCC +0.3 V 1 to 6, 19 to 28 1 to 10, 23 to 28 output current of each pin to ground − −10 mA tsc(max) − − maximum short-circuit time (all pins to VCC − and all pins to GND, OSCGND and RFGND) 10 s Tstg − − storage temperature −40 +150 °C Tamb − − ambient temperature −20 +85 °C Tj − − junction temperature − 150 °C IO(n) (I2C-bus mode) Note 1. Maximum ratings can not be exceeded, not even momentarily without causing irreversible IC damage. Maximum ratings can not be accumulated. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2000 Mar 16 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 16 TYP. UNIT 110 K/W Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 11 CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply; Tamb = 25 oC VCC supply voltage ICC supply current 4.5 5.0 5.5 V all PMOS ports ‘off’ − 71 78 mA one PMOS port ‘on’ and sourcing 25 mA − 103 113 mA one PMOS port ‘on’ and sourcing − 25 mA; a second port ‘on’ and sourcing 5 mA 111 122 mA − 3.2 − V at VCC = 5 V PLL part; VCC = 4.5 to 5.5 V; Tamb = −20 to +85 °C; unless otherwise specified FUNCTIONAL RANGE VPOR power-on reset supply voltage N divider ratio below this supply voltage power-on reset becomes active 15-bit frequency word 64 − 32767 14-bit frequency word 64 − 16383 fXTAL crystal oscillator frequency RXTAL = 25 to 300 Ω − 4.0 − MHz ZXTAL input impedance (absolute value) fXTAL = 4 MHz 600 1200 − Ω PMOS PORTS: PINS PUHF, PVHFL, PVHFH AND FMST IPn(off) leakage current VCC = 5.5 V; VPn = 0 V −10 − − µA VPn(sat) output saturation voltage VPn(sat) = VCC − VPn; one buffer output is ‘on’ and sourcing 25 mA − 0.25 0.4 V LOCK OUTPUT: PIN LOCK/ADC (IN 3-WIRE BUS MODE) IUNLOCK output current when the PLL is out-of-lock VCC = 5.5 V; VO= 5.5 V − − 200 µA VUNLOCK output saturation voltage when the PLL is out-of-lock VUNLOCK = VCC − VO; IO = 200 µA − 0.4 0.8 V VLOCK output voltage the PLL is locked − 0.2 0.40 V ADC INPUT: PIN LOCK/ADC (IN I2C-BUS MODE) VADC ADC input voltage see Table 11 0 − VCC V IADC(H) HIGH-level input current VADC = VCC − − 10 µA IADC(L) LOW-level input current VADC = 0 V −10 − − µA BUS FORMAT SELECTION: PIN SW VSW(L) LOW-level input voltage 0 − 1.5 V VSW(H) HIGH-level input voltage 3 − VCC V ISW(H) HIGH-level input current VSW = VCC − − 10 µA ISW(L) LOW-level input current VSW = 0 V −100 − − µA 2000 Mar 16 17 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners SYMBOL PARAMETER TDA6502; TDA6502A; TDA6503; TDA6503A CONDITIONS MIN. TYP. MAX. UNIT CHIP ENABLE/ADDRESS SELECTION INPUT: PIN CE/AS VCE/AS(L) LOW-level input voltage 0 − 1.5 V VCE/AS(H) HIGH-level input voltage 3 − 5.5 V ICE/AS(H) HIGH-level input current VCE/AS = 5.5 V − − 10 µA ICE/AS(L) LOW-level input current VCE/AS = 0 V −10 − − µA CLOCK AND DATA INPUTS: PINS CL AND DA VCL(L), VDA(L) LOW-level input voltage 0 − 1.5 V VCL(H), VDA(H) HIGH-level input voltage 3 − 5.5 V VBUS = 5.5 V; VCC = 0 V − − 10 µA VBUS = 5.5 V; VCC = 5.5 V − − 10 µA VBUS = 1.5 V; VCC = 0 V − − 10 µA VBUS = 0 V; VCC = 5.5 V −10 − − µA ICL(H), IDA(H) HIGH-level input current ICL(L), IDA(L) LOW-level input current DATA OUTPUT: PIN DA (IN I2C-BUS MODE ONLY) IDA(H) HIGH-level output current VDA = 5.5 V − − 10 µA VDA(H) HIGH-level output voltage IDA = 3 mA (sink current) − − 0.4 V − − 400 kHz CLOCK FREQUENCY (I2C-BUS MODE) fclk clock frequency CHARGE PUMP OUTPUT: PIN CP ICP(H) HIGH-level input current (absolute value) CP = 1 − 280 − µA ICP(L) LOW-level input current (absolute value) CP = 0 − 60 − µA ICP(leak) off-state leakage current T2 = 0; T1 = 1 −15 −0.5 +15 nA OS = 1; tuning supply is 33 V − − 10 µA 0.2 − 32.7 V TUNING VOLTAGE OUTPUT: PIN VT IVT(off) leakage current when switched-off VVT output voltage when the loop OS = 0; T2 = 0; T1 = 0; T0 = 1; is closed RL = 27 kΩ; tuning supply is 33 V Mixer/oscillator part; VCC = 5 V; Tamb = 25 oC; measurements related to the measurement circuit (see Fig.19) VHF MIXER (INCLUDING IF PREAMPLIFIER) fRF(o) RF operational frequency 800 MHz fRF RF frequency note 1 55.25 − 361.25 MHz Gv voltage gain fRF = 57.5 MHz; see Fig.12 17.5 20 22.5 dB NF noise figure 2000 Mar 16 40 fRF = 363.5 MHz; see Fig.12 17.5 20 22.5 dB fRF = 50 MHz; see Figs 13 and 14 − 7.5 10 dB fRF = 150 MHz; see Figs 13 and 14 − 7.5 10 dB fRF = 300 MHz; see Fig.14 − 7.5 10 dB 18 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT 110 − dBµV 107 110 − dBµV − 83 − dBµV optimum source fRF = 50 MHz conductance for noise figure fRF = 150 MHz − 0.7 − mS − 0.9 − mS fRF = 300 MHz − 1.5 − mS fRF = 55.25 MHz; see Fig.7 − 0.3 − mS fRF = 361.25 MHz; see Fig.7 − 0.4 − mS fRF = 57.5 to 357.5 MHz; see Fig.7 − 1.35 − pF 600 MHz output voltage (causing 1% fRF = 55.25 MHz; see Fig.15 cross modulation in channel) fRF = 361.25 MHz; see Fig.15 Vi input voltage (causing fRF = 361.25 MHz; note 2 pulling-in channel at 750 Hz) gos Ci MIN. 107 Vo gi TDA6502; TDA6502A; TDA6503; TDA6503A input conductance input capacitance VHF OSCILLATOR fOSC(o) oscillator operational frequency fOSC oscillator frequency ∆fOSC(V) 60 101 − 407 MHz oscillator frequency variation ∆VCC = 5%; note 4 with supply voltage ∆VCC = 10%; note 4 − 60 − kHz − 110 − kHz ∆fOSC(T) oscillator frequency variation ∆T = 25 °C; with compensation; with temperature note 5 − 1600 − kHz ∆fOSC(t) oscillator frequency drift 400 − kHz ΦOSC phase noise, carrier-to-noise ±100 kHz frequency offset; worst sideband case in the frequency range − 105 − dBc/Hz RSC ripple susceptibility of VCC (peak-to-peak value) 15 30 − mV 900 MHz note 3 5 s to 15 min after switch-on; note 6 − VCC = 5 V; worst case in the frequency range; ripple frequency 500 kHz; note 7 UHF MIXER (INCLUDING IF PREAMPLIFIER) fRF(o) RF operational frequency fRF RF frequency Gv voltage gain NF Vo Vi 2000 Mar 16 200 note 1 367.25 − 801.25 MHz fRF = 369.5 MHz; see Fig.16 29 32 35 dB fRF = 803.5 MHz; see Fig.16 29 32 35 dB fRF = 369.5 MHz; see Fig.17 − 7 9 dB fRF = 803.5 MHz; see Fig.17 − 7 9 dB output voltage (causing 1% fRF = 367.25 MHz; see Fig.18 cross modulation in channel) fRF = 801.25 MHz; see Fig.18 107 110 − dBµV 107 110 − dBµV input voltage (causing fRF = 801.25 MHz; note 2 pulling in channel at 750 Hz) − 85 − dBµV noise figure (not corrected for image) 19 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners SYMBOL Zi PARAMETER TDA6502; TDA6502A; TDA6503; TDA6503A CONDITIONS input impedance (RS + jLSω) RS at fRF = 367.25 MHz; see Fig.8 MIN. − TYP. 26 MAX. − UNIT Ω RS at fRF = 801.25 MHz; see Fig.8 − 28 − Ω LS at fRF = 367.25 MHz; see Fig.8 − 8.5 − nH LS at fRF = 801.25 MHz; see Fig.8 − 8 − nH 1000 MHz UHF OSCILLATOR fOSC(o) oscillator operational frequency fOSC oscillator frequency ∆fOSC(V) 300 413 − 847 MHz oscillator frequency variation ∆VCC = 5%; note 4 with supply voltage ∆VCC = 10%; note 4 − 35 − kHz − 100 − kHz ∆fOSC(T) oscillator frequency variation ∆T = 25 °C; with compensation; with temperature note 5 − 500 − kHz ∆fOSC(t) oscillator frequency drift − 120 − kHz ΦOSC phase noise, carrier-to-noise ±100 kHz frequency offset; worst sideband case in the frequency range − 105 − dBc/Hz RSC ripple susceptibility of VCC (peak-to-peak value) 15 30 − mV 60 MHz note 3 5 s to 15 min after switching on; note 6 VCC = 5 V; worst case in the frequency range; ripple frequency 500 kHz; note 7 IF PREAMPLIFIER IF IF operational frequency S22 output reflection coefficient Zo output impedance (RS + jLSω) 30 magnitude; see Fig.9 − −12.8 − dB phase; see Fig.9 − 0.2 − degree RS at 43.5 MHz; see Fig.9 − 80 − Ω LS at 43.5 MHz; see Fig.9 − 0.5 − nH REJECTION AT THE IF OUTPUT INTdiv level of divider interferences in the IF signal worst case; note 8 − 16 20 dBµV INTxtal crystal oscillator interferences rejection VIF = 100 dBµV; worst case in the frequency range; note 9 60 − − dBc INTref reference frequency rejection VIF = 100 dBµV; worst case in the frequency range; fREF = 62.5 kHz; note 10 60 − − dBc INTch6 channel 6 beat VRF(pix) = VRF(snd) = 80 dBµV; note 11 tbf 54 − dBc INTchA-5 channel A-5 beat VRF(pix) = 80 dBµV; note 12 tbf 60 − dBc Notes 1. The RF frequency range is defined by the oscillator frequency range and the IF frequency. 2. This is the level of the RF signal (100% amplitude modulated with 11.89 kHz) that causes a 750 Hz frequency deviation on the oscillator signal; it produces sidebands 30 dB below the level of the oscillator signal. 3. Limits are related to the tank circuits used in Fig.19; frequency bands may be adjusted by the choice of external components. 2000 Mar 16 20 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 4. The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from VCC = 5 to 4.75 V (4.5 V) or from VCC = 5 to 5.25 V (5.5 V). The oscillator is free running during this measurement. 5. The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from Tamb = 25 to 50 °C or from Tamb = 25 to 0 °C. The oscillator is free running during this measurement. 6. Switch-on drift is defined as the change in oscillator frequency between 5 s and 15 min after switch-on. The oscillator is free running during this measurement. 7. The ripple susceptibility is measured for a 500 kHz ripple at the IF output using the measurement circuit of Fig.19; the level of the ripple signal is increased until a difference of 53.5 dB occurs between the IF carrier fixed at 100 dBµV and the sideband components. 8. This is the level of divider interferences close to the IF frequency. For example channel C: fOSC = 179 MHz, 1⁄ f 4 OSC = 44.75 MHz. The VHFIN input must be left open (i.e. not connected to any load or cable); The UHFIN1 and UHFIN2 inputs are connected to a hybrid. 9. Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. The rejection has to be greater than 60 dB for an IF output signal of 100 dBµV. 10. The reference frequency rejection is the level of reference frequency sidebands related to the sound sub-carrier. 11. Channel 6 beat is the interfering product of fRF(pix) + fRF(snd) − fOSC of channel 6 at 42 MHz. 12. Channel A-5 beat is the interfering product of fRF(pix), fIF and fOSC of channel A-5: fbeat = 45.5 MHz. The possible mechanisms are: fOSC − 2 × fIF or 2 × fRF(pix) − fOSC. For the measurement: VRF = 80 dBµV. 1 handbook, full pagewidth 2 0.5 0.2 5 10 −j 10 ∞ 5 2 1 0.5 0.2 40 MHz 0 +j 10 400 MHz 5 0.2 2 0.5 1 FCE528 Fig.7 Input admittance (S11) of the VHF mixer input (40 to 400 MHz); Y0 = 20 mS. 2000 Mar 16 21 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 1 handbook, full pagewidth 0.5 2 860 MHz 0.2 5 350 MHz 10 +j 0.2 0 0.5 1 2 5 10 ∞ −j 10 5 0.2 2 0.5 1 FCE529 Fig.8 Input impedance (S11) of the UHF mixer input (350 to 860 MHz); Z0 = 50 Ω. 1 handbook, full pagewidth 0.5 2 0.2 5 10 +j 0 0.2 0.5 1 20 MHz 2 5 10 ∞ 100 MHz −j 10 5 0.2 2 0.5 1 FCE530 Fig.9 Output impedance (S22) of the IF amplifier (20 to 60 MHz); Z0 = 50 Ω. 2000 Mar 16 22 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 12 TIMING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. UNIT 3-wire bus timing tHIGH clock HIGH time see Fig.10 2 µs tSU;DA data set-up time see Fig.10 2 µs tHD;DA data hold time see Fig.10 2 µs tSU;ENCL enable-to-clock set-up time see Fig.10 10 µs tHD;ENDA enable-to-data hold time see Fig.10 2 µs tEN enable time between two transmissions see Fig.11 10 µs tHD;ENCL enable-to-clock active edge hold time see Fig.11 6 µs INVALID DATA handbook, full pagewidth DA INVALID DATA LSB MSB CL tHIGH tSU;DA tHD;DA CE tSU;ENCL tHD;ENDA FCE575 Fig.10 Timing diagram for 3-wire bus; DA, CL and CE. handbook, halfpage tEN CE CL tHD;ENCL FCE576 Fig.11 Timing diagram for 3-wire bus; CE and CL. 2000 Mar 16 23 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 13 TEST AND APPLICATION INFORMATION 13.1 Test circuits handbook, full pagewidth signal source 50 Ω 27 Ω VHFIN e Vmeas V 50 Ω IFOUT D.U.T. Vi spectrum analyzer Vo 50 Ω V'meas RMS voltmeter FCE577 Zi >> 50 Ω ⇒ Vi = 2 × Vmeas = 80 dBµV Vi = Vmeas + 6 dB = 80 dBµV 50 + 27 Vo = V’meas × ------------------50 Vo Gv = 20 log -----Vi Fig.12 Gain measurement in VHF band. I1 handbook, full pagewidth BNC I3 PCB C1 L1 BNC C2 PCB C3 plug plug I2 RIM-RIM RIM-RIM C4 (a) (b) FCE578 (a) For fRF = 50 MHz: (b) For fRF = 150 MHz: mixer A frequency response measured = 57 MHz, loss = 0 dB image suppression = 16 dB mixer A frequency response measured = 150.3 MHz, loss = 1.3 dB image suppression = 13 dB C1 = 9 pF C2 = 15 pF L1 = 7 turns (∅ 5.5 mm, wire ∅ = 0.5 mm) l1 = semi rigid cable (RIM) of 5 cm long (semi rigid cable (RIM); 33 dB/100 m; 50 Ω; 96 pF/m). C3 = 5 pF C4 = 25 pF l2 = semi rigid cable (RIM): 30 cm long l3 = semi rigid cable (RIM) of 5 cm long (semi rigid cable (RIM); 33 dB/100 m; 50 Ω; 96 pF/m). Fig.13 Input circuit for optimum noise figure in VHF band. 2000 Mar 16 24 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A handbook, full pagewidth 27 Ω NOISE SOURCE VHFIN RIM BNC INPUT CIRCUIT IFOUT NOISE FIGURE METER D.U.T. FCE579 NF = NFmeas − loss (of input circuit) (dB). Fig.14 Noise figure (NF) measurement in VHF band. FILTER handbook, full pagewidth 50 Ω AM = 30% 2 kHz unwanted signal source eu 27 Ω A VHFIN C 18 dB attenuator IFOUT 45.75 MHz HYBRID D.U.T. Vo V Vmeas modulation analyzer 50 Ω 50 Ω B ew wanted signal source D 50 Ω RMS voltmeter FCE580 50 + 27 Vo = Vmeas × ------------------50 Wanted output signal at fRF(w) = 55.25 (361.25) MHz; Vo(w) = 100 dBµV. Measuring the level of the unwanted output signal Vo(u) causing 0.3% AM modulation in the wanted output signal; fRF(u) = 59.75 (366.75) MHz. fOSC = 101 (407) MHz. Filter characteristics: fc = 45.75 MHz, f−3 dB(BW) = 1.4 MHz, f−30 dB(BW) = 3.1 MHz. Fig.15 Cross modulation measurement in VHF band. 2000 Mar 16 25 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners handbook, full pagewidth e 50 Ω TDA6502; TDA6502A; TDA6503; TDA6503A signal source 27 Ω A Vmeas V 50 Ω Vi UHFIN1 IFOUT C HYBRID B D.U.T. spectrum analyzer Vo V'meas UHFIN2 D RMS 50 Ω voltmeter FCE581 Loss (in hybrid) = 1 dB. Vi = Vmeas − loss (in hybrid) = 70 dBµV. 50 + 27 Vo = V’meas × ------------------50 Vo Gv = 20 log -----Vi Fig.16 Gain (Gv) measurement in UHF band. handbook, full pagewidth 27 Ω NOISE SOURCE A C UHFIN HYBRID B D IFOUT NOISE FIGURE METER D.U.T. UHFIN 50 Ω FCE582 Loss (in hybrid) = 1 dB. NF = NFmeas − loss (in hybrid). Fig.17 Noise figure (NF) measurement in bands UHF. 2000 Mar 16 50 Ω 26 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A FILTER handbook, full pagewidth AM = 30% 50 Ω 2 kHz unwanted signal source eu A C ew C 27 Ω UHFIN IFOUT 45.75 MHz HYBRID HYBRID B B 50 Ω wanted signal source A 18 dB attenuator D 50 Ω D D.U.T. Vo V Vmeas modulation analyzer 50 Ω UHFIN RMS voltmeter 50 Ω FCE583 50 + 27 Vo = Vmeas × ------------------50 Wanted output signal at fRF(w) = 367.25 (801.25) MHz; Vo(w) = 100 dBµV. Measuring the level of the unwanted output signal Vo(u) causing 0.3% AM modulation in the wanted output signal; fRF(u) = 371.25 (805.75) MHz. fOSC = 413 (847) MHz. Filter characteristics: fc = 45.75 MHz, f−3 dB(BW) = 1.4 MHz, f−30 dB(BW) = 3.1 MHz. Fig.18 Cross modulation measurement in UHF band. 2000 Mar 16 27 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... W3 C2 4.7 nF UHFIN2 C3 4.7 nF C4 VHFIN IFFIL1 5(24) 24(5) IFFIL2 23(6) OSCGND R16 330 Ω FMST 7(22) TDA6502/2A 22(7) (TDA6503/3A) 9(20) 20(9) 19(10) 10(19) 18(11) XTAL SW 11(18) DA VCC CL CON1 TR1 D2 82 pF L3 C17 4.7 nF C16 BA792 10 kΩ C6 C14 4.7 nF C18 4.7 nF L5 VCC Y1 13(16) 16(13) 14(15) 100 nF 15(14) LOCK/ADC C21 C20 R9 R8 22 nF VHF-HIGH 680 Ω VHF-LOW 3.9 kΩ 18 pF CON3 R12 J1 R14 2.2 kΩ C23 10 nF R13 22 kΩ C22 330 pF R22 330 Ω R11 27 Ω R26 6.8 kΩ R25 C26 10 µF (16 V) 1 kΩ LOCK/ADC for test purpose only R24 TR2 Fig.19 Measurement circuit. GND for test purpose only VS handbook, full pagewidth LOCK +5 V EN/AS The pin numbers in brackets represent the TDA6503 and TDA6503A. BC847B FCE481 J2 04 03 02 01 Preliminary specification 01 02 03 04 05 06 J3 +33 V 68 kΩ RIPPLE D3 3.9 kΩ R10 C19 4.7 nF 12 kΩ 22 kΩ R7 2 pF 17(12) VT R19 330 Ω R6 5.6 Ω C15 TDA6502; TDA6502A; TDA6503; TDA6503A C27 10 µF (16 V) BB178 C13 L2 12(17) CP R5 +5 V BC847B R20 330 Ω R21 330 Ω CLOCK GND DATA 28 CE/AS 22 kΩ C11 1.2 pF IFOUT VCC C12 27 pF R2 27 Ω VHFOSCIB 8(21) L1 C10 1.2 pF VHFOSCOC 21(8) GND CON4 open for 3-wire UHFOSCIB1 R3 22 kΩ D1 BB179 R4 C9 1.2 pF 2 pF 6(23) PUHF R17 330 Ω for test purpose only UHFOSCOC1 25(4) PVHFH R18 330 Ω UHFOSCIB2 RFGND 4(25) PVHFL R15 330 Ω 27(2) 26(3) L4 15 pF D4 LED D5 LED D6 LED D7 LED 2(27) C8 1.2 pF UHFOSCOC2 3(26) 15 pF C5 28(1) Philips Semiconductors 4.7 nF 1(28) Measurement circuit W2 UHFIN1 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 13.2 2000 Mar 16 C1 W1 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners Table 13 Capacitors (all SMD and NP0) COMPONENT TDA6502; TDA6502A; TDA6503; TDA6503A COMPONENT VALUE VALUE R15 330 Ω C1 4.7 nF R16 330 Ω C2 4.7 nF R17 330 Ω C3 4.7 nF R18 330 Ω C4 15 pF R19 330 Ω C5 15 pF R20 330 Ω C6 22 nF R21 330 Ω C8 1.2 pF (N750) R22 330 Ω C9 1.2 pF (N750) R24 68 kΩ C10 1.2 pF(N750) R25 1 kΩ C11 1.2 pF (N750) R26 6.8 kΩ C12 27 pF (N750) C13 2 pF (N750) C14 2 pF (N750) C15 82 pF (N750) D1 BB179 C16 4.7 nF D2 BB178 C17 4.7 nF D3 BA792 C18 4.7 nF IC C19 4.7 nF TDA6502; TDA6502A TDA6503; TDA6503A C20 18 pF C21 100 nF C22 330 pF C23 10 nF L1 1.5 turns; diameter 1.5 mm C26 10 µF (16 V, electrolytic) L2 2.5 turns; diameter 2.5 mm C27 10 µF (16 V, electrolytic) L3 7.5 turns; diameter 3.0 mm L5 2.5 turns; diameter 2.5 mm Table 15 Diodes and ICs COMPONENT Table 16 Coils (note 1) COMPONENT Table 14 Resistors (all SMD) VALUE Note COMPONENT VALUE R2 27 Ω R3 22 kΩ R4 22 kΩ R5 22 kΩ R6 5.6 Ω R7 10 kΩ R8 680 Ω R9 3.9 kΩ R10 3.9 kΩ R11 27 Ω R12 12 kΩ R13 22 kΩ R14 2.2 kΩ 2000 Mar 16 VALUE 1. Wire size is 0.4 mm. Table 17 Transformer (note 1) COMPONENT L4 VALUE 2 x 5 turns Note 1. Coil type: TOKO 7kN; material: 113 kN; screw core: 03-0093; pot core: 04-0026. Table 18 Crystal COMPONENT Y1 29 VALUE 4 MHz Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners Table 19 Transistors 13.5 COMPONENT VALUE TR1 BC847B TR2 BC847B TDA6502; TDA6502A; TDA6503; TDA6503A Examples of I2C-bus data format sequences for TDA6502 and TDA6503 Tables 20 to 24 show the various write sequences where: S = START bit A = acknowledge bit 13.3 Tuning amplifier P = STOP bit. The tuning amplifier is capable of driving the varicap voltage without an external transistor. The tuning voltage output must be connected to an external load of 27 kΩ which is connected to the tuning voltage supply rail. The loop filter design depends on the oscillator characteristics and the selected reference frequency. 13.4 Conditions: fxtal = 4 MHz N = 1600 fosc = 100 MHz fstep = 62.5 kHz Port register VHFL is ‘on’ to switch-on band VHF low Crystal oscillator Port register FMST is ‘on’ to switch-on an FM sound trap The crystal oscillator uses a 4 MHz crystal connected in series with an 18 pF capacitor thereby operating in the series resonance mode. Connecting the crystal to the ground is preferred, but it can also be connected to the supply voltage. 13.5.1 ICP = 280 µA. WRITE SEQUENCES TO REGISTER C2 Table 20 Complete sequence with first the divider bytes (first data bit = 0) START ADDRESS ACK BYTE S C2 DIVIDER BYTE 1 ACK DIVIDER BYTE 2 ACK 06 A 40 A A BANDSWITCH BYTE CONTROL ACK BYTE CE A 09 ACK STOP A P Table 21 Complete sequence with first the control and band-switch bytes (first data bit = 1) START ADDRESS CONTROL ACK ACK BYTE BYTE S C2 A CE A BANDSWITCH BYTE ACK DIVIDER BYTE 1 ACK DIVIDER BYTE 2 09 A 06 A 40 ACK STOP A P Table 22 Sequence with divider bytes only (first data bit = 0) START ADDRESS BYTE ACK DIVIDER BYTE 1 ACK DIVIDER BYTE 2 S C2 A 06 A 40 ACK STOP A P Table 23 Sequence with control and band-switch bytes only (first data bit = 1) START ADDRESS BYTE ACK CONTROL BYTE ACK BAND-SWITCH BYTE S C2 A CE A 09 ACK STOP A P Table 24 Sequence with control byte only (first data bit = 1) START ADDRESS BYTE ACK CONTROL BYTE S C2 A CE 2000 Mar 16 30 ACK STOP A P Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 13.5.2 TDA6502; TDA6502A; TDA6503; TDA6503A READ SEQUENCES FROM REGISTER C3 Tables 25 and 26 show the various read sequences where: S = START bit A = acknowledge bit XX = read status byte X = no acknowledge from the master means end of sequence P = STOP bit Table 25 One status byte acquisition START ADDRESS BYTE ACK STATUS BYTE S C3 A XX ACK STOP X P Table 26 Two status bytes acquisition START ADDRESS BYTE ACK STATUS BYTE ACK STATUS BYTE S C3 A XX A XX 13.6 13.6.1 ACK STOP X P Examples of 3-wire bus data format sequences for TDA6502 and TDA6503 18-BIT SEQUENCE Conditions: fosc = 800 MHz Port register PUHF is ‘on’. Table 27 18-bit sequence PUHF FMST PVHFH PVHFL 1 0 0 0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 The reference divider is automatically set to 64 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB has been set to logic 0, in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 18-bit sequence has to be adapted to the 80 divider ratio. 13.6.2 19-BIT SEQUENCE Conditions: fosc = 650 MHz Port register PUHF is ‘on’. Table 28 19-bit sequence PUHF FMST PVHFH PVHFL N14 1 0 0 0 1 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 The reference divider is automatically set to 128 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB has been set to logic 0 in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 19-bit sequence has to be adapted to the 80 divider ratio. 2000 Mar 16 31 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 13.6.3 TDA6502; TDA6502A; TDA6503; TDA6503A 27-BIT SEQUENCE Conditions: fosc = 750 MHz Port register PUHF is ‘on’ Reference divider is set at 80 ICP = 60 µA No test function. Table 29 27-bit sequence FREQUENCY DATA BITS CONTROL DATA BITS PORT BITS 1 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X CP T2 T1 T0 RSA RSB OS 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 To change the oscillator frequency to 600 MHz in 50 kHz steps a 19-bit sequence or an 18-bit sequence can be used. The charge pump current remains at 60 µA. Table 30 Changing frequency with a 19-bit sequence FREQUENCY DATA BITS PORT BITS 1 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 Table 31 Changing frequency with an 18-bit sequence FREQUENCY DATA BITS PORT BITS 1 0 2000 Mar 16 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 32 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 14 INTERNAL PIN CONFIGURATION DC VOLTAGE (AVERAGE VALUE)(2) PIN SYMBOL TDA6502; TDA6502A TDA6503; TDA6503A VHF UHF UHFIN1 1 28 − 1.0 V UHFIN2 2 27 − 1.0 V EQUIVALENT CIRCUIT(1) 1 2 (28) (27) FCE584 VHFIN 3 26 − − 3 (26) FCE585 RFGND 4 25 0.0 V 0.0 V 4 (25) FCE586 IFFIL1 5 24 3.6 V 3.6 V IFFIL2 6 23 3.6 V 3.6 V (24) 5 6 (23) FCE587 PVHFL 7 22 n.a. or 4.8 V n.a. PVHFH 8 21 4.8 V or n.a. n.a. n.a. 4.8 V PUHF 9 20 FMST 10 19 n.a. or 4.8 V n.a. or 4.8 V 7 8 (22) (21) 9 10 (20) (19) FCE588 2000 Mar 16 33 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A DC VOLTAGE (AVERAGE VALUE)(2) PIN SYMBOL SW TDA6502; TDA6502A TDA6503; TDA6503A VHF UHF 11 18 5.0 V 5.0 V EQUIVALENT CIRCUIT(1) 11 (18) FCE189 CE/AS 12 17 1.25 V 1.25 V 12 (17) FCE191 DA 13 16 − − 13 (16) FCE190 CL 14 15 − − 14 (15) FCE192 LOCK/ADC 15 14 4.6 V 4.6 V 15 (14) FCE193 2000 Mar 16 34 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners DC VOLTAGE (AVERAGE VALUE)(2) PIN SYMBOL CP TDA6502; TDA6502A TDA6503; TDA6503A VHF UHF 16 13 1V 1V TDA6502; TDA6502A; TDA6503; TDA6503A EQUIVALENT CIRCUIT(1) 16 (13) FCE194 VT 17 12 VVT VVT 17 (12) FCE589 XTAL 18 11 2.6 V 2.6 V 18 (11) FCE590 VCC 19 10 5.0 V 5.0 V IFOUT 20 9 2.1 V 2.1 V supply voltage 20 (9) FCE591 GND 21 8 0.0 V 0.0 V 21 (8) FCE592 2000 Mar 16 35 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A DC VOLTAGE (AVERAGE VALUE)(2) PIN SYMBOL OSCGND TDA6502; TDA6502A TDA6503; TDA6503A VHF UHF 23 6 0.0 V 0.0 V EQUIVALENT CIRCUIT(1) 23 (6) FCE593 VHFOSCIB 22 7 1.8 V − VHFOSCOC 24 5 3.0 V − 24 (5) 22 (7) FCE594 UHFOSCIB1 25 4 − 1.9 V UHFOSCOC1 26 3 − 2.9 V UHFOSCOC2 27 2 − 2.9 V UHFOSCIB2 28 1 − 1.9 V (2) (3) 27 26 25 28 (4) (1) FCE595 Notes 1. The pin numbers in parenthesis represent the TDA6503 and TDA6503A. 2. Measured in circuit of Fig.19. 2000 Mar 16 36 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 15 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 2000 Mar 16 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-150 37 o Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners If wave soldering is used the following conditions must be observed for optimal results: 16 SOLDERING 16.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 16.2 TDA6502; TDA6502A; TDA6503; TDA6503A – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.3 16.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2000 Mar 16 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 38 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners 16.5 TDA6502; TDA6502A; TDA6503; TDA6503A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Mar 16 39 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A 17 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Mar 16 40 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners NOTES 2000 Mar 16 41 TDA6502; TDA6502A; TDA6503; TDA6503A Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners NOTES 2000 Mar 16 42 TDA6502; TDA6502A; TDA6503; TDA6503A Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners NOTES 2000 Mar 16 43 TDA6502; TDA6502A; TDA6503; TDA6503A Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/02/pp44 Date of release: 2000 Mar 16 Document order number: 9397 750 06924