TDA8757 Triple 8-bit ADC 170 Msps Rev. 07 — 28 February 2002 Preliminary data 1. General description The TDA8757 is a triple 8-bit ADC for the digitizing of large bandwidth RGB/YUV signals at a sampling rate up to 170 Msps. The IC supports display resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The IC also includes a PLL that can be locked to the horizontal line frequency and generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics applications. An external clock signal can also be used to clock the ADC. The outputs are available either on one port up to 110 Msps or on two ports up to 170 Msps. The operating mode is selectable with the serial interface to for either I2C-bus or 3-wire serial bus (3W-bus) operation. The clamp level, the gain and the other settings are controllable through the serial interface. 2. Features ■ Triple 8-bit ADC ■ Sampling rate up to 170 Msps ■ IC controllable by a serial interface which can be I2C-bus or 3W-bus, selected by a TTL input pin ■ Three clamps for programming a clamping code from −63.5 to +64 in steps of 1⁄ LSB (RGB) and from +120 to +136 in steps of 1⁄ LSB (YUV) 2 2 ■ Three controllable amplifiers: gain controlled by the serial interface to produce a full-scale resolution of 1⁄2 LSB peak-to-peak ■ Amplifier bandwidth of 250 MHz ■ Low gain variation with temperature ■ PLL controllable through the serial interface to generate the ADC clock which can be locked to any line frequency of 15 to 150 kHz ■ Integrated PLL divider ■ Programmable phase clock adjustment cells ■ Internal voltage regulators ■ TTL compatible digital inputs and outputs ■ Outputs on one port or demultiplexed on two ports; selectable with the serial interface ■ Chip enable, high-impedance ADC output ■ Power-down mode ■ 1.5 W power dissipation ■ Sync on green extractor. TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 3. Applications ■ ■ ■ ■ RGB/YUV high-speed digitizing LCD panels drive LCD projection systems VGA to UXGA (1600 × 1200 at 60 Hz) modes. 4. Quick reference data Table 1: Quick reference data Symbol Parameter VCCA Conditions Min Typ Max Unit analog supply voltage for PLL and the RGB channels 4.75 5.0 5.25 V VDDD logic supply voltage for I2C-bus and 3W-bus 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage for PLL and the RGB channels 4.75 5.0 5.25 V VCCA(PLL) analog PLL supply voltage 4.75 5.0 5.25 V VCCO(PLL) output PLL supply voltage 4.75 5.0 5.25 V ICCA analog supply current for the RGB channels − 135 − mA IDDD logic supply current for I2C-bus and 3W-bus − 1 − mA ICCD digital supply current − 95 − mA ICCO output stages supply current − 80 − mA ICCA(PLL) analog PLL supply current − 34 − mA fclk clock frequency normal (Dmx = 0) − − 110 MHz de-multiplexed (Dmx = 1) − − 170 MHz fref(PLL) PLL reference clock frequency 15 − 150 kHz fPLL output clock frequency range 10 − 170 MHz INL DC integral non-linearity from analog input to digital output; full-scale; sinusoidal input; fclk = 170 MHz − ±0.5 ±1.5 LSB DNL DC differential non-linearity from analog input to digital output; full-scale; sinusoidal input; fclk = 170 MHz − ±0.4 ±1 LSB ∆Gamp/∆T amplifier gain stability variation Vref = 2.5 V with with temperature 100 ppm/°C maximum − 325 − ppm/°C B amplifier bandwidth −3 dB; Tamb = 25 °C 250 − − MHz tset(ADC+AGC) settling time of the block ADC + AGC input signal settling time <1 ns; settling to 1%; fi = 85 MHz − 4 − ns © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 2 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 1: Quick reference data…continued Symbol Parameter DRPLL PLL divider ratio Conditions Ptot total power dissipation jPLL(max)(p-p) maximum PLL phase jitter (peak-to-peak value) Min Typ Max 100 − 4095 Unit fclk = 170 MHz; sinusoidal input − 1.5 − W fclk = 170 MHz − 360 − ps 5. Ordering information Table 2: Ordering information Type number TDA8757HL Package Name Description Version HLQFP144 plastic, heatsink low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT612-1 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 3 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 6. Block diagram CLP AGCR GAINCR INR DECR 5 7 11 CLPR 131 8 6 CLAMP 8 114 to 121 9 MUX OUTPUT ADC 8 100 to 107 113 VREF AGCG GAINCG ING DECG AGCB GAINCB INB DECB 3 RED CHANNEL 15 129 18 17 16 21 GREEN CHANNEL 19 8 92 to 99 8 79 to 86 91 26 29 28 27 32 BLUE CHANNEL 30 8 71 to 78 8 58 to 65 70 BOTR A0R to A7R B0R to B7R ORR OE CLPG BOTG A0G to A7G B0G to B7G ORG CLPB BOTB A0B to A7B B0B to B7B ORB HSYNCI INSOG SOGO A1 A2 SEN SCL SDA DIS I2C/3W 23 24 38 39 43 47 44 42 37 CKADC SYNCHRO EXTRACTOR SERIAL INTERFACE I2C- BUS or 3W-BUS I2C-bus TDA8757 123 124 REGULATOR 134 133 135 136 1-bit (Hlevel) PLL 132 4 2 130 141 CKDATA CKREFO CKEXT INV COAST CKREF 140 FCE694 HSYNC DEC1 DEC2 PD CZ CP Fig 1. Block diagram. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 4 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps CLP OE AGCα CKDMX CLPα CLAMP CONTROL DAC VP CKADC 150 kΩ INα MUX AGC I2C-bus: 8 bits 8 OUTPUTS A (Oα) & REGISTER OUTPUTS B 8 8 ADC D B0α to B7α ORα VREF DAC A0α to A7α I2C-bus: 3 bits (Dmx, Odda, Shift, Blk) 8 D R R 5 8 1 I2C-bus: REGISTER FINE GAIN ADJUST 5 bits (Fα) 1 BOTα 7 REGISTER COARSE GAIN ADJUST I2C-bus: 7 bits (Cα) SERIAL I2C-BUS FCE695 GAINCα SDA HSYNC SCL Fig 2. Channel diagram (where α stands for R, G or B). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 5 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps CZ CP COAST I2C-bus: 1 bit +/− (Vlevel) CKEXT Z I2C-bus: 3 bits (Z) CKADC I2C-bus: 5 bits (P) CKREF I2C-bus: 1 bit (Edge) PHASE FREQUENCY DETECTOR I2C-bus: 5 bits (Ip, Up, Do) INV VCO 0/180 MUX PHASE I2C-bus: 1 bit (Ckext) I2C-bus: 2 bits (Vco) CKDMX I2C-bus: 1 bit (Odda) MUX ÷2 DIV N (100 to 4095) τ +/− CKDATA I2C-bus: 2 bits (Ckdd, Ckdp) I2C-bus: 1 bit (Dmx) I2C-bus: 12 bits (Di) MUX SYNCHRO +/− CKREFO I2C-bus: 1 bit I2C-bus: 1 bit (Ckrs) (Ckrp) MBL365 OE (1) (1) Enable of CKDATA and CKREFO by OE. Available in C3 version only. Fig 3. PLL diagram. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 6 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 7. Pinning information 109 OGNDR 110 VCCO(R) 112 VCCO(R) 111 OGNDR 113 ORR 115 A1R 114 A0R 116 A2R 118 A4R 117 A3R 119 A5R 121 A7R 120 A6R 122 OGNDPLL 123 CKDATA 124 CKREFO 125 TESTO 127 n.c. 126 VCCO(PLL) 128 DGND1 129 OE 130 PD 131 CLP 132 HSYNC 133 INV 134 CKEXT 135 COAST 136 CKREF 137 VCCD1 139 AGNDPLL 138 n.c. 140 CP 141 CZ 142 AGNDPLL 143 VCCA(PLL) 144 n.c. 7.1 Pinning n.c. 1 108 n.c. DEC2 2 VREF 3 107 B7R 106 B6R DEC1 4 105 B5R AGCR 5 BOTR 6 104 B4R 103 B3R GAINCR 7 102 B2R CLPR 8 DECR 9 101 B1R 100 B0R VCCA(R) 10 99 A7G INR 11 98 A6G n.c. 12 AGNDR 13 97 A5G 96 A4G n.c. 14 95 A3G AGCG 15 BOTG 16 94 A2G 93 A1G GAINCG 17 CLPG 18 DECG VCCA(G) 19 20 90 VCCO(G) 89 OGNDG ING AGNDG 21 88 VCCO(G) 22 87 OGNDG INSOG 23 86 B7G SOGO 24 n.c. 25 85 B6G 84 B5G AGCB 26 83 B4G BOTB 27 GAINCB 28 82 B3G 81 B2G CLPB DECB 29 80 B1G 30 VCCA(B) 31 79 B0G 78 A7B INB AGNDB 32 77 A6B 33 n.c. 34 76 A5B 75 A4B n.c. 35 74 A3B n.c. 36 73 A2B 92 A0G 91 ORG A1B 72 A0B 71 ORB 70 VCCO(B) 69 B7B 65 OGNDB 66 VCCO(B) 67 OGNDB 68 B6B 64 B5B 63 B4B 62 B3B 61 B2B 60 B1B 59 B0B 58 n.c. 57 VSSD2 55 VSSD3 56 n.c. 54 DGND2 53 VCCD2 52 n.c. 51 n.c. 50 n.c. 49 n.c. 48 SCL 47 SDA 44 VDDD 45 VSSD1 46 SEN 43 DIS 42 TDO 41 TCK 40 A2 39 A1 38 I2C/3W 37 TDA8757HL GNDDP FCE697 Fig 4. Pin configuration. 7.2 Pin description Table 3: Pin description Symbol Pin Description n.c. 1 not connected DEC2 2 main regulator decoupling input 2 VREF 3 gain stabilizer voltage reference input DEC1 4 main regulator decoupling input 1 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 7 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 3: Pin description…continued Symbol Pin Description AGCR 5 red channel AGC output BOTR 6 red channel ladder decoupling input (BOT) GAINCR 7 red channel gain capacitor input CLPR 8 red channel clamp capacitor input DECR 9 red channel regulator decoupling input VCCA(R) 10 red channel analog supply voltage INR 11 red channel analog input n.c. 12 not connected AGNDR 13 red channel gain analog ground n.c. 14 not connected AGCG 15 green channel AGC output BOTG 16 green channel ladder decoupling input (BOT) GAINCG 17 green channel gain capacitor input CLPG 18 green channel clamp capacitor input DECG 19 green channel regulator decoupling input VCCA(G) 20 green channel analog supply voltage ING 21 green channel analog input AGNDG 22 green channel gain analog ground INSOG 23 sync on green channel input SOGO 24 composite sync output n.c. 25 not connected AGCB 26 blue channel AGC output BOTB 27 blue channel ladder decoupling input (BOT) GAINCB 28 blue channel gain capacitor input CLPB 29 blue channel clamp capacitor input DECB 30 blue channel regulator decoupling input VCCA(B) 31 blue channel analog supply voltage INB 32 blue channel analog input AGNDB 33 blue channel gain analog ground n.c. 34 not connected n.c. 35 not connected n.c. 36 not connected I2C/3W 37 selection input between I2C-bus (active HIGH) and 3W-bus (active LOW) A1 38 I2C-bus address control input 1 A2 39 I2C-bus address control input 2 TCK 40 scan test mode input (active HIGH) TDO 41 scan test output DIS 42 I2C-bus and 3W-bus disable control input (disable at HIGH level) SEN 43 select enable input for 3W-bus © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 8 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 3: Pin description…continued Symbol Pin Description SDA 44 I2C-bus/3W-bus serial data input VDDD 45 logic I2C-bus/3W-bus digital supply voltage VSSD1 46 logic I2C-bus/3W-bus digital ground 1 SCL 47 I2C-bus/3W-bus serial clock input n.c. 48 not connected n.c. 49 not connected n.c. 50 not connected n.c. 51 not connected VCCD2 52 digital supply voltage 2 DGND2 53 digital ground 2 n.c. 54 not connected VSSD2 55 logic I2C-bus/3W-bus digital ground 2 VSSD3 56 logic I2C-bus/3W-bus digital ground 3 n.c. 57 not connected B0B 58 blue channel ADC output B bit 0 (LSB) B1B 59 blue channel ADC output B bit 1 B2B 60 blue channel ADC output B bit 2 B3B 61 blue channel ADC output B bit 3 B4B 62 blue channel ADC output B bit 4 B5B 63 blue channel ADC output B bit 5 B6B 64 blue channel ADC output B bit 6 B7B 65 blue channel ADC output B bit 7 (MSB) OGNDB 66 blue channel ADC output B ground VCCO(B) 67 blue channel ADC output B supply voltage OGNDB 68 blue channel ADC output A ground VCCO(B) 69 blue channel ADC output A supply voltage ORB 70 blue channel ADC output bit out of range A0B 71 blue channel ADC output A bit 0 (LSB) A1B 72 blue channel ADC output A bit 1 A2B 73 blue channel ADC output A bit 2 A3B 74 blue channel ADC output A bit 3 A4B 75 blue channel ADC output A bit 4 A5B 76 blue channel ADC output A bit 5 A6B 77 blue channel ADC output A bit 6 A7B 78 blue channel ADC output A bit 7 (MSB) B0G 79 green channel ADC output B bit 0 (LSB) B1G 80 green channel ADC output B bit 1 B2G 81 green channel ADC output B bit 2 B3G 82 green channel ADC output B bit 3 B4G 83 green channel ADC output B bit 4 B5G 84 green channel ADC output B bit 5 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 9 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 3: Pin description…continued Symbol Pin Description B6G 85 green channel ADC output B bit 6 B7G 86 green channel ADC output B bit 7 (MSB) OGNDG 87 green channel ADC output B ground VCCO(G) 88 green channel ADC output B supply voltage OGNDG 89 green channel ADC output A ground VCCO(G) 90 green channel ADC output A supply voltage ORG 91 green channel ADC output bit out of range A0G 92 green channel ADC output A bit 0 (LSB) A1G 93 green channel ADC output A bit 1 A2G 94 green channel ADC output A bit 2 A3G 95 green channel ADC output A bit 3 A4G 96 green channel ADC output A bit 4 A5G 97 green channel ADC output A bit 5 A6G 98 green channel ADC output A bit 6 A7G 99 green channel ADC output A bit 7 (MSB) B0R 100 red channel ADC output B bit 0 (LSB) B1R 101 red channel ADC output B bit 1 B2R 102 red channel ADC output B bit 2 B3R 103 red channel ADC output B bit 3 B4R 104 red channel ADC output B bit 4 B5R 105 red channel ADC output B bit 5 B6R 106 red channel ADC output B bit 6 B7R 107 red channel ADC output B bit 7 (MSB) n.c. 108 not connected OGNDR 109 red channel ADC output B ground VCCO(R) 110 red channel ADC output B supply voltage OGNDR 111 red channel ADC output A ground VCCO(R) 112 red channel ADC output A supply voltage ORR 113 red channel ADC output A bit out of range A0R 114 red channel ADC output A bit 0 (LSB) A1R 115 red channel ADC output A bit 1 A2R 116 red channel ADC output A bit 2 A3R 117 red channel ADC output A bit 3 A4R 118 red channel ADC output A bit 4 A5R 119 red channel ADC output A bit 5 A6R 120 red channel ADC output A bit 6 A7R 121 red channel ADC output A bit 7 (MSB) OGNDPLL 122 PLL digital ground CKDATA 123 output data clock CKREFO 124 output horizontal pulse synchronized to pixel clock TESTO 125 output reserved for test © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 10 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 3: Pin description…continued Symbol Pin Description VCCO(PLL) 126 PLL output supply voltage n.c. 127 not connected DGND1 128 digital ground 1 OE 129 output enable; active LOW (when OE is HIGH, the outputs are high-impedance) PD 130 power-down control input (IC is in Power-down mode when this pin is HIGH) CLP 131 clamp pulse input (clamp active HIGH) HSYNC 132 horizontal synchronization pulse input INV 133 PLL clock output inverter control input (invert when HIGH) CKEXT 134 external clock input COAST 135 PLL coast control input CKREF 136 PLL reference clock input VCCD1 137 digital supply voltage 1 n.c. 138 not connected AGNDPLL 139 PLL analog ground CP 140 PLL filter input CZ 141 PLL filter input AGNDPLL 142 PLL analog ground VCCA(PLL) 143 PLL analog supply voltage n.c. 144 not connected GNDDP exposed die pad connection 8. Functional description This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals, coming from an analog source, into digital data used by a LCD driver (pixel clock up to 170 MHz). 8.1 Analog video inputs The RGB/YUV video inputs are externally AC coupled and are internally DC polarized. The synchronization signals are also used for the internal PLL and the gain calibration. If the green video signal has composite sync (sync on green), it is possible to extract this composite sync by connecting the green signal to pin INSOG (AC coupled). When the sync pulse amplitude is below 300 mV, the I2C-bus bit ‘Slevel’ has to be set to logic 1 (see Figure 5). The maximum amplitude for the sync pulse is 600 mV. The composite sync is available at pin SOGO (TTL level compatible signal). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 11 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps blank level 300 mV to 600 mV 150 mV comparison level set by I2C-bus bit Slevel = 0 blank level 150 mV to 300 mV 80 mV comparison level set by I2C-bus bit Slevel = 1 005aaa009 Fig 5. Sync level diagram. If this function is not used, pin INSOG should be connected to the analog power supply. In this event, pin SOGO is at LOW-level TTL. 8.2 Clamps Three independent parallel clamping circuits are used to clamp the video input signals on several black levels. The clamping levels may be set from −63.5 to +64 LSBs (RGB) and from +120 to +136 LSBs in steps of 1⁄2 LSB (YUV). They are controlled by changing the values in three 8-bit registers: OFFSETR, OFFSETG and OFFSETB (see Table 5). Each clamp must be able to correct an offset from ±100 mV to ±10 mV within 300 ns, and correct the total offset in 10 lines. The clamping is done using the following principle: On the incoming of a TTL positive going pulse supplied on pin CLP, three external capacitors are loaded independently by the device in order to change the voltage level of each analog RGB input. The capacitors are connected to pins CLPR, CLPG and CLPB. video signal ADC Clamp = +128 clamp programming 255 constant level Clamp = +64 0 constant level Clamp =0 Clamp = −63.5 CLP FCE698 Fig 6. Clamp definition. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 12 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 8.2.1 Variable gain amplifiers Three independent variable gain amplifiers are used to provide a full-scale input signal to the 8-bit ADC for each channel. The gain adjustment range is designed so that for an input range varying from 0.4 to 1.2 V (p-p), the output signal corresponds to the ADC full-scale input of 1 V (p-p). To ensure that the gain does not vary over the whole operating temperature range, a reference voltage Vref = 2.5 V (DC) with a maximum variation of 100 ppm/°C, is supplied externally on pin VREF. The calibration of the gains is done using the following principle: On the incoming of a pulse supplied to pin HSYNC, an internal multiplexer switches from the RGB video signals to a reference voltage (1⁄16Vref). The ADCs inputs become this reference signal and the three corresponding outputs are compared to pre-set values loaded in three 7-bit registers: COARSER, COARSEG and COARSEB. Depending on the result of the comparisons, the three gains are adjusted such that the ADC outputs become equal to the pre-set values in the registers. The three gains are simply controlled by changing the values in the COARSE registers. The signal supplied on pin HSYNC, may be selected active HIGH or active LOW. The choice is done through the serial interface by setting bit ‘Hlevel’ in the control register (active HIGH when bit Hlevel = 0). This active part of the signal has to occur during the blanking period of the signal in order not to interrupt the active video. Normally the horizontal synchronization signal, provided by the video source, is connected to pin HSYNC. The values loaded in the gain registers (COARSER, COARSEG, COARSEB) are chosen among 68 values (see Table 6). A fine correction is also used to finely tune the gain on the three channels and to compensate the channel-to-channel gain mismatch. The fine correction is done using the following principle: the three binary codes, stored in the three 5-bit registers (FINER, FINEG and FINEB) are converted into three analog voltages (with three DACs) and are independently added to the reference voltage (1⁄16Vref). Thus, three different reference voltages are used for the gain calibration of the three channels. When the COARSE registers are set at full-scale, the resolution of the fine registers corresponds to 1⁄2 LSB peak-to-peak (see Equation 3). 8.2.2 Important recommendations The clamping and the gain calibration requires two external signals (pulses). One signal is connected to pin CLP and the other is connected to pin HSYNC. It is very important that: • The active part of these two signals occur during the blanking of the video signal, in order not to interrupt or disturb the active video. • The active part of these two signals does not overlap on each other, in order to perform correctly the gain calibration and the clamping. Normally the clamp pulse is sent after the end of the horizontal synchronization pulse. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 13 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 8.2.3 ADCs Three ADCs convert analog signals into three series of 8-bit codes, with a maximum clock frequency of 170 Msps. The ADCs input range is 1 V (p-p) full-scale and the pipeline delay is 1 clock cycle from the sampling to the data output. The reference ladder regulators are integrated. 8.2.4 Data outputs ADC outputs are straight binary. Pin OE switches the output status between active and high-impedance (OE = HIGH). It is possible to force the outputs with a maximum 10 pF capacitive load. The timing must be checked very carefully if the capacitive loads are more than 10 pF. It is possible to force the outputs to logic 0 during the gain calibration (during HSYNC pulse) and during the clamping (CLP pulse). This mode is activated through the serial interface by setting bit ‘Blk’ to logic 1 in register DEMUX. The TDA8757 provides outputs either on one port (port A) or on two ports (ports A and B). The selection is made with the serial interface by setting bit ‘Dmx’ to logic 0 or logic 1 in register DEMUX. When just one port is used (Dmx = 0), the unused ports are forced to LOW level. When two ports are used (Dmx = 1), it is possible to select the port that would provide the odd pixel by setting bit ‘Odda’ to logic 1 or logic 0 in register DEMUX; when this bit is logic 1, the odd pixel is output on port A. One out-of-range bit exists per channel (ORR, ORG and ORB). It will be at logic 1 when the signal is out-of-range of the ADC voltage ladder. Finally, two configurations are possible: either the port A outputs and the port B outputs are both synchronous or they are interleaved. The selection is done by setting bit ‘Shift’ to logic 0 or logic 1 in register DEMUX. CKREF CKADC CKREFO XXX OUT A XXX ODD EVEN FCE708 Fig 7. Definition of odd and even pixels; Edge = 0, Dmx = 0 and Ckrp = 1. 8.2.5 PLL The ADCs are clocked by either the internal PLL locked to the reference clock CKREF or an external clock connected to pin CKEXT. All parts of the PLL are on-chip except the loop filter capacitance. The selection is performed via the serial interface by setting bit ‘Ckext’ in register PHASE (Ckext = 1 when the external clock is used). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 14 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps The reference clock (CKREF) range is between 15 and 150 kHz. Consequently, the VCO minimum frequency is 12 MHz and the maximum frequency is 170 MHz. The gain of the VCO part can be controlled through the serial interface, depending on the frequency range to which the PLL is locked. Moreover, the PLL may be locked either on the rising or on the falling edge of the CKREF signal pulses. This choice is made through the serial interface by setting bit ‘Edge’ in register CONTROL (rising edge when bit ‘Edge’ = 0). The charge pump current (Icp) enables an increase of PLL bandwidth. It is programmable through the serial interface by setting bits ‘Ip2’, ‘Ip1’ and ‘Ip0’ in the control register (see Table 8). Different resistance values (R) for the filter can also be programmed through the serial interface by setting the bits ‘Z2’, ‘Z1’ and ‘Z0’ in register VCO (see Table 9). To have optimal PLL performance, R and Icp must be chosen so that: • The result of the product ‘R × Icp’ is smaller than a determined limit (Lim) • The result of the product ‘R × Icp’ is as close as possible to this limit (Lim). 0.3π × DR PLL × f ref Lim = -------------------------------------------------K0 (1) where: • DRPLL = the divider ratio, which is the ratio between the pixel frequency and the horizontal line frequency of the incoming signal. The setting of this parameter is performed through the serial interface with bits Di0 to Di11. These bits are present in the VCO-, divider- and phase registers. • fref = the frequency of the signal. • K0 = the VCO gain, which depends on the pixel frequency ranges given in Table 10. In the event that several combinations of R and Icp give the same result, a calculation of the damping factor (ξ) for each combination becomes necessary. The combination of R and Icp whose damping factor is the closest to 1.5, generates the optimal PLL performance. K 0 ⋅ I cp R ⋅ CZ ξ = --------------- ⋅ ----------------------------------------------DR PLL ⋅ ( C Z + C P ) 2 (2) where CZ and CP are the external capacitors of the PLL loop filter. The recommended values are: CZ = 68 nF and CP = 150 pF. The COAST signal is used to disconnect the PLL phase frequency detector during the frame flyback (vertical blanking) or during the unavailability of the CKREF signal. This signal can normally be derived from the VSYNC signal. COAST may be set either active HIGH or active LOW by setting bit ‘Vlevel’ in the control register through the serial interface (Vlevel = 0 when HIGH). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 15 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps It is possible to control the phase of the ADC clock (CKADC) through the serial interface with the included digital phase-shift controller. The phase register (5 bits) enables the phase to shift by steps of 11.25 °. The CKREF signal is re-synchronized by the synchro-block on the CKADC clock. The new reference is available on pin CKREFO. This synchronization may be done with the CKREF signal directly, or with the output of the divider in the PLL (see Figure 3). The selection is done via the serial interface by setting bit ‘Ckrs’ in the phase register (Ckrs = 1 when the CKREF signal is used). The polarity of the signal on pin CKREFO is controlled through the serial interface by setting bit ‘Ckrp’ in register DEMUX (positive polarity if Ckrp = 0). The width of this signal is fixed to 8 clock cycles. The PLL also provides a CKDATA clock. This clock is synchronized on the data outputs whatever the output mode. It is possible to delay the CKDATA clock with a constant time (τ = 3 ns, compared to the outputs) by setting bit ‘Ckdd’ to logic 1 in register DEMUX. It is also possible to reverse the CKDATA clock, referenced to the outputs, by setting bit ‘Ckdp’ in register DEMUX. The maximum capacitive load for each clock output is 10 pF, and pin OE switches the output status between active and high impedance (OE = HIGH). If an external clock is used, it has to be connected to pin CKEXT. Bit ‘Ckext’ and bit ‘Ckrs’ in the phase register have to be set at logic 1, and it is also important to disconnect the internal PLL by using the following settings: • Set bit ‘Do’ in the control register to logic 1. • Set bits ‘Vco1’ and ‘Vco0’ in register VCO to logic 0. CKREF tCKAO CKADC tCKREFO CKREFO Ckrp = 0 8 clock periods CKREFO Ckrp = 1 FCE699 Fig 8. Timing diagram; CKREFO; Dmx = 0. There is a delay between the input signal on pin CKREF and the corresponding output on pin CKREFO; see Figure 8. This delay is tCKREFO: tCKREFO = either tCKAO (if clock phase >01000) or tCKAO + TCLK(pixel) (if phase <01000) tCKAO = tCLK(buffer) + tphase selector phase tCLK(buffer) = tbf and tphase selector = --------------- ⋅ T CLK ( pixel ) 2π © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 16 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 9. I2C-bus and 3W-bus interfaces 9.1 Register definitions The configuration of the registers is given in Table 4. Table 4: I2C-bus and 3W-bus registers Function name Subaddress Bit definition A7 A6 A5 A4 A3 A2 A1 A0 MSB SUBADDR LSB Default value X X X Mode Sa3 Sa2 Sa1 Sa0 XXX1 0000 OFFSETR X X X X 0 0 0 0 Or7 Or6 Or5 Or4 Or3 Or2 Or1 Or0 0111 1111 COARSER X X X X 0 0 0 1 Or8 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 0010 0000 FINER X X X X 0 0 1 0 X X X Fr4 Fr3 Fr2 Fr1 Fr0 XXX0 0000 OFFSETG X X X X 0 0 1 1 Og7 Og6 Og5 Og4 Og3 Og2 Og1 Og0 0111 1111 COARSEG X X X X 0 1 0 0 Og8 Cg6 Cg5 Cg4 Cg3 Cg2 Cg1 Cg0 0010 0000 FINEG X X X X 0 1 0 1 X X Slevel Fg4 Fg3 Fg2 Fg1 Fg0 XXX0 0000 OFFSETB X X X X 0 1 1 0 Ob7 Ob6 Ob5 Ob4 Ob3 Ob2 Ob1 Ob0 0111 1111 COARSEB X X X X 0 1 1 1 Ob8 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 0010 0000 FINEB X X X X 1 0 0 0 X X X Fb4 Fb3 Fb2 Fb1 Fb0 XXX0 0000 CONTROL X X X X 1 0 0 1 Vlevel Hlevel Edge Up Do Ip2 Ip1 Ip0 0000 0111 VCO X X X X 1 0 1 0 Z2 Z1 Z0 Vco1 Vco0 Di11 Di10 Di9 1011 1011 DIVIDER (LSB) X X X X 1 0 1 1 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 0100 1100 PHASE X X X X 1 1 0 0 Di0 Ckrs Ckext P4 P3 P2 P1 P0 DEMUX X X X X 1 1 0 1 Blk Cken Ckrp Ckdp Ckdd Shift Odda Dmx 9.1.1 0000 0000 1000 0111 Subaddress All the registers are defined by a subaddress of 7 bits: bit Mode refers to the mode which is used with the I2C-bus interface, bits ‘Sa3’ to ‘Sa0’ give the subaddress of each register. Bit Mode, used only with the I2C-bus, allows two modes for the programming: Mode 0 Each register is programmed independently, by giving its subaddress and its content. Mode 1 All the registers are programmed one after the other, by giving this initial condition (XXX1 1111) as the subaddress state; thus, the registers are changed following the predefined sequence of 16 bytes (from subaddress 0000 to 1101). The default values correspond to a VESA 1280 × 1024 at 75 Hz graphic mode. 9.1.2 Offset register This register controls the clamp level for the RGB channels. The relationship between the programming code and the level of the clamp code is given in Table 5. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 17 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 5: Coding Programmed code Clamp code ADC output 0 −63.5 1 −63 2 −62.5 ... ... 127 0 0 ... ... ... 254 63.5 63 or 64 255 64 64 256 120 120 ... ... ... 287 136 136 underflow The default programmed value is: • Programmed code = 127 • Clamp code = 0 • ADC output = 0. 9.1.3 Coarse and Fine registers These two registers enable the gain control: the AGC gain with the coarse register, and the reference voltage with the fine register. The coarse register programming equation is as follows: N COARSE + 1 N COARSE + 1 1 GAIN = ------------------------------------------------ × ------ = ------------------------------------------------ × 32 16 V N FINE ref . ( 512 – N FINE ) - V ref ⋅ 1 – ----------------32 × 16 (3) Where: Vref = 2.5 V. The gain correspondence is given in Table 6. The gain is linear with reference to the programming code (NFINE = 0). Table 6: Typical gain correspondence (COARSE) NCOARSE Gain Vi to be full-scale (V) 32 0.825 1.212 99 2.5 0.4 The default programmed value is as follows: • NCOARSE = 32 • Gain = 0.825 • Vi to be full-scale = 1.212. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 18 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps To modulate this gain, the fine register is programmed using the above equation. With a full-scale ADC input, the fine register resolution is a 1⁄2 LSB peak-to-peak (see Table 7 for NCOARSE = 32). Table 7: Typical gain correspondence (FINE) NFINE Gain Vi to be full-scale (V) 0 0.825 1.212 31 0.878 1.139 The default programmed value is: NFINE = 0. 9.1.4 Control register COAST and HSYNC signals can be derived by setting the I2C-bus control bits ‘Vlevel’ and ‘Hlevel’ respectively. When bits ‘Vlevel’ and ‘Hlevel’ are set to zero, COAST and HSYNC are active HIGH. Bit ‘Edge’ defines the rising or falling edge of CKREF to synchronize the PLL. It will be on the rising edge if the bit is a logic 0 and on the falling edge if the bit is at logic 1. Bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These bits have to be logic 0 during normal use. Bit ‘Cken’ is used for the test to check the CKADC internal signal. This bit has to be logic 0 during normal use. Bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the bandwidth of the PLL, as shown in Table 8. Table 8: Charge pump current control Ip2 Ip1 Ip0 Current (µA) 0 0 0 6.25 0 0 1 12.5 0 1 0 25 0 1 1 50 1 0 0 100 1 0 1 200 1 1 0 400 1 1 1 700 The default programmed value is as follows: • • • • 9.1.5 Charge pump current = 700 µA Bits ‘Up’ and ‘Do’ are used for testing, normally they are set to logic 0 Rising edge of CKREF: bit ‘Edge’ at logic 0 COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0. VCO register Bits ‘Z2’, ‘Z1’ and ‘Z0’ enable the internal resistance for the VCO filter to be selected. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 19 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 9: VCO register bits Z2 Z1 Z0 Resistance (kΩ) 0 0 0 high-impedance 0 0 1 9 0 1 0 6.4 0 1 1 4.5 1 0 0 3.2 1 0 1 2.25 1 1 0 1.6 1 1 1 1.1 Bits ‘Vco1’ and ‘Vco0’ control the VCO gain. Table 10: VCO gain control Vco1 Vco0 VCO gain (MHz/V) Pixel clock frequency range (MHz) 0 0 12 10 to 20 0 1 20 20 to 40 1 0 40 40 to 85 1 1 70 85 to 170 The default programmed value is as follows: • Internal resistance = 2.25 kΩ • VCO gain = 70 MHz/V. 9.1.6 Divider register This register controls the PLL frequency. Bits ‘Di8’ to ‘Di0’ are the LSB bits. The default programmed value is 0110 1001 1000 = 1688. The MSB bits (‘Di11’, ‘Di10’ and ‘Di9’) and the LSB bit ‘Di0’ have to be programmed before bits ‘Di8’ to ‘Di1’ in order to have the required divider ratio. Bit ‘Di0’ is used for the parity divider number (Di0 = 0: even number; Di0 = 1: odd number). It should be noted that if the I2C-bus programming is done in mode 1 and the bit ‘Di0’ has to be toggled, then the registers have to be loaded twice to update the divider ratio. 9.1.7 Phase register Bit ‘Ckext’ is logic 0 when the PLL clock is used, and logic 1 when the external clock is used. Bit ‘Ckrs’ is logic 1 when the synchronization is done with CKREF (see Figure 3). Bits ‘P4’ to ‘P0’ are used to program the phase shift for the clock pixel. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 20 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 11: Phase registers bits P4 P3 P2 P1 P0 Phase shift (deg) 0 0 0 0 0 0 0 0 0 0 1 11.25 ... ... ... ... ... ... 1 1 1 1 0 337.5 1 1 1 1 1 348.75 The default programmed value is as follows: • No external clock: bit ‘Ckext’ is logic 0 • Phase shift for CKDATA is 0 degrees. 9.1.8 DEMUX register The default programming is: • • • • • • • 9.1.9 Outputs forced to logic 0 during CLP and HSYNC pulses: bit ‘Blk’ = 1 CKREFO with positive polarity: bit ‘Ckrp’ = 0 CKDATA not reversed: bit ‘Ckdp’ = 0 CKDATA not delayed: bit ‘Ckdd’ = 0 De-multiplexed outputs: bit ‘Dmx’ = 1 Interleaved outputs: bit ‘Shift’ = 1 Odd pixels on port A: bit ‘Odda’ = 1. Power-down mode • When the supply is completely switched off, the registers are set to their default values; in that event they have to be reprogrammed if the required settings are different (e.g. through an EEPROM) • When the device is in Power-down mode (pin PD = HIGH), the previously programmed register values remain unaffected. 9.2 I2C-bus protocol Table 12: Register format A6 A5 A4 A3 A2 A1 A0 RW 1 0 0 1 1 A2 A1 0 The address of the circuit for the I2C-bus is 1001 1XX0. Bits ‘A1’ and ‘A0’ are fixed by the potential on pins A2 and A1. Bit ‘RW’ must always be equal to logic 0 because it is not possible to read the data in the register. The timing and protocol for the I2C-bus are standard. Two sequences are available; see Table 13 and 14. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 21 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 13: Address sequence for mode 0 S = START condition, A = acknowledge bit (generated by the device) and P = STOP condition. S IC ADDRESS A SUBADDRESS A REGISTER1 DATA REGISTER1 (see Table 4) A SUBADDRESS A REGISTER2 ... P ... P Table 14: Address sequence for mode 1 S = START condition, A = acknowledge bit (generated by the device) and P = STOP condition. S IC ADDRESS A SUBADDRESS A XX11 1111 DATA REGISTER1 (see Table 4) A DATA REGISTER2 A 9.3 3W-bus protocol For the 3W-bus, the first byte refers to the register address which is programmed. The second byte refers to the data to be sent to the chosen register (see Table 4). Using a 3W-bus interface, an indefinite number of ICs can operate on the same system. Pin SEN is used to validate the circuits. t r3W = 600 ns 100 ns SEN 1 9 1 9 x D7 D6 D5 D4 D3 D2 D1 D0 SCL SDA x x x x A3 A2 A1 A0 x FCE707 t s3W = 100 ns t h3W = 100 ns Fig 9. 3W-bus protocol. 10. Limiting values Table 15: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCCA Conditions Min Max Unit analog supply voltage −0.3 +7.0 V VDDD logic supply voltage −0.3 +7.0 V VCCD digital supply voltage −0.3 +7.0 V VCCO output stages supply voltage −0.3 +7.0 V © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 22 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 15: Limiting values…continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter ∆VCC supply voltage differences Conditions Min Max Unit VCCA − VCCD −1.0 +1.0 V VCCO − VCCD −1.0 +1.0 V VCCO − VDDD −1.0 +1.0 V VCCA − VDDD −1.0 +1.0 V VCCD − VDDD −1.0 +1.0 V VCCA − VCCO −1.0 +1.0 V −0.3 +7.0 V Vi(RGB) RGB input voltage range referenced to AGND Io output current − 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature 0 70 °C Tj junction temperature − 150 °C 11. Thermal characteristics Table 16: Typical thermal characteristics Symbol Parameter Conditions Value Unit Rth(j-a) thermal resistance from junction to ambient in free air 30 K/W 12. Characteristics Table 17: Characteristics VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VCCA(PLL), VCCA(R), VCCA(G), VCCA(B) analog supply voltage for PLL and the RGB channels 4.75 5.0 5.25 V VDDD logic supply voltage for I2C-bus and 3W-bus 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO(PLL), VCCO(R), VCCO(G), VCCO(B) output stages supply voltage for PLL and the RGB channels 4.75 5.0 5.25 V ICCA(PLL) analog PLL supply current − 34 − mA © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 23 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 17: Characteristics…continued VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. Symbol Parameter ICCA(R), ICCA(G), ICCA(B) Conditions Min Typ Max Unit analog supply current for the RGB channels − 135 − mA IDDD logic supply current for I2C-bus and 3W-bus − 1 − mA ICCD digital supply current − 95 − mA ICCO(R), ICCO(G), ICCO(B), ICCO(PLL) output stages supply current for the RGB channels and PLL − 80 − mA ∆VCC supply voltage difference VCCA − VCCD −0.25 − +0.25 V VCCO − VCCD −0.25 − +0.25 V VCCO − VDDD −0.25 − +0.25 V VCCA − VDDD −0.25 − +0.25 V VCCD − VDDD −0.25 − +0.25 V −0.25 − +0.25 V − 1.5 − W − 55 − mW sinusoidal input VCCA − VCCO Ptot total power dissipation sinusoidal input Ppd power dissipation in Power-down mode R, G and B amplifiers B bandwidth −3 dB; Tamb = 25 °C 250 − − MHz tset(ADC+AGC) settling time of the block ADC + AGC full-scale (black to white) transition; input signal settling time <1 ns; settling to within 2 LSB − 4 − ns GCOARSE coarse gain range minimum coarse gain; code = 32 − −1.67 − dB maximum coarse gain; code = 99 − 8 − dB minimum fine input code = 0 − 0 − dB maximum fine input code = 31 − −0.5 − dB Vref with 100 ppm/°C maximum variation − 325 − ppm/°C − ±20 − µA − 25 − mdB/µs − 2.5 − V GFINE fine gain correction range ∆Gamp/∆T amplifier gain stability variation with temperature IGC gain current tstab amplifier gain adjustment speed from minimum to maximum gain Vref amplifier reference voltage HSYNC active; capacitors on pins 8, 16 and 24 are 22 nF © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 24 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 17: Characteristics…continued VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Iref amplifier reference voltage current Vi(p-p) input voltage (peak-to-peak value) Ci input capacitance GE(rms) channel-to-channel gain matching (RMS value) Conditions Min Typ Max Unit − 50 − µA corresponding to full-scale input at high gain − 0.4 − V corresponding to full-scale output at low gain − − 1.212 V − 10 − pF maximum coarse gain; Tamb = 25 °C − 1 − % minimum coarse gain; Tamb = 25 °C − 5 − % maximum black level noise on RGB channels = 10 mV; Tamb = 25 °C − 0.5 − LSB Clamps PCLP precision tW(CLP) clamp pulse width 500 − 2000 ns CLPE channel-to-channel clamp matching − 0.5 − LSB Aoff code clamp reference clamp register input code = 0 − −63.5 − LSB clamp register input code = 255 − +64 − LSB clamp register input code = 256 − +120 − LSB clamp register input code = 287 − +135.5 − LSB fclk = 170 MHz − 360 − ps Phase-locked loop (PLL) jPLL(max)(p-p) long term PLL phase jitter (peak-to-peak value) DR divider ratio 100 − 4095 − fref reference clock frequency 15 − 150 kHz fPLL output clock frequency 10 − 170 MHz standard at 160 Msps − − 2 step Tamb = 25 °C − 11.25 − deg 170 − − MHz ∆Φstep phase Φstep phase shift step drift [1] ADCs fs maximum sampling frequency INL DC integral non-linearity from IC analog input to digital output; sinusoidal input; fclk = 170 MHz − ±0.5 ±1.5 LSB DNL DC differential non-linearity from IC analog input to digital output; sinusoidal input; fclk = 170 MHz − ±0.4 ±1 LSB © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 25 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 17: Characteristics…continued VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. Symbol Parameter ENOB [2] effective number of bits Conditions Min Typ Max Unit − 7.4 − bits fclk = 170 MHz − 46 − dB fclk = 170 MHz − 57 − dB Signal-to-noise ratio S/N signal-to-noise ratio Spurious free dynamic range SFDR spurious free dynamic range Clock timing output (CKDATA) ηext ADC clock duty factor 45 50 55 % fclk(max) maximum clock frequency − − 170 MHz Clock timing input (CKEXT) fclk(max) maximum clock frequency − − 170 MHz tCPH clock pulse width HIGH 2.5 − − ns clock pulse width LOW 2.5 − − ns − −7.5 − ns − −7 − ns − 1 − ns tCPL Data timing [3] td(s) sampling delay time tsu(d)(o) output data set-up time th(o) output hold time all times referenced to 50% of the rising edge of CKDATA; see Figure 10 3-state output delay time tdZH output enable HIGH − 15 − ns tdZL output enable LOW − 18 − ns tdHZ output disable HIGH − 13 − ns tdLZ output disable LOW − 10 − ns Data and sync outputs VOL LOW-level output voltage Io = 1 mA − − 0.4 V VOH HIGH-level output voltage Io = 1 mA 2.4 − − V IOL LOW-level output current VOL = 0.2 V − 0.2 − mA IOH HIGH-level output current VOH = 3.4 V − 0.3 − mA CL load capacitance − 10 − pF − − 0.8 V TTL digital inputs (CKREF, COAST, INV, HSYNC, CLP, PD, DIS, I2C/3W, OE, CKEXT) VIL LOW-level input voltage VIH HIGH-level input voltage 2.0 − − V IIL LOW-level input current − 400 − µA IIH HIGH-level input current − 35 − µA Zi input impedance − tbf − kΩ Ci input capacitance − tbf − pF Slevel = 0; see Figure 5 300 − 600 mV Slevel = 1; see Figure 5 150 − 300 mV Sync on green input Vsync(G) sync on green pulse amplitude [4] © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 26 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 17: Characteristics…continued VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 3W-bus trst reset time of the chip before 3-wire communication − 600 − ns tsu data set-up time for 3-wire communication − 100 − ns th data hold time for 3-wire communication − 100 − ns I2C-bus [5] VIL LOW-level input voltage for SCL and SDA − − 0.3VDD V VIH HIGH-level input voltage for SCL and SDA; VPU = 5 V 3 − − V for SCL and SDA; VPU = 3 V 0.7VDD − − fSCL clock frequency 0 − 100 kHz tBUF time the bus must be free before new transmission can start 4.7 − − µs tHD;STA start condition hold time 4.0 − − µs tSU;STA start condition set-up time 4.7 − − µs tLOW LOW-level clock period 4.7 − − µs tHIGH HIGH-level clock period 4.0 − − µs tSU;DAT data set-up time 250 − − ns tHD;DAT data hold time 0 − − ns tr SDA and SCL rise time fSCL = 100 kHz − − 1.0 µs tf SDA and SCL fall time fSCL = 100 kHz − − 300 ns tSU;STO stop condition set-up time 4.0 − − µs Cb bus line capacitive loading − − 400 pF [1] [2] [3] [4] [5] repeated start From 25 to 70 °C, the edge of the clock CKDATA has a shift of 1 phase compared to CKREF. Effective bits are obtained from a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency). Conversion-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. Output data acquisition: the output data is available after the maximum sampling delay time td(s). All the timings are given for a 10 pF capacitive load. Pulse relative to the blank level. The I2C-bus timings are given for use of the bus at a frequency of 100 kbit/s (100 kHz). This bus could be used at a frequency of 400 kbit/s (400 kHz). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 27 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Table 18: Examples of PLL settings and performance VCCA = VDDD = VCCD = VCCO = 5 V; Tamb = 25 °C. KO CZ CP (MHz/V) (nF) (nF) IP Z Long-term time jitter [1] (µA) (kΩ) RMS-value peak-to-peak (ps) value (ps) 31.469 25.175 800 20 68 0.15 200 4.5 242 1452 VESA: 800 × 600 (SVGA 72 Hz) 48.08 50 1040 40 68 0.15 700 1.6 225 1350 VESA: 1024 × 768 (XGA 75 Hz) 60.02 78.75 1312 40 68 0.15 400 4.5 120 720 VESA: 1280 × 1024 (SXGA 60 Hz) 63.98 108 1688 70 68 0.15 400 3.2 98 588 VESA: 1280 × 1024 (SXGA 75 Hz) 80.00 135 1688 70 68 0.15 400 4.5 70 420 VESA: 1600 × 1200 (UXGA 60 Hz) 75.00 162 2160 70 68 0.15 400 4.5 65 390 Video standards fref (kHz) VGA: 640 × 480 [1] fclk (MHz) N PLL long-term time jitter is measured at the end of the video line, where it is at its maximum. tCPH tCPL n 50% CKDATA tsu(d)(o) In−1 DATA In 2.4 V In+1 0.4 V th(o) td(s) Vin Sample n+1 Sample n+2 Sample n+3 Sample n FCE700 Fig 10. Data timing; Dmx = 0; n = even pixel. RGBIN n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 CKADC CKDATA OUT A FCE701 Fig 11. Timing diagram; single port mode; Dmx = 0, Ckdd = 0, Ckdp = 0; n = even pixel. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 28 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps RGBIN n n+1 n+2 n+3 n+4 n+5 n+6 n+7 CKADC CKDATA OUT A n-2 n OUT B n+2 n-1 n+4 n+1 n+3 FCE702 Fig 12. Timing diagram; dual port mode, interleaved outputs, even pixels on port A; Dmx = 1, Shift = 1, Odda = 0, Ckdd = 0, Ckdp = 0; n = even pixel. RGBIN n n+1 n+2 n+3 n+4 n+5 n+6 n+7 CKADC CKDATA OUT A OUT B n-1 n-2 n+1 n n+3 n+2 n+4 FCE703 Fig 13. Timing diagram; dual port mode, interleaved outputs, odd pixels on port A; Dmx = 1, Shift = 1, Odda = 1, Ckdd = 0, Ckdp = 0; n = even pixel. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 29 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps RGBIN n n+1 n+2 n+3 n+4 n+5 n+6 n+7 CKADC CKDATA OUT A n-4 n-2 n n+2 OUT B n-3 n-1 n+1 n+3 FCE704 Fig 14. Timing diagram; dual port mode, synchronized outputs, even pixels on port A; Dmx = 1, Shift = 0, Odda = 0, Ckdd = 0, Ckdp = 0; n = even pixel. RGBIN n n+1 n+2 n+3 n+4 n+5 n+6 n+7 CKADC CKDATA OUT A n-1 n+1 n+3 OUT B n-2 n n+2 n+5 n+4 FCE705 Fig 15. Timing diagram; dual port mode, synchronized outputs, odd pixels on port A; Dmx = 1, Shift = 0, Odda = 1, Ckdd = 0, Ckdp = 0; n = even pixel. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 30 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 13. Application information OGNDR 1 109 110 A0R A1R ORR VCCO(R) OGND R 111 VCCO(R) 112 113 114 115 A3R A4R A5R A6R A2R 116 117 118 119 120 121 CKDATA CKREFO OGNDPLL A7R 122 123 TESTO 125 124 VCCO(PLL) 126 OE PD DGND1 n.c. 127 128 129 130 HSYNC INV CKEXT COAST CLP 131 132 133 134 135 136 n.c. VCCD1 137 138 139 CP CZ AGNDPLL 140 141 142 143 n.c. VCCA(PLL) AGNDPLL 108 2 VREF 3 DEC1 4 AGCR 5 10 nF BOT R 6 22 nF GAINCR 7 4.7 nF CLP R 8 10 nF DECR 9 VCCA(R) 10 100 nF INR RIN 11 n.c. 12 AGNDR 75 or 50Ω 13 n.c. 14 AGCG 15 10 nF BOTG 16 22 nF GAINCG 17 4.7 nF CLP G 18 10 nF DECG 19 VCCA(G) 20 100 nF ING GIN 21 AGNDG 22 INSOG 75 or 50Ω GIN 23 SOG 470 nF O 24 n.c. 25 AGCB 26 10 nF BOT B 27 22 nF GAINCB 28 4.7 nF CLP B 29 10 nF DECB 30 VCCA(B) 31 100 nF INB BIN 32 AGNDB 33 n.c. 75 or 50Ω 34 n.c. 35 n.c. 36 107 106 10 nF 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 TDA8757HL 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 VPU 10 kΩ 70 71 A1B A0B ORB 69 VCCO(B) 68 OGND B 67 65 OGND B 66 VCCO(B) B7B 64 B6B 63 B5B 62 B4B 61 60 B3B B2B 59 B1B 58 B0B 57 56 n.c. 55 VSSD3 VSSD2 54 n.c. 53 DGND2 52 51 VCCD2 n.c. 49 n.c. 50 n.c. 48 n.c. 47 46 10 kΩ SCL VDDD 45 VSSD1 43 42 44 SDA SEN 41 DIS 39 40 TDO A2 TCK 38 I2C/3W 37 A1 73 72 DEC2 144 n.c. 10 nF CKREF 150 pF 68 nF n.c. B7R B6R B5R B4R B3R B2R B1R B0R A7G A6G A5G A4G A3G A2G A1G A0G ORG VCCO(G) OGNDG VCCO(G) OGNDG B7G B6G B5G B4G B3G B2G B1G B0G A7B A6B A5B A4B A3B A2B GNDDP (tbf) 005aaa010 VPU For interfacing the 5 V digital outputs of TDA8757 to devices with 3 V compliant inputs, a resistor bridge (220 Ω in series, 820 Ω to ground) should be applied to each digital output. Fig 16. Application diagram. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 31 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 14. Package outline HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm; exposed die pad SOT612-1 c y X A Dh 73 72 108 109 ZE e Eh E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) Dh E(1) Eh e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 7.1 6.9 20.1 19.9 7.1 6.9 0.5 HD HE 22.15 22.15 21.85 21.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) 1.4 1.1 1.4 1.1 θ 7o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT612-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-22 02-01-25 MS-026 Fig 17. Package outline. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 32 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 16. Soldering 16.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 16.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C small/thin packages. 16.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 33 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 16.5 Package related soldering information Table 19: Suitability of surface mount IC packages for wave and reflow soldering methods Package Soldering method BGA, HBGA, LFBGA, SQFP, TFBGA Reflow[1] not suitable suitable suitable[2] HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not PLCC[3], SO, SOJ suitable not SSOP, TSSOP, VSO not recommended[5] [2] [3] [4] [5] suitable suitable recommended[3][4] LQFP, QFP, TQFP [1] suitable suitable All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Wave Rev. 07 — 28 February 2002 34 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 17. Revision history Table 20: Revision history Rev Date 07 20020228 CPCN Description - Preliminary data (9397 750 09457); seventh version © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Preliminary data Rev. 07 — 28 February 2002 35 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps 18. Data sheet status Data sheet status[1] Product status[2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 19. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21. Licenses Purchase of Philips I2C components 20. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Preliminary data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09457 Rev. 07 — 28 February 2002 36 of 37 TDA8757 Philips Semiconductors Triple 8-bit ADC 170 Msps Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 9 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.2 9.3 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 11 Analog video inputs . . . . . . . . . . . . . . . . . . . . 11 Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Variable gain amplifiers . . . . . . . . . . . . . . . . . 13 Important recommendations . . . . . . . . . . . . . . 13 ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C-bus and 3W-bus interfaces . . . . . . . . . . . . 17 Register definitions . . . . . . . . . . . . . . . . . . . . . 17 Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Offset register . . . . . . . . . . . . . . . . . . . . . . . . . 17 Coarse and Fine registers . . . . . . . . . . . . . . . 18 Control register . . . . . . . . . . . . . . . . . . . . . . . . 19 VCO register . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Divider register . . . . . . . . . . . . . . . . . . . . . . . . 20 Phase register. . . . . . . . . . . . . . . . . . . . . . . . . 20 DEMUX register . . . . . . . . . . . . . . . . . . . . . . . 21 Power-down mode . . . . . . . . . . . . . . . . . . . . . 21 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 3W-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal characteristics. . . . . . . . . . . . . . . . . . 23 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 23 Application information. . . . . . . . . . . . . . . . . . 31 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 Handling information. . . . . . . . . . . . . . . . . . . . 33 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 33 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 33 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 34 Package related soldering information . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 35 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 36 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 © Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 28 February 2002 Document order number: 9397 750 09457 20 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36