IMAGE SENSORS FT 18 Frame Transfer CCD Image Sensor Product specification File under Image Sensors Philips Semiconductors 2000 January 7 TRAD Philips Semiconductors Product specification Frame Transfer CCD Image Sensor • 2/3-inch optical format • 1M active pixels (1024H x 1024V) • Progressive scan • Excellent anti-blooming • Variable electronic shuttering • Square pixel structure • Hor. and Vert. binning • 100% optical fill factor • High dynamic range (>60dB) • High sensitivity • Low dark current and fixed pattern noise • Low read-out noise • Data rate up to 40 MHz • Frame rate up to 30 Hz • Mirrored read-out option FT 18 Description The FT 18 is a monochrome progressive-scan frame-transfer image sensor offering 1K x 1K pixels at 30 frames per second through a single output buffer. The combination of high speed and a high linear dynamic range (>10 true bits at room temperature without cooling) makes this device the perfect solution for high-end real time medical X-ray, scientific and industrial applications. A second output can be used for mirrored images. The device structure is shown in figure 1. 8 black lines 4 contour 8 black lines lines Device structure Optical size: Chip size: Pixel size: Active pixels: Total no. of pixels: Optical black pixels: Timing pixels: Dummy register cells: Contour lines: Optical black lines: 7.68 mm (H) x 7.68 mm (V) 8.9 mm (H) x 17.0 mm (V) 7.5 µm x 7.5 µm 1024 (H) x 1024 (V) 1072 (H) x 1048 (V) Left: 20 Right: 20 Left: 4 Right: 4 Left: 7 Right: 7 Bottom: 1 Top: 4 Bottom: 11 Top: 8 Image Section 20 1024 active pixels pix 4 1 contour line 1024 active lines 20 pix 11 black lines 2096 lines Storage Section Output 7 amplifier Figure 1 - Device structure 2000 January 2 1072 cells Output register 7 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Architecture of the FT 18 The FT18 consists of a shielded storage section and an open image section. Both sections have the same structure with identical cells and properties. The only difference between the two sections is the optical light shield. The storage section is controlled by four storage clocks (B1 to B4). An output register is located below the storage section for read-out. The output register has buffers at both ends. This allows either normal or mirrored read-out. The optical centres of all pixels in the image section form a square grid. The charge is generated and integrated in this section. The image section is controlled by four image clocks (A1 to A4). After integration, the image charge is completely shifted to the storage section. The integration time is electronically controlled by charge reset (CR). Transport of the pixels in the output register is controlled by three register clock phases (C1 to C3). The register can be used for vertical binning. Horizontal binning can be achieved by summing pixel charges under the floating diffusion. More information can be found in the application note. Figure 2 shows the detailed internal structure. IMAGE SECTION Image diagonal 10.9 mm Aspect ratio 1:1 Active image width x height 7.680 x 7.680 mm2 Total width x height 8.040 x 7.860 mm2 Pixel width x height 7.5 x 7.5 µm2 Geometric fill factor 100% Image clock pins A1, A2, A3, A4 Capacity of each clock phase <3.75nF per pin Number of active lines 1024 Number of contour lines 4 (top) + 1 (bottom) Number of black lines 8 (top) + 11 (bottom) Total number of lines 1048 Number of active pixels per line 1024 Number of overscan (timing) pixels per line 8 (2x4) Number of black reference pixels per line 40 (2x20) Total number of pixels per line 1072 Storage width x height STORAGE SECTION 8.040 x 7.860 mm2 Cell width x height 7.5 x 7.5 µm2 Storage clock phases B1, B2, B3, B4 Capacity of each B phase <4.1nF per pin Number of cells per line x number of lines 1072 x 1048 OUTPUT REGISTER Output buffers (three-stage source follower) 2 Number of registers 1 (bidirectional below storage) Number of register cells below storage 1072 Number of extra cells to output 2x7 Output register horizontal transport clock pins 3 (C1..C3) Capacity of each C-clock phase <85pF per pin Overlap capacity between neighbouring C-clocks <35pF Reset Gate clock phases 2 pins (RGL, RGR) Capacity of each RG <15pF 2000 January 3 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 A2 A2 A3 A3 A4 A4 A1 A1 12 lines A2 A2 A3 A3 A4 A4 One Pixel A1 A1 A2 A2 A3 A3 A4 A4 IMAGE A1 1K active images lines A2 A3 A4 A1 A2 A3 A4 A1 A1 A2 A2 A3 A3 A4 A4 A1 A1 12 lines A2 A2 A3 A3 A4 A4 FT CCD A1 A1 B2 B2 B3 B3 B4 B4 B1 B1 B2 A1 B2 A1 B3 B3 B4 B4 STORAGE B1 B2 B1 B2 B3 B3 B4 B4 B1 B1 1048 storage lines B2 A1 B2 A1 B3 B3 B4 B4 B1 B2 B2 B3 B3 B4 B4 B3 B3 B2 A1 B2 A1 B3 B3 B4 B4 OUTL OG C3 B1 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 column 24+1 column 1 7 extra cells 20 black & 4 timing columns C1 C3 C2 C1 C3 C2 column 24+1K 1K image pixels C2 C1 C3 4 timing & 20 black columns Figure 2 - Detailed internal structure 4 C1 C3 C2 C1 C3 C2 column 24+1K+24 A1, A2, A3, A4: clocks of image section B1, B2, B3, B4: clocks of storage section C1, C2, C3: clocks of horizontal register OG: output gate 2000 January OUTR B1 B1 7 extra cells C1 C3 OG Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Specifications Absolute Maximum Ratings Min. Max. Unit GENERAL: storage temperature ambient temperature during operation voltage between any two gates DC current through any clock (absolute value) OUT current (no short circuit protections) -55 -40 -20 -0.2 0 +80 +60 +20 +0.2 6 °C °C V µA mA VOLTAGES IN RELATION TO VNS: VPS, SFS SFD RD All other pins -30 -8 -15 -32 +0.5 +8 +0.5 +0.5 V V V V VOLTAGES IN RELATION TO VPS: VNS SFD, RD SFS All other pins -0.5 +0 -8 -20 +30 +30 +8 +20 V V V V DC Conditions1 Min. Typical Max. Unit 16 2 18 -2 3 12 adjusted 4 20 0 0 5.4 13 24 6 22 3 8 15 V V V V V V V Min. Typical Max. Unit IMAGE CLOCKS: A-clock swing A-clock low level Charge Reset (CR) level on A-clocks 3 Charge Pump (CP) level on A- clocks 9.5 - 10 0 -5 0 - V V V V STORAGE CLOCKS (duty cycle=5/8): B-clock swing B-clock low level 9.5 - 10 0 - V V OUTPUT REGISTER CLOCKS (duty cycle=1/2): C-clock swing C-clock low level - 5 3 OTHER CLOCKS: Reset Gate (RG) swing Reset Gate (RG) low level - 10 1 VNS2 VPS SFD SFS VCS OG RD N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain AC Clock Level Conditions1 1 - 12 - V V V V All voltages in relation to SFS. To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values. 3 Guaranteed charge reset requires the CR voltage to last at least 1.2µs. 2 2000 January 5 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Timing diagrams (for default operation) AC Characteristics Horizontal frequency (1/Tp) Vertical frequency Min. Typical Max. Unit - 36 750 40 833 MHz kHz Line Timing Phase or pixel count 1100 1110 1120 1130 1140 1150 10 20 30 40 50 60 70 80 90 100 110 120 0 1/(36MHz) = 27.8ns One charge pumping cycle of the image gates (during line blanking), shifting the charge of one line back and forth H L H A2 L H A3 L H A4 L A1 19 64 28 37 46 55 One cycle of the storage gates (during line blanking), moving one line from storage to output register 32 62 H B2 L 26 44 H B3 L 38 56 H B4 L 20 50 H B1 L SSC PB BLC CB CR H L H L H L H L H L 72 0 Start-Stop C-clocks 1080 pixels until 1152 C clocks stopped for 2 microseconds 0 79 0 79 Pre-Blanking Black Level Clamp 1131 99 Composite Blanking 19 Charge Reset 64 1.25 microseconds Pixel Timing Tp/6 = (1/36MHz)/6 = 4.63ns dummy 1 6 black 20 2000 January ....... Figure 3 - Line and pixel timing diagrams black 1 In this figure, charge is transported to the left output buffer (normal readout) by moving it from C1 to C2 to C3 etc. By exchanging the timing of C1 and C2, charge will be transported to the right output buffer (mirrored readout). timing 4 ....... timing 1 pixel 1024 ....... pixel 1 timing 4 ....... timing 1 black 20 ....... black 1 dummy 7 ....... dummy 1 H L H C1 L H C2 L H C3 L H RG L SSC Tp = 1/36MHz = 27.8ns Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Frame Timing Frame Transfer (FT): charge image (all lines) is moved from image to storage by the image and storage clocks together (see Figure "Frame Shift Timing"). internal LINE counter 1109 1110 1111 1112 1113 1114 1115 1116 ...... 1119 1120 1121 1122 ...... 1250 1 ...... 26 27 ...... 70 video 1024 D D B B BLC BLC B B D D E line no. Charge Pump (CP): a measure to reduce dark current due to interface states. For details see figure 3 "Line and pixel timing diagrams". H A1 L H A2 L H A3 L H A4 L 71 72 73 74 75 76 E E E E B B 79 80 81 82 83 BLC BLC B 77 78 B D D C ...... 86 87 88 C 1 2 Hustle: moving the charge packets of one line from storage to the output register. For details see figure 3 "Line and pixel timing diagrams". B1 B2 B3 B4 SSC CR BLC PB CB H L H L H L H L Linetime: the C-clocks shift charge packets one-by-one to the selected output buffer. For details see figure 3 "Line and pixel timing diagrams". H L H L H L H L H L By adding one CR-pulse during the horizontal blanking, the effective integration time is decreased: "electronic shuttering" CR before nominal integration Black-Level Clamp (BLC): the video processing clamps the black lines to determine its output zero-level. Frame Shift Timing 48 Tp Tp=1/(36MHz) = 27.8ns A1 H 750kHz 1 2 1047 1048 1 2 1047 1048 L A2 H L A3 H L A4 H L B1 H L B2 H L B3 H L B4 H L 30Tp 18Tp for all A and B clocks, duty cycle = 5/8 Figure 4 - Frame timing diagrams 2000 January 7 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Performance • The vertical transport or frame shift frequency equals 750kHz (714kHz). • The horizontal transport or read-out frequency equals 36MHz (40MHz). • The RMS read-out noise of the output buffers and the FPN are measured in the bandwidth 0.1-18MHz (0.1-20MHz). • The performance in dark is given at a temperature of 318K / 45°C. Note that the dark current decreases by a factor of two for every decrease of temperature of approximately 10°C. The performance of the FT 18 is described for modes of operation with 25 frames/sec or 30 frames/sec respectively. Measurements for the FT 18 are done under the following circumstances (values in brackets apply for the 30 frames/sec mode): • VNS is adjusted as low as possible while maintaining proper Vertical Anti-Blooming. • Integration takes place under 2 gates with 10V clock swing during 40ms (33.33ms) Linear / Saturation Min. Typical Max. Unit Overexposure over entire area while maintaining good VAB 300 - - lux Vertical resolution (MTF) @ 67 lp/mm 25 - - % Quantum efficiency @ 450 nm 10 11 - % Quantum efficiency @ 520 nm 21 22 - % Quantum efficiency @ 600 nm 18 19 - % Quantum efficiency @ 800 nm (near IR) 5 - - % Image lag - 0 - % White Shading 1 - - 2.5 % - 1.0 1.4 % 120 - - kel. Random Non-Uniformity (RNU) 2 Full-well capacity Floating Diffusion (FD) Full-well capacity saturation level (Q ) 3 image max 40 45 - kel. Full-well capacity saturation level (Q max ) storage 45 - - kel. Full-well capacity saturation level (Q ) output register 4 max 90 - - kel. Sensitivity @ 3200K without IR cut-off filter 5.6 5.8 - kel/lux Smear without shutter 5 - - 0.39 % Dynamic range 60 63.8 - dB RMS read-out noise - 29 38 el 4.6 4.8 - kel/lux 25 frames/sec mode only 30 frames/sec mode only Sensitivity @ 3200K without IR cut-off filter - - 0.40 % Dynamic range 60 63.5 - dB RMS read-out noise - 30 40 el Smear without shutter 1 5 White Shading is defined as the ratio of the one-σ value of an 8x8 pixel blurred image (low-pass) to the mean signal value. Random Non Uniformity is defined as the ratio of the one- σ value of the highpass image to the mean signal value at nominal light. Q max is determined from the lowpass filtered image. 4 Q max of the output register may be increased up to 200kel. In this case the charge packets of the pixels may get mixed in the output register during horizontal transport. This may reduce the number of times that the output register needs to be read out if lines are read out solely to be dumped. 5 The smear condition is: overexposure with a spot with a height of 10% of the image height (approx. 100 lines). 2 3 2000 January 8 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Quantum efficiency (%) 30 20 10 0 400 500 600 700 800 Wavelength (nm) Figure 5 - Quantum efficiency versus wavelength 2000 January 9 900 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Output Buffers Min. Conversion factor 8.5 Typical Max. 10 11.5 Unit µV/el. Supply current 4 mA Bandwidth 110 MHz Output impedance buffer (Rload = 3.3kΩ, Cload = 2pF) 400 Ω Dark Condition Min. Typical Max. Unit - - 240 pA/cm2 - - 25 el Average dark signal - 56 67 el Shot noise of the dark current - - 10 el Horizontal shading - - 25 el Vertical shading - - 66 el - - 19 el Average dark signal - 47 56 el Shot noise of the dark current - - 10 el Horizontal shading - - 25 el Vertical shading - - 56 el - - 19 el Dark current Black level offset 1 Dark condition at 25 frames/sec: Fixed Pattern Noise 2 in dark (FPN) Dark condition at 30 frames/sec: Fixed Pattern Noise 1 2 2 in dark (FPN) Black level offset is defined as the difference in dark signal of a black refence line and an active image line. FPN is the one-σ value of the highpass image. 2000 January 10 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Application information Current handling One of the purposes of VPS is to drain the holes that are generated during exposure of the sensor to light. Free electrons are either transported to the VRD connection and, if excessive (from overexposure), free electrons are drained to VNS. No current should flow into any VPS connection of the sensor. During high overexposure a total current 10 to 15mA through all VPS connections together may be expected. The PNP emitter follower in the circuit diagram (figure 6) serves these current requirements. a high-frequency transistor. Mount the base of this transistor as close as possible to the sensor and keep the connection between the emitter and the next stage short. The CCD output buffer can easily be destroyed by ESD. By using this emitter follower, this danger is suppressed; do NOT reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the output of the emitter follower. Slew rate limitation is prevented by avoiding a too-small quiescent current in the emitter follower; about 10mA should do the job. The collector of the emitter follower should be decoupled properly to suppress the Miller effect from the base-collector capacitance. A CCD output load resistor of 3.3kΩ typically results in a bandwidth of 110MHz. The bandwidth can be enlarged to about 130MHz by using a resistor of 2.2kΩ instead, which, however, also enlarges the on-chip power dissipation. VNS drains superfluous electrons as a result of overexposure. In other words, it only sinks current. During high overexposure a total current of 10 to 15mA through all VNS connections together may be expected. The NPN emitter follower in the circuit diagram meets these current requirements. Decoupling of DC voltages All DC voltages should be decoupled with a 100nF decoupling capacitor. This capacitor must be mounted as close as possible to the sensor pin. Further noise reduction (by bandwidth limiting) is achieved by the resistors in the connections between the sensor and its voltage supplies. The electrons that build up the charge packets that will reach the floating diffusions only add up to a small current, which will flow through VRD. Therefore a large series resistor in the VRD connection may be used. Device protection The output buffers of the FT 18 are likely to be damaged if VPS rises above SFD or RD at any time. This danger is most realistic during power-on or power-off of the camera. The RD voltage should always be lower than the SFD voltage. Never exceed the maximum output current. This may damage the device permanently. The maximum output current should be limited to 6mA. Be especially aware that the output buffers of these image sensors are very sensitive to ESD damage. Outputs To limit the on-chip power dissipation, the output buffers are designed with open source outputs. Outputs to be used should therefore be loaded with a current source or more simply with a resistance to GND. In order to prevent the output (which typically has an output impedance of about 400Ω) from bandwidth limitation as a result of capacitive loading, load the output with an emitter follower built from 2000 January Because of the fact that our CCDs are built on an n-type substrate, we are dealing with some parasitic npn transistors. To avoid activation of these transistors during switch-on and switch-off of the camera, we recommend the application diagram of figure 6. 11 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Device Handling An image sensor is a MOS device which can be destroyed by electrostatic discharge (ESD). Therefore, the device should be handled with care. When cleaning the glass we recommend using ethanol (or possibly water). Use of other liquids is strongly discouraged: • if the cleaning liquid evaporates too quickly, rubbing is likely to cause ESD damage. Always store the device with short-circuiting clamps or on conductive foam. Always switch off all electric signals when inserting or removing the sensor into or from a camera (the ESD protection in the CCD image sensor process is less effective than the ESD protection of standard CMOS circuits). • the cover glass and its coating can be damaged by other liquids. Rub the window carefully and slowly. Being a high quality optical device, it is important that the cover glass remain undamaged. When handling the sensor, use fingercots. Dry rubbing of the window may cause electro-static charges or scratches which can destroy the device. VSFD keep short <10mm! BC 850C 100nF OUT 100 Ω BAT74 Schottky! VPS VOG 100nF VRD VCS 100nF 100nF 10kΩ 100nF BC 860C 15 Ω BAT74 Schottky! 10kΩ 10kΩ Figure 6 - Application diagram to protect the FT 18 2000 January 12 <7pF! SFD BFR 92A output for preprocessing 1k Ω 3.3kΩ 100nF 0.5-1mA 0.5-1mA 27 Ω VNS 10mA BC 850C 100nF 0.5-1mA BAT74 keep short! Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Pin configuration The FT18 is mounted in a ceramic DIL 32-pin package. The position of pin 1 is marked with a white dot on top of the package. Pinning Symbol VNS VNS VPS VPS SFDL SFDR SFSL SFSR VCSL VCSR OGL OGR RDL RDR A1 A2 A3 A4 B1 B2 B3 B4 C1 C1 C2 C2 C3 C3 RGL RGR OUTL OUTR 2000 January Name Pin # N substrate N substrate P well P well Source Follower Drain Left Source Follower Drain Right Source Follower Source Left Source Follower Source Right Current Source Gate Left Current Source Gate Right Output Gate left Output Gate Right Reset Drain Left Reset Drain Right Image Clock (Phase 1) Image Clock (Phase 2) Image Clock (Phase 3) Image Clock (Phase 4) Storage Clock (Phase 1) Storage Clock (Phase 2) Storage Clock (Phase 3) Storage Clock (Phase 4) Register Clock (Phase 1) Register Clock (Phase 1) Register Clock (Phase 2) Register Clock (Phase 2) Register Clock (Phase 3) Register Clock (Phase 3) Reset Gate Left Reset Gate Right Output Left Output Right 12 21 5 28 9 24 8 25 7 26 6 27 11 22 3 4 30 29 1 2 32 31 14 19 15 18 16 17 13 20 10 23 13 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 B3 32 B4 31 A1 A3 30 4 A2 A4 29 5 VPS VPS 28 6 OGL 7 1 B1 2 B2 3 TOP OGR 27 VCSL VCSR 26 8 SFSL SFSR 25 9 SFDL SFDR 24 10 OUTL OUTR 23 11 RDL B4 RDR 22 12 VNS B1 VNS 21 13 RGL RGR 20 14 C1 C1 19 15 C2 C2 18 16 C3 C3 17 STORAGE B1 B4 IMAGE FT18 Figure 7 - FT18 pin configuration (top view) 2000 January 14 Philips Semiconductors Product specification Frame Transfer CCD Image Sensor FT 18 Package information 9.575 ±0.2 4.92 ±0.2 29.70 ±0.3 7.68 ±0.2 25.4 ±0.1 0.78 ±0.05 1.778 ±0.13 2.868 ±0.29 3.3 ±0.2 7.747 ±0.2 1 / 100 B 3.317 ±0.2 B 0.48 ±0.05 0.762 ±0.07 4.5 ±0.3 15.494 ±0.25 0.25 +0.05 -0.02 Angle of rotation: less than ± 10 Sensor flatness: < 7 µm (P-V) Cover glass: Corning 7059 Thickness of cover glass: 0.8 ± 0.05 Refractive index: nd = 1.53 Single sided AR coating inside, 21% reflection (430-660 nm) All drawing units are in mm. Figure 8 - Mechanical drawing of the FT 18 package 2000 January 15 2.986 ±0.29 1.4 / 100 0.725 ±0.05 Crystal + Glue 0.8 ±0.05 0.08 +0.07 -0.02 Glue Sensor crystal 0.665 ±0.07 Anti-reflex coating 1.090 ±0.11 Cover glass 1.016 ±0.10 15.24 ±0.25 15 ±0.1 Image area 0.005 Product specification Frame Transfer CCD Image Sensor Order codes The sensor can be ordered using the following code: FT18 sensors Description Quality Grade Order Code FT18/TG Test grade 9922 157 32031 FT18/IG Industrial grade 9922 157 32021 FT18/HG High grade 9922 157 32011 FT18/SG Selected grade 9922 157 32001 You can contact the Image Sensors division of Philips Semiconductors at the following address: Philips Semiconductors Image Sensors Internal Postbox WAG-05 Prof. Holstlaan 4 5656 AA Eindhoven The Netherlands phone fax +31 - 40 - 27 44 400 +31 - 40 - 27 44 090 www.semiconductors.philips.com/imagers/ FT 18 Philips reserves the right to change any information contained herein without notice. All information furnished by Philips is believed to be accurate. © Philips Electronics N.V. 2000 9922 157 32001 Philips Semiconductors lmtb Philips Semiconductors TRAD