INTEGRATED CIRCUITS DATA SHEET SAA7360 Bitstream conversion ADC for digital audio systems Product specification Supersedes data of July 1993 File under Integrated Circuits, IC01 Philips Semiconductors 1995 Apr 24 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 FEATURES • Stereo input • Single-ended input • Uncommitted input buffer for filtering and pre-scaling • Fully differential analog-to-digital converter (ADC) using 3rd order Sigma-Delta modulation • 128 times oversampling • Four stage digital decimation filter • Switchable high-pass filter to remove DC offsets GENERAL DESCRIPTION • 16-bit or 18-bit selectable output in a multiple of formats The SAA7360 is a CMOS ADC using Philips bitstream conversion technique. The device is designed for digital audio playback systems, such as digital amplifiers, CD-recordable and Digital Compact Cassette (DCC). The device is a complementary device to the SAA7350 bitstream conversion digital-to-analog converter (DAC). • Sampling rates between 18 and 53 kHz supported • Master or slave operation • Choice of 2 crystal frequencies • Single power supply operation (+5 V). QUICK REFERENCE DATA SYMBOL PARAMETER VDD supply voltage fxtal crystal frequency THD + N total harmonic distortion + noise CONDITIONS 256fs 512fs MIN. TYP. MAX. UNIT 4.5 5.0 5.5 V − 11.2896 − MHz − 22.5792 − MHz − −90 −85 dB ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7360GP QFP44(1) DESCRIPTION plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 × 14 × 2.2 mm VERSION SOT205-1 Note 1. When using IR reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Pocketbook” (order number 9398 510 34011) are followed. 1995 Apr 24 2 VDACP DCKO XIN XOUT 34 32 33 18 16 6 7 XSYS1 XSYS2 8 9 TIMING AND CONTROL SDM 1 V refL 40 MUX 39 29 VDDAT VSSAT V refL 35 19 21 42 TIMING 1st DECIMATION FILTER STAGE 8f s 2nd DECIMATION FILTER STAGE 41 fs OUTPUT INTERFACE HIGHPASS FILTER 14 11 V ref 12 13 3 I ref 28 FSEL 128f s 27 20 V refR DIOL 30 V refL VDACN PINL 10 MUX I ref WSEL TSEL Philips Semiconductors BAIL NINL Bitstream conversion ADC for digital audio systems 31 BBOL BLOCK DIAGRAM 1995 Apr 24 BAOL ODF1 ODF2 SWSO SCKO SDO SWSI SCKI 128f s BAIR 44 26 SAA7360 SDM 43 V refR VDDA 3 37 RESET TEST2 36 25 BAOR 22 BBOR 24 NINR 23 PINR 15 DSEL 38 17 2 5 4 HPEN TEST1 VDDD VSSD DIOR Product specification Fig.1 Block diagram. MLA714 - 1 SAA7360 handbook, full pagewidth V SSA V refR CEN Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 PINNING SYMBOL PIN DESCRIPTION FSEL 1 Crystal frequency select input. This pin is used to select the master crystal frequency as follows: FSEL = HIGH = 256fs; FSEL = LOW = 512fs; if unconnected the pin will default HIGH. TEST1 2 test input 1; this pin should be left open-circuit TEST2 3 test input 2; this pin should be left open-circuit VSSD 4 supply ground for the digital section VDDD 5 supply voltage for the digital section (+5 V) XIN 6 crystal oscillator input XOUT 7 crystal oscillator output XSYS1 8 system clock output XSYS2 9 output clock at a frequency half the system clock frequency SCKI 10 serial interface clock input SCKO 11 serial interface clock output SDO 12 serial interface data output SWSI 13 serial interface word select input SWSO 14 serial interface word select output DSEL 15 input for selecting between the internally generated 1-bit code (DSEL = HIGH) or an externally generated 1-bit code (DSEL = LOW); if unconnected this pin defaults HIGH DCKO 16 1-bit code clock output DIOR 17 1-bit code input/output (right channel) DIOL 18 1-bit code input/output (left channel) VSSAT 19 supply ground for the analog timing section VDDAT 20 supply voltage for the analog timing section (+5 V) VrefR 21 voltage reference generator for the right channel analog section BBOR 22 output of right channel buffer operational amplifier ‘B’ PINR 23 positive input to right channel Sigma-Delta modulator NINR 24 negative input to right channel Sigma-Delta modulator BAOR 25 output of right channel buffer operational amplifier ‘A’ BAIR 26 input of right channel buffer operational amplifier ‘A’ VDACN 27 negative voltage reference level input for the DACs Iref 28 current reference output VDACP 29 positive voltage reference level input for the DACs BAIL 30 input of left channel buffer operational amplifier ‘A’ BAOL 31 output of left channel buffer operational amplifier ‘A’ NINL 32 negative input to left channel Sigma-Delta modulator PINL 33 positive input to left channel Sigma-Delta modulator BBOL 34 output of left channel buffer operational amplifier ‘B’ VrefL 35 voltage reference generator for the left channel analog section VDDA 36 supply voltage for the analog section (+5 V) VSSA 37 supply ground for the analog section 1995 Apr 24 4 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL SAA7360 PIN DESCRIPTION HPEN 38 high-pass filter enable input (HPEN = HIGH = enabled); if unconnected this pin defaults HIGH TSEL 39 input to select master (TSEL = LOW) or slave (TSEL = HIGH) operation of the serial interface; if unconnected this pin defaults HIGH WSEL 40 input to indicate 16-bit (WSEL = HIGH) or 18-bit (WSEL = LOW) output data word length of the serial interface; if unconnected this pin defaults HIGH ODF2 and ODF1 41 and 42 serial interface format inputs; these 2 pins determine the interface format in which the device will operate (see Chapter “Functional Description”); if unconnected these pins will default HIGH (I2S format) V refL BBOL 34 FSEL 1 33 PINL TEST1 2 32 NINL TEST2 3 31 BAOL VSSD 4 30 BAIL VDDD 5 29 V DACP XIN 6 XOUT 7 27 VDACN XSYS1 8 26 BAIR XSYS2 9 25 BAOR SAA7360 28 I ref 5 MLA715 - 2 BBOR 22 V refR 21 VDDAT 20 DIOL 18 VSSAT 19 DIOR 17 DCKO 16 DSEL 15 23 PINR SWSO 14 SCKO 11 SWSI 13 24 NINR SDO 12 SCKI 10 Fig.2 Pin configuration. 1995 Apr 24 35 37 VSSA 36 VDDA 38 HPEN 39 TSEL 40 WSEL ODF1 44 CEN handbook, full pagewidth 41 ODF2 Chip enable input; this pin, when LOW, disables the operation of the device and 3-states the outputs of the serial interface bus. This enables the connection of one of more devices to the output bus; if unconnected this pin defaults HIGH. 42 Power-On Reset (POR) input (active LOW) to mute the digital output during power on 44 RESET 43 CEN 43 RESET Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 allow a headroom of 1 dB to prevent clipping with DC offsets. FUNCTIONAL DESCRIPTION General The overall response of the digital decimation filter is a pass band from 0fs to 0.454fs (20 kHz at fs = 44.1 kHz) with a ripple of <0.0002 dB and a transition band of 0.454fs to 0.544fs. All frequencies between 0.544fs and 64fs which could result in aliasing into the base band are attenuated by >−93 dB. The SAA7360 is a bitstream conversion CMOS ADC for digital audio systems. The device consists of a input buffer which can be configured by the user for pre-scaling and anti-aliasing, a third order Sigma- Delta modulator with a performance of better than 90 dB THD + Noise, and decimation filters with anti-aliasing suppression of >93 dB and in band ripple of less than 0.0002 dB. The device outputs data in a number of formats compatible with a range of manufacturers. High-pass filter The operational amplifiers in the Sigma-Delta modulator can cause a small DC offset to be present in the 1-bit code passed to the digital section. This can result in the possibility of clicks when switching between devices and the recording of DC offsets which can upset offsets introduced in filters and noise shaping DACs in the playback path. A switchable high-pass filter is included on the IC after the decimation filter stage to allow the user to remove these DC offsets (selectable via pin HPEN). The filter does not affect the decimation process. The filter is 1st order high pass with following specifications: Clock frequency The SAA7360 can operate in either master or slave mode (CMOS input drive levels). The clock can be either 256fs or 512fs (where fs is the sampling frequency) indicated via pin FSEL. System clock outputs equal to the input frequency (XSYS1) and half the input frequency (XSYS2) are provided to drive other ICs in the system. All performance parameters track with fs which can vary between 18 and 53 kHz without degradation of performance. • Corner frequency (−3 dB): 1.7 Hz • Ripple: none Input buffer • Above 100 Hz: <0.00002 dB; <1 degree The input buffer stage consists of an uncommitted input operational amplifier (‘A’) and a committed unity gain operational amplifier (‘B’) to perform a single-to-double ended conversion for the differential ADC. The input buffer can be configured for pre-scaling and second order anti-aliasing filtering. The scaling should be performed so as to provide a maximum of 1 V RMS value at the output of the operational amplifier. • At 20 Hz: −0.03 dB, 5 degree phase deviation • Noise floor: −116 dB. Output interface The output interface can operate in master or slave mode selectable by pin TSEL. Master mode drives pins SWSO (word select), SCKO (bit clock) and SDO (data output). Slave mode receives the word clock on pin SWSI and the bit clock on pin SCKI. In slave mode the internal circuitry runs on the incoming bit clock and therefore cannot operate with burst clocks. Slave mode causes the pins SWSO and SCKO to be 3-stated allowing systems to connect SWSO and SCKO to pins SWSI and SCKI respectively for applications where the device has to operate in master and slave modes. The bit clock in master mode is at 32fs for 16-bit output, and 64fs for 18-bit output. In slave mode the bit clock is a minimum of 32fs and a maximum of 64fs. Sigma-Delta modulator The analog-to-digital conversion is performed by a third order Sigma-Delta modulator, which outputs a 1-bit code at 128fs with a distortion plus noise figure of >90 dB. The modulator is scaled so that a 0 dB input results in an output of −3 dB, at the 1-bit outputs. Digital decimation filter The left and right channel 1-bit codes from the ADC are decimated from 128fs to 1fs in four stages of filtering. The first filter stage decimates by a factor of 16fs to 8fs using a 4th order combination type filter. The other three filter stages consist of three cascaded half-band filters each decimating by a factor of two. The half-band filter decimating from 8fs to 4fs has a gain of +2 dB to compensate for the −3 dB through the analog part and 1995 Apr 24 Three output formats are supported, I2S and two pseudo I2S modes common in digital audio ADC systems. These formats are shown in Fig.3. Selection of the three formats is given in Table 1. 16-bit or 18-bit output words can be chosen (via pin WSEL). 6 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems Table 1 SAA7360 Output data formats ODF2 ODF1 0 0 test 0 1 format 1 1 0 format 2 1 1 I2S Reset When pin RESET is held LOW the data outputs are set to zero. The RESET pin operates as a Schmitt trigger, enabling a power-on reset function by using an external RC circuit. MODE LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT −0.5 +6.5 V DC input voltage −0.5 +6.5 V IIK DC input diode current − ±20 mA VO DC output voltage −0.5 VDD + 0.5 V IO DC output source or sink current − ±20 mA IDD or ISS total DC VDD or VSS current − ±0.5 A Tamb operating ambient temperature −40 +85 °C Tstg storage temperature −65 +150 °C Ves electrostatic handling VDDA analog supply voltage VI note 1 note 2 −2000 +2000 V note 3 −200 +200 V Notes 1. All VDD and VSS pins must be externally connected to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor. CHARACTERISTICS VDD = 5 V; Tamb = 25 °C; fxtal = 256fs; fs = 44.1 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage 4.5 5.0 5.5 V IDDA analog supply current − 43 − mA VDDD digital supply voltage 4.5 5.0 5.5 V IDDD digital supply current − 50 − mA Ptot total power consumption − 465 − mW 1995 Apr 24 7 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL PARAMETER SAA7360 CONDITIONS MIN. TYP. MAX. UNIT Digital part inputs FSEL, HPEN, DSEL, TSEL, WSEL, ODF2, ODF1 AND CEN VIL LOW level input voltage note 1 −0.5 − +0.8 V VIH HIGH level input voltage note 1 2.0 − VDDD + 0.5 V Zi input impedance − 35 − kΩ Ci input capacitance − − 10 pF RESET VIL LOW level input voltage note 1 −0.5 − +0.2VDDD V VIH HIGH level input voltage note 1 0.6VDDD − VDDD + 0.5 V ∆VI input hysteresis 0.2 − − V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF note 2 SCKI and SWSI VIL LOW level input voltage note 1 −0.5 − +0.8 V VIH HIGH level input voltage note 1 2.0 − VDDD + 0.5 V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF −0.5 − +0.8 V 0.7VDDD − VDDD + 0.5 V −10 − +10 µA − − 10 pF Crystal oscillator input XIN VIL LOW level input voltage VIH HIGH level input voltage ILI input leakage current Ci input capacitance note 2 Outputs SWSO, SCKO AND SDO VOL LOW level output voltage −400 µA; note 1 − − +0.4 V VOH HIGH level output voltage 20 µA; note 1 2.4 − − V CL load capacitance − − 50 pF ILI leakage current in 3-state note 2 −10 − +10 µA − − 0.4 V XSYS1 AND XSYS2 VOL LOW level output voltage −400 µA; note 1 VOH HIGH level output voltage 20 µA; note 1 CL load capacitance 2.4 − − V − − 35 pF − 1.0 V DCKO VOL LOW level output voltage −400 µA; note 1 − VOH HIGH level output voltage 20 µA; note 1 VDDD − 1.0 − − V CL load capacitance − 20 pF 1995 Apr 24 8 − Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL SAA7360 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Input/outputs DIOR and DIOL VIL LOW level input voltage note 1 −0.5 − +0.8 V VIH HIGH level input voltage note 1 2.0 − VDDD + 0.5 V Zi input impedance − 35 − kΩ Ci input capacitance − − 10 pF VOL LOW level output voltage −400 µA; note 1 − − 1.0 V VOH HIGH level output voltage 20 µA; note 1 VDDD − 1.0 − − V CL load capacitance − − 20 pF 4.608 256fs or 512fs 27.136 MHz Crystal oscillator input XIN and output XOUT fxtal crystal operating frequency note 3 Gm mutual conductance 100 kHz 1.5 − − mA/V Gv small signal voltage gain Gv = Gm × Ro − 3.5 − V/V Ci input capacitance − − 10 pF CFB feedback capacitance − − 5 pF Co output capacitance ILI input leakage current − − 10 pF note 2 −10 − +10 µA Timing External clock input XIN fi input frequency note 3 4.608 256fs or 512fs 27.136 MHz tr input rise time VIL to VIH − − 10 ns tf input fall time VIH to VIL − − 10 ns msr mark-space ratio slave mode; 256fs 45 − 55 % slave mode; 512fs 40 − 60 % System clock outputs XSYS1 and XSYS2 (note 4) tr output rise time VOL to VOH − − 15 ns tf output fall time VOH to VOL − − 15 ns tH output HIGH time (relative to clock period) note 5 40 50 60 % 1-bit code outputs (see Fig.4); 1−bit code inputs (see Fig.5) CLOCK DCKO tr clock output rise time note 6 − − 15 ns tf clock output fall time note 6 − − 15 ns tH clock output HIGH time 45 − − ns tL clock output LOW time 45 − − ns 1995 Apr 24 9 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL PARAMETER SAA7360 CONDITIONS MIN. TYP. MAX. UNIT DATA DIOL AND DIOR tdor data output rise time note 6 − − 15 ns tdof clock output fall time note 6 − − 15 ns td data output delay time (relative to DCKO) note 6 −30 − +30 ns tdir data input rise time − − 20 ns tdif data input fall time − − 20 ns tsu data input set-up time (relative to DCKO) 30 − − ns th data input hold time (relative to DCKO) 30 − − ns Serial data outputs (see Fig.6) CLOCK SCKO tr clock output rise time note 7 − − 30 ns tf clock output fall time note 7 − − 30 ns WORD SELECT SWSO tr word select output rise time note 7 − − 30 ns tf word select output fall time note 7 − − 30 ns tsr word select output set-up time note 8 100 − − ns thr word select output hold time 100 − − ns note 8 CLOCK SCKI (note 9) tr clock input rise time − − 100 ns tf clock input fall time − − 100 ns tHC clock input HIGH time 50 − − ns tLC clock input LOW time 50 − − ns WORD SELECT SWSI (note 9) tr word select input rise time − − 100 ns tf word select input fall time − − 100 ns tsr word select input set-up time note 10 100 − − ns thr word select input hold time note 10 100 − − ns tr data output rise time note 7 − − 30 ns tf data output fall time note 7 − − 30 ns tdod data output delay time note 10 −100 − +100 ns tsr data output set-up time note 8 100 − − ns thr data output hold time note 8 100 − − ns DATA SDO 1995 Apr 24 10 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL SAA7360 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog part VOLTAGE REFERENCE VrefL AND VrefR VI input voltage 2.0 2.3 2.7 V − V refR ---------------13 kΩ − A − VSSA − V − VDDA − V − 1 − V Current reference Iref (note 11) IO output current DAC reference INPUT VDACN VI input voltage INPUT VDACP VI input voltage Sigma-Delta modulator inputs PINR, NINR, PINL and NINL VI(rms) input voltage (RMS value) note 12 ADC performance (note 13) THD + N total harmonic distortion + noise at −1 dB digital output; − note 14 −90 (0.003%) −85 (0.0056%) dB DR dynamic range note 14 93 97 − dB αcs channel separation fi = 1 kHz; note 15 − 100 − dB −1.5 −1 −0.5 dB − 1.25 − ms G gain tgd group delay (in pass band) note 16 Notes 1. Minimum VIL, VOL and maximum VIH, VOH are peak values to allow for transients. 2. ILI minimum and ILO minimum measured at VI = 0 V; ILI maximum and ILO maximum measured at VI = VDDD. 3. fxtal is a multiple of the system sampling frequency fs which can vary between 18 and 53 kHz. 4. Output times are measured with a capacitive load of 35 pF; XSYS2 is the master clock frequency divided by 2. 5. tH valid only when used with XTAL, with 50% input mark space ratio; XSYS1 (tH) is measured at 1⁄2VDDD. 6. Output times are measured with a capacitive load of 20 pF. 7. Output times are measured with a capacitive load of 50 pF. 8. Relative to SCKO in master mode. 9. In slave mode the number of SCKI clocks in each channel should be <33 and the same in both. The polarity of SWSI indicates left/right channel. 10. Relative to SCKI in slave mode. 11. Iref connected to 0 V via a 13 kΩ resistor. 12. The maximum recommended input voltage (referred to as 0 dB) yields a −1 dB output (relative to full-scale digital swing). The input voltage scales with V(VDACP) − V(VDACN); almost equal to VDDA, hence: [ V ( V DACP ) – V ( V DACN ) ] V I (0 dB) = ----------------------------------------------------------------------- V (RMS value) 5 13. Device measured with external components as shown in recommended application diagram (see Fig.7). 1995 Apr 24 11 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 14. Typical values are for 18-bit performance, minimum and/or maximum values are for 16-bit performance. 15. This is the ratio (in dB) of the digital output amplitude of single tone, in one channel, to the digital output amplitude of the same tone in the measurement channel. This definition presupposes that the channels have the same gain. (55.5 ± 1) 16. Group delay = ------------------------- , where fs is the output sampling frequency. Typical value given is for fs = 44.1 kHz. fs handbook, full pagewidth SCKO/SCKI SWSO/SWSI SDO L MSB R MSB - 1 LSB 0 MSB MSB - 1 I2 S FORMAT SCKO/SCKI SWSO/SWSI SDO L MSB MSB - 1 R LSB 0 MSB MSB - 1 FORMAT 1 SCKO/SCKI SWSO/SWSI SDO L MSB MSB - 1 R LSB 0 MSB MSB - 1 MLA716 - 1 FORMAT 2 Fig.3 Output interface modes. 1995 Apr 24 12 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 clock period TDCK handbook, full pagewidth VDD DCKO tH tL tr 1V 1.0 V tf td VDD 1V DIOL and DIOR 1.0 V MLA717 Fig.4 One bit code output timing. clock period TDCK handbook, full pagewidth tH tL tr VDD 1V DCKO 1.0 V tf t su th VDD 1V DIOL and DIOR 1.0 V MLA718 Fig.5 One bit code input timing. 1995 Apr 24 13 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 clock period TSCK handbook, full pagewidth t LC t HC 2.0 V SCKO/SCKI 0.8 V t hr t sr 2.0 V SWSO/SWSI or SDO 0.8 V MLA719 Fig.6 Serial output timing. 1995 Apr 24 14 100 pF 150 Ω 5V 10 kΩ 270 Ω 330 kΩ 100 kΩ 47 µF 13 kΩ 47 µF 10 270 kΩ Ω 620 kΩ 68 pF 68 pF 150 Ω 150 Ω 100 pF 47 nF 10 kΩ 33 32 31 PINL NINL BAOL 10 kΩ 30 BAIL 29 V DACP 28 27 VDACN I ref 26 BAIR 25 24 23 BAOR NINR PINR 34 BBOL 35 VrefL VrefR 22 21 47 µF 47 µF 47 nF 47 nF SAA7360 36 5V 47 µF VDDA VDDAT 47 nF 37 100 kΩ 43 VSSA VSSAT SWSO SDO RESET 2.2 µF VSSD VDDD 4 XIN 5 47 nF 6 100 kΩ 7 SCKO 20 VDDA 47 µF 19 47 nF 14 12 11 to serial interface receiver MLA720 - 2 4.7 Ω 11.2896 MHz 33 pF 47 µF 5V Product specification Fig.7 Application diagram. 15 pF SAA7360 Pins 1 to 3, 8 to 10, 13, 15 to 18, 38 to 42 and 44 are not connected. XOUT handbook, full pagewidth 15 4.7 Ω 5V BBOR Philips Semiconductors 47 µF Bitstream conversion ADC for digital audio systems VI (R) 100 kΩ 150 Ω APPLICATION INFORMATION 1995 Apr 24 VI (L) Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm SOT205-1 c y X 33 A 23 34 22 ZE e E HE A A2 (A 3) A1 wM θ bp Lp pin 1 index 44 L 12 detail X 1 11 ZD e v M A wM bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.60 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 14.1 13.9 1 19.2 18.2 19.2 18.2 2.35 2.0 1.2 0.3 0.15 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC SOT205-1 133E01A 1995 Apr 24 JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 16 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. SOLDERING Plastic quad flat packages Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C. BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.) A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Apr 24 17 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 NOTES 1995 Apr 24 18 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7360 NOTES 1995 Apr 24 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. 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(02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD MD, EINDHOVEN, EINDHOVEN, The The Netherlands, Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD38 © Philips Electronics N.V. 1995 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 513061/1500/03/pp20 Document order number: Date of release: 1995 Apr 24 9397 750 00081