DISCRETE SEMICONDUCTORS DATA SHEET PHN708 7 N-channel 80 mΩ FET array enhancement mode MOS transistors Product specification Supersedes data of 1997 Jun 19 File under Discrete Semiconductors, SC13 1998 Mar 17 Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors FEATURES PHN708 PINNING - SOT340-1 (SSOP24) • High-speed switching • No secondary breakdown PIN SYMBOL 1 and 4 d1 drain 1 2 s1 source 1 3 g1 gate 1 5 and 8 d2 drain 2 6 s2 source 2 7 g2 gate 2 9 and 12 d3 drain 3 • Very low on-state resistance. APPLICATIONS • Driving high performance three phase brushless DC motors. DESCRIPTION DESCRIPTION 10 s3 source 3 Seven enhancement mode MOS transistors in a 24-pin plastic SOT340-1 (SSOP24) package. Six of the transistors are in three half-bridge configurations. 11 g3 gate 3 13 g4 gate 4 CAUTION 14 s4 source 4 15, 17, 18, 20, 21, 23, 24 d4 drain 4 16 g5 gate 5 19 g6 gate 6 22 g7 gate 7 The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. d4 handbook, full pagewidth 24 13 g7 g6 g5 d1 g1 1 d2 g2 d3 s4 g3 12 s1 s2 Fig.1 Simplified outline and symbol. 1998 Mar 17 g4 2 s3 MAM275 Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors PHN708 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage (DC) − 30 V VGS gate-source voltage (DC) − ±20 V VGSth gate-source threshold voltage ID = 1 mA; VDS = VGS 1 2.8 V ID drain current (DC) Ts = 80 °C − 3.1 A RDSon drain-source on-state resistance ID = 1.5 A; VGS = 10 V − 80 mΩ Ptot total power dissipation Ts = 80 °C − 1.3 W LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per FET VDS drain-source voltage (DC) − 30 V VGS gate-source voltage (DC) − ±20 V ID drain current (DC) Ts = 80 °C; note 1 − 3.1 A IDM peak drain current note 2 − 12.4 A Ptot total power dissipation Ts = 80 °C; note 3 − 1.3 W Ts = 80 °C; note 4 − 1.13 W Ts = 80 °C; note 5 − 0.92 W Ts = 80 °C; note 6 − 0.77 W Tstg storage temperature −55 +150 °C Tj operating junction temperature −55 +150 °C Source-drain diode IS source current (DC) Ts = 80 °C − 1.3 A ISM peak source current note 2 − 5.2 A Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. When only one FET dissipates. 4. When either combination of FETs 1-5, 1-6, 2-5, 2-7, 3-6 or 3-7 dissipate an equal amount of power. 5. When FET four plus either combination of FETs 1-5, 1-6, 2-5, 2-7, 3-6 or 3-7 dissipate an equal amount of power. 6. When all seven FETs dissipate an equal amount of power. 1998 Mar 17 3 Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors PHN708 MDA787 2 MDA788 10 2 handbook, halfpage handbook, halfpage Ptot ID (A) (W) 1.6 (1) 10 tp = 100 µs 1.2 1 ms 1 10 ms 0.8 tp δ= T P 10 0.4 1 100 ms DC t tp T 0 0 50 100 150 Ts (°C) 10 200 2 10 1 1 10 VDS (V) 10 2 δ = 0.01; Ts = 80 °C. (1) RDSon limitation. Fig.2 Power derating curve. Fig.3 SOAR. THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT note 1 53 K/W note 2 62 K/W note 3 76 K/W note 4 91 K/W Per FET Rth j-s thermal resistance from junction to soldering point Notes 1. When only one FET dissipates. 2. When either combination of FETs 1-5, 1-6, 2-5, 2-7, 3-6 or 3-7 dissipate an equal amount of power. 3. When FET four plus either combination of FETs 1-5, 1-6, 2-5, 2-7, 3-6 or 3-7 dissipate an equal amount of power. 4. When all seven FETs dissipate an equal amount of power. 1998 Mar 17 4 Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors PHN708 CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per FET V(BR)DSS drain-source breakdown voltage VGS = 0; ID = 10 µA 30 − − V VGSth gate-source threshold voltage VGS = VDS ; ID = 1 mA 1 − 2.8 V IDSS drain-source leakage current VGS = 0; VDS = 24 V − − 100 nA IGSS gate leakage current VGS = ±20 V; VDS = 0 − − ±100 nA RDSon drain-source on-state resistance VGS = 4.5 V; ID = 0.75 A − − 130 mΩ VGS = 10 V; ID = 1.5 A − − 80 mΩ Ciss input capacitance VGS = 0; VDS = 24 V; f = 1 MHz − 180 − pF Coss output capacitance VGS = 0; VDS = 24 V; f = 1 MHz − 70 − pF Crss reverse transfer capacitance VGS = 0; VDS = 24 V; f = 1 MHz − 36 − pF QG total gate charge VGS = 10 V; VDD = 15 V; ID = 1 A − 5.4 8 nC QGS gate-source charge VDD = 15 V; ID = 1 A − 0.4 − nC QGD gate-drain charge VDD = 15 V; ID = 1 A − 1.6 − nC Switching times td(on) turn-on delay time VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 3 − ns tf fall time VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 2.5 − ns ton turn-on switching time VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 5.5 10 ns td(off) turn-off delay time VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 10 − ns tr rise time VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 6 − ns toff turn-off switching time VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 16 25 ns Source-drain diode VSD source-drain diode forward voltage VGD = 0; IS = 1.25 A − − 1 V trr reverse recovery time IS = 1.25 A; di/dt = −100 A/µs − 25 − ns 1998 Mar 17 5 Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors handbook, full pagewidth PHN708 VDD 90 % Vin RL 10 % 0 Vout 90 % Vout Vin 10 % 0 td(off) td(on) tf MAM274 tr ton toff Fig.4 Switching times test circuit with input and output waveforms. 102 handbook, full pagewidth MDA786 Rth j−s (K/W) δ= 1 0.75 0.5 0.33 10 0.2 0.1 0.05 0.02 1 tp δ= T P 0.01 0 t tp T 10−1 10−6 10−5 10−4 10−3 10−2 10−1 tp (s) 1 Fig.5 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values. 1998 Mar 17 6 Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors PHN708 MDA792 10 MDA790 16 handbook, halfpage handbook, halfpage VGS ID (A) (V) 8 (1) (2) (3) (4) 12 6 (5) 8 (6) 4 (7) 4 2 (8) (9) 0 0 0 2 4 QG (nC) 6 0 2 4 6 Tamb = 25 °C; tp = 80 µs; δ = 0. (1) (2) (3) (4) VDD = 15 V; ID = 1 A; Tamb = 25 °C. Fig.6 Gate-source voltage as a function of total gate charge; typical values. MDA791 16 (5) (6) (7) (8) (9) VGS = 10 V. VGS = 7.5 V. VGS = 6 V. VGS = 5 V. Fig.7 8 10 VDS (V) VGS = 4.5 V. VGS = 4 V. VGS = 3.5 V. VGS = 3 V. VGS = 2.5 V. Output characteristics; typical values. MDA789 400 handbook, halfpage handbook, halfpage ID (A) C (pF) 12 300 8 200 4 100 Ciss Coss Crss 0 0 0 2 4 VGS (V) 6 0 5 10 15 20 25 VDS (V) VGS = 0 ; f = 1 MHz; Tj = 25 °C. VDS = 10 V; Tamb = 25 °C; tp = 80 µs; δ = 0. Fig.9 Fig.8 Transfer characteristic; typical values. 1998 Mar 17 7 Capacitance as a function of drain-source voltage; typical values. Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors PHN708 MDA793 8 MDA794 10 handbook, halfpage handbook, halfpage IS (A) RDSon (Ω) (1)(2)(3)(4)(5)(6)(7)(8) 6 (1) (2) (3) 1 4 10−1 2 10−2 0 0 0.4 0.8 VSD (V) 1.2 0 2 4 6 8 10 VGS (V) Tamb = 25 °C; tp = 300 µs; δ = 0. ID = 0.3 A. ID = 0.75 A. ID = 1.5 A. ID = 3.1 A. (5) ID = 5 A. (6) ID = 7.5 A. (7) ID = 10 A. (8) ID = 12.4 A. tp = 300 µs; δ = 0. (1) Tamb = 150 °C. (2) Tamb = 25 °C. (3) Tamb = −65 °C. (1) (2) (3) (4) Fig.10 Source current as a function of source-drain diode forward voltage; typical values. Fig.11 Drain-source on-state resistance as a function of gate-source voltage; typical values. 1998 Mar 17 8 Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors PHN708 MDA795 1.2 MDA796 1.8 handbook, halfpage handbook, halfpage k k (1) 1.4 1 (2) 1 0.8 0.6 −75 −25 25 75 125 0.6 −75 175 Tj (°C) −25 25 75 125 175 Tj (°C) R DSon at T j k = ---------------------------------------R DSon at 25 °C V GSth at T j k = ------------------------------------V GSth at 25°C VGSth at VDS = VGS; ID = 1 mA. RDSon at: (1) VGS = 10 V; ID = 1.5 A. (2) VGS = 4.5 V; ID = 0.75 A. Fig.12 Temperature coefficient of gate-source threshold voltage as a function of junction temperature; typical values. Fig.13 Temperature coefficient of drain-source on-resistance as a function of junction temperature; typical values. 1998 Mar 17 9 Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors PHN708 PACKAGE OUTLINE SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT340-1 1998 Mar 17 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AG 10 o Philips Semiconductors Product specification 7 N-channel 80 mΩ FET array enhancement mode MOS transistors PHN708 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Mar 17 11 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 135108/00/03/pp12 Date of release: 1998 Mar 17 Document order number: 9397 750 03274