INTEGRATED CIRCUITS DATA SHEET PCF8573 Clock/calendar with Power Fail Detector Product specification Supersedes data of May 1989 File under Integrated Circuits, IC12 1997 Mar 28 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector CONTENTS FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 Oscillator Prescaler and time counter Alarm register Comparator Power on/power fail detection Interface level shifters 8 CHARACTERISTICS OF THE I2C-BUS 8.1 8.2 8.3 8.4 Bit transfer Start and stop conditions System configuration Acknowledge 9 I2C-BUS PROTOCOL 9.1 9.2 Addressing Clock/calendar READ/WRITE cycles 10 LIMITING VALUES 11 HANDLING 12 DC CHARACTERISTICS 13 AC CHARACTERISTICS 14 APPLICATION INFORMATION 15 PACKAGE OUTLINES 16 SOLDERING 16.1 16.2 16.2.1 16.2.2 16.3 16.3.1 16.3.2 16.3.3 Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints 17 DEFINITIONS 18 LIFE SUPPORT APPLICATIONS 19 PURCHASE OF PHILIPS I2C COMPONENTS 1997 Mar 28 2 PCF8573 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector 1 FEATURES • Serial input/output days and months 2 I2C-bus interface for minutes, hours, PCF8573 GENERAL DESCRIPTION The PCF8573 is a low threshold, CMOS circuit that functions as a real time clock/calendar. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. • Additional pulse outputs for seconds and minutes • Alarm register for presetting a time for alarm or remote switching functions The IC incorporates an addressable time counter and an addressable alarm register for minutes, hours, days and months. Three special control/status flags, COMP, POWF and NODA, are also available. Back-up for the clock during supply interruptions is provided by a 1.2 V nickel cadmium battery. The time base is generated from a 32.768 kHz crystal-controlled oscillator. • On-chip power fail detector • Separate ground pin for the clock allows easy implementation of battery back-up during supply interruption • Crystal oscillator control (32.768 kHz) • Low power consumption. 3 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD − VSS1 supply voltage, clock (pin 16 to pin 15) 1.1 − 6.0 V VDD − VSS2 supply voltage, I2C-bus (pin 16 to pin 8) 2.5 − 6.0 V fosc crystal oscillator frequency − 32.768 − kHz 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCF8573P DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 PCF8573T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 1997 Mar 28 3 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector 5 PCF8573 BLOCK DIAGRAM Fig.1 Block diagram. 6 PINNING SYMBOL PIN DESCRIPTION A0 1 address input A1 2 address input COMP 3 comparator output SDA 4 serial data line; I2C-bus SCL 5 serial clock line; I2C-bus EXTPF 6 enable power fail flag input PFIN 7 power fail flag input VSS2 8 negative supply 2 (I2C interface) MIN 9 one pulse per minute output SEC 10 one pulse per second output FSET 11 oscillator tuning output TEST 12 test input; connect to VSS2 if not in use OSCI 13 oscillator input OSCO 14 oscillator input/output VSS1 15 negative supply 1 (clock) VDD 16 common positive supply 1997 Mar 28 Fig.2 Pinning diagram. 4 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector 7 7.3 FUNCTIONAL DESCRIPTION 7.1 The PCF8573 has an integrated crystal-controlled oscillator which provides the timebase for the prescaler. The frequency is determined by a single 32.76 kHz crystal connected between OSCI and OSCO. A trimmer is connected between OSCI and VDD. 7.4 Comparator The comparator compares the contents of the alarm register and the time counter, each with a length of 24 bits. When these contents are equal the flag COMP will be set 4 ms after the falling edge of MIN. This set condition occurs once at the beginning of each minute. This information is latched, but can be cleared by an instruction via the I2C-bus. A clear instruction may be transmitted immediately after the flag is set and will be executed. Flag COMP information is also available at the output COMP. The comparison may be based upon hours and minutes only if the internal flag NODA (no date) is set. Flag NODA can be set and cleared by separate instructions via the I2C-bus, but it is undefined until the first set or clear instruction has been received. Both COMP and NODA flags are readable via the I2C-bus. Prescaler and time counter The prescaler provides a 128 Hz signal at the FSET output for fine adjustment of the crystal oscillator without loading it. The prescaler also generates a pulse once a second to advance the seconds counter. The carry of the prescaler and the seconds counter are available at the outputs SEC, MIN respectively, and are also readable via the I2C-bus. The mark-to-space ratio of both signals is 1 : 1. The time counter is advanced one count by the falling edge of output signal MIN. A transition from HIGH-to-LOW of output signal SEC triggers MIN to change state. The time counter counts minutes, hours, days and months, and provides a full calendar function which needs to be corrected only once every four years - to allow for leap-year. Cycle lengths are shown in Table 1. Table 1 Alarm register The alarm register is a 24-bit memory. It stores the time-point for the next setting of the status flag COMP. Details of writing and reading of the alarm register are included in the description of the characteristics of the I2C-bus. Oscillator 7.2 PCF8573 Cycle length of the time counter UNIT NUMBER OF BITS COUNTING CYCLE CARRY FOR FOLLOWING UNIT minutes 7 00 to 59 59 → 00 hours 6 00 to 23 23 → 00 days(1) 6 01 to 28 28 → 01 months 5 CONTENT OF MONTH COUNTER 2 (note 1) or 29 → 01 2 (note 1) 01 to 30 30 → 01 4, 6, 9, 11 01 to 31 31 → 01 1, 3, 5, 7, 8, 10, 12 01 to 12 12 → 01 Note 1. During February of a leap-year the ‘Time Counter Days’ may be set to 29 by directly writing into it using the ‘execute address’ function. Leap-years must be tracked by the system software. 1997 Mar 28 5 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector 7.5 The external power fail control operates by absence of the VDD − VSS2 supply. Therefore the input levels applied to PFIN and EXTPF must be within the range of VDD−VSS1. A LOW level at PFIN indicates a power fail. POWF is readable via the I2C-bus. A power-on reset for the I2C-bus control is generated on-chip when the supply voltage VDD − VSS2 is less than VTH2. Power on/power fail detection If the voltage VDD − VSS1 falls below a certain value the operation of the clock becomes undefined. Thus a warning signal is required to indicate that faultless operation of the clock is not guaranteed. This information is latched in a flag called POWF (Power Fail) and remains latched after restoration of the correct supply voltage until a write procedure with EXECUTE ADDRESS has been received. The flag POWF can be set by an internally generated power fail level-discriminator signal for application with (VDD − VSS1) greater than VTH1, or by an externally generated power fail signal for application with (VDD − VSS1) less than VTH1. The external signal must be applied to the input PFIN. The input stage operates with signals of slow rise and fall times. Internally or externally controlled POWF can be selected by input EXTPF as shown in Table 2. Table 2 7.6 PFIN(1) 0 0 power fail is sensed internally 0 1 test mode 1 0 power fail is sensed externally 1 1 no power fail sensed FUNCTION Note 1. 0 = VSS1 (LOW); 1 = VDD (HIGH). 1997 Mar 28 Interface level shifters The level shifters adjust the 5 V operating voltage (VDD − VSS2) of the microcontroller to the internal supply voltage (VDD − VSS1) of the clock/calendar. The oscillator and counter are not influenced by the VDD − VSS2 supply voltage. If the voltage VDD − VSS2 is absent (VDD = VSS2) the output signal of the level shifter is HIGH because VDD is the common node of the VDD − VSS2 and the VDD − VSS1 supplies. Because the level shifters invert the input signals, the internal circuit behaves as if a LOW signal is present on the inputs. FSET, SEC, MIN and COMP are CMOS push-pull output stages. The driving capability of these outputs is lost when the supply voltage VDD − VSS2 = 0. Power fail selection EXTPF(1) PCF8573 6 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector 8 PCF8573 CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer (see Fig.3) One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. SDA SCL change of data allowed data line stable; data valid MBC621 Fig.3 Bit transfer. 8.2 Start and stop conditions (see Fig.4) Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). SDA SDA SCL SCL S P START condition STOP condition Fig.4 Definition of start and stop conditions. 1997 Mar 28 7 MBC622 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector 8.3 PCF8573 System configuration (see Fig.5) A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER SLAVE RECEIVER MASTER TRANSMITTER / RECEIVER MASTER TRANSMITTER MBA605 Fig.5 System configuration. 8.4 The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition, see Figs. 9 and 10. Acknowledge (see Fig.6) The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S START CONDITION MBC602 Fig.6 Acknowledgment on the I2C-bus. 1997 Mar 28 8 clock pulse for acknowledgement Philips Semiconductors Product specification Clock/calendar with Power Fail Detector 9 9.1 PCF8573 I2C-BUS PROTOCOL Addressing Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.7. Bits A0 and A1 correspond to the two hardware address pins A0 and A1. Connecting these to VDD or VSS allows the device to have 1 of 4 different addresses. Fig.7 Slave address. 9.2 Clock/calendar READ/WRITE cycles The I2C-bus configuration for different clock/calendar READ and WRITE cycles is shown in Figs 8, 9 and 10. The write cycle is used to set the time counter, the alarm register and the flags. The transmission of the clock/calendar address is followed by the MODE-POINTER-word which contains a CONTROL-nibble (Table 3) and an ADDRESS-nibble (Table 4). The ADDRESS-nibble is valid only if the preceding CONTROL-nibble is set to EXECUTE ADDRESS. The third transmitted word contains the data to be written into the time counter or alarm register. Fig.8 Master transmitter transmits to clock/calendar slave receiver. 1997 Mar 28 9 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 (1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. Fig.9 Master transmitter reads clock/calendar after setting mode pointer. (1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. Fig.10 Master reads clock/calendar immediately after first byte. 1997 Mar 28 10 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector Table 3 PCF8573 MODE-POINTER-word, CONTROL-nibble (bits 8, 7, 6 and 5) BIT 8 C2 C1 C0 FUNCTION 0 0 0 0 execute address 0 0 0 1 read control/status flags 0 0 1 0 reset prescaler, including seconds counter; without carry for minute counter 0 0 1 1 time adjust, with carry for minute counter (note 1) 0 1 0 0 reset NODA flag 0 1 0 1 set NODA flag 0 1 1 0 reset COMP flag Note 1. If the seconds counter is below 30 there is no carry. This causes a time adjustment of max. −30 s. From the count 30 there is a carry which adjusts the time by max. +30 s. Table 4 MODE-POINTER-word, ADDRESS-nibble (bits 4, 3, 2 and 1) BIT 4 B2 B1 B0 ADDRESSED TO: 0 0 0 0 time counter hours 0 0 0 1 time counter minutes 0 0 1 0 time counter days 0 0 1 1 time counter months 0 1 0 0 alarm register hours 0 1 0 1 alarm register minutes 0 1 1 0 alarm register days 0 1 1 1 alarm register months At the end of each data word the address bits B1, B0 will be incremented automatically provided the preceding CONTROL-nibble is set to EXECUTE ADDRESS. There is no carry to B2. Table 5 shows the placement of the BCD upper and lower digits in the DATA byte for writing into the addressed part of the time counter and alarm register respectively. Table 6 shows the acknowledgement response of the clock calendar as a slave receiver. Table 5 Placement of BCD digits in the DATA byte; note 1 MSB DATA LSB UPPER DIGIT LOWER DIGIT UD UC UB UA LD LC LB LA X X D D D D D D hours X D D D D D D D minutes X X D D D D D D days X X X D D D D D months Note 1. ‘X’ is the don’t care bit; ‘D’ is the data bit. 1997 Mar 28 11 ADDRESSED TO: Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 Acknowledgement response of the PCF8573 as slave-receiver is shown in Table 6. Note that data is only associated with the ‘execute address’ function where C0, C1, C2 = 0, 0, 0. Table 6 Slave receiver acknowledgement; note 1 MODE POINTER ACKNOWLEDGE ON BYTE: BIT 8 C2 C1 C0 BIT 4 B2 B1 B0 ADDRESS MODE POINTER DATA 0 0 0 0 0 X X X yes yes yes 0 0 0 0 1 X X X yes no no 0 0 0 1 X X X X yes yes no 0 0 1 0 X X X X yes yes no 0 0 1 1 X X X X yes yes no 0 1 0 0 X X X X yes yes no 0 1 0 1 X X X X yes yes no 0 1 1 0 X X X X yes yes no 0 1 1 1 X X X X yes no no 1 X X X X X X X yes no no Note 1. ‘X’ is ‘don’t care’. To read the addressed part of the time counter and alarm register, plus information from specified control/status flags, the BCD digits in the DATA byte are organized as shown in Table 7. The status of the CONTROL-nibble of the MODE-POINTER-WORD (C2, C1, C0) remains unchanged until re-written. Table 7 Organization of the BCD digits in the DATA byte; note 1 MSB DATA LSB UPPER DIGIT LOWER DIGIT UD UC UB UA LD LC LB LA 0 0 D D D D D D hours 0 D D D D D D D minutes 0 0 D D D D D D days 0 0 0 D D D D D months 0 0 0 m s NODA COMP POWF Note 1. ‘D’ is the data bit; ‘m’ = minutes; ‘s’ = seconds. 1997 Mar 28 12 ADDRESSED TO: control/status flags Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER VDD − VSS1 supply voltage (pin 16 to pin 15) −0.3 +8.0 V VDD − VSS2 supply voltage (pin 16 to pin 8) −0.3 +8.0 V Vl MIN. MAX. UNIT input voltage pins 4 and 5 (with input impedance of minimum 500 Ω) VSS2 − 0.8 VDD + 0.8 V pins 6, 7, 13 and 14 VSS1 − 0.6 VDD + 0.6 V any other pin VSS2 − 0.6 VDD + 0.6 V Il DC input current − 10 mA IO DC output current − 10 mA Ptot total power dissipation per package − 200 mW PO power dissipation per output − 100 mW Tamb operating ambient temperature −40 +85 °C Tstg storage temperature −55 +125 °C 11 HANDLING Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under “Handling MOS Devices”. 1997 Mar 28 13 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 12 DC CHARACTERISTICS VSS2 = 0 V; Tamb = −40 to + 85 °C unless otherwise specified. Typical values at Tamb = 25 °C. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNI T Supply VDD − VSS2 supply voltage (I2C interface) VDD − VSS1 supply voltage (clock) ISS1 ISS2 supply current at VSS1 (pin 15) supply current at VSS2 (pin 8) tHD; DAT ≥ 300 ns 2.5 5.0 6.0 V 1.1 1.5 VDD − VSS2 V see Fig.11 VDD − VSS1 = 1.5 V − −3 −10 µA VDD − VSS1 = 5 V − −12 −50 µA − − −50 µA VDD − VSS2 = 5 V; IO = 0 all outputs Input SCL, input/output SDA VIL LOW level input voltage − − 0.3VDD V VIH HIGH level input voltage 0.7VDD − − V ILI input leakage current Ci input capacitance VI = VSS2 or VDD −1 − +1 µA − − 7 pF Inputs A0, A1, TEST VIL LOW level input voltage − − 0.2VDD V VIH HIGH level input voltage 0.7VDD − − V ILI input leakage current −250 − +250 nA 0 − 0.2VDD − VSS1 V VI = VSS2 or VDD Inputs EXTPF, PFIN VIL LOW level input voltage VIH HIGH level input voltage ILI input leakage current 0.7VDD − VSS1 − − V VI = VSS1 to VDD −1.0 − +1.0 µA VI = VSS1 to VDD; Tamb = 25 °C −0.1 − +0.1 µA Output SDA (n channel open-drain) VOL LOW level output voltage output ON; IO = 3 mA; VDD − VSS2 = 2.5 to 6 V − − 0.4 V ILI input leakage current VDD − VSS2 = 6 V; VO = 6 V −1.0 − +1.0 µA VDD − VSS2 = 2.5 V; IO = 0.3 mA − − 0.4 V VDD − VSS2 = 4 to 6 V; IO = 1.6 mA − − 0.4 V VDD − VSS2 = 2.5 V; IO = −0.1 mA VDD − 0.4 − − V VDD − VSS2 = 4 to 6 V; IO = −0.5 mA VDD − 0.4 − − V Output SEC, MIN, COMP, FSET (normal buffer outputs) VOL VOH 1997 Mar 28 LOW level output voltage HIGH level output voltage 14 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector SYMBOL PARAMETER PCF8573 CONDITIONS MIN. TYP. MAX. UNI T Internal threshold voltages VTH1 Power failure detection 1 1.2 1.4 V VTH2 Power-on reset 1.5 2.0 2.5 V MGL072 −12 handbook, halfpage ISS1 (µA) −8 −4 0 0 2 4 VDD−VSS1 (V) 6 Fig.11 Typical supply current (ISS1) as a function of clock supply voltage (VDD − VSS1) at Tamb = −40 to +85 °C. 1997 Mar 28 15 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 13 AC CHARACTERISTICS VSS2 = 0 V; Tamb = −40 to +85 °C unless otherwise specified. Typical values at Tamb = +25 °C. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Rise and fall times of input signals tr tf rise time fall time input EXTPF − − 1 µs input PFIN − − ∞ µs all other inputs (levels between VIL and VIH) − − 1 µs input EXTPF − − 1 µs input PFIN − − ∞ µs all other inputs (levels between VIL and VIH) − − 0.3 µs − 40 − pF − 3 − MΩ − 2 × 10−7 − Oscillator Cosc integrated oscillator capacitance Rf oscillator feedback resistance ∆fosc oscillator stability ∆(VDD − VSS1) = 100 mV; Tamb = 25 °C; (VDD − VSS1) = 1.55 V Quartz crystal parameters (f = 32.768 kHz) Rs series resistance − − 40 kΩ CL parallel load capacitance − 10 − pF CT trimmer capacitance 5 − 25 pF I2C-bus timing (see Fig.12; notes 1 and 2) fSCL SCL clock frequency − − 100 kHz tSP tolerable spike width on bus − − 100 ns tBUF bus free time 4.7 − − µs tSU;STA START condition set-up time 4.7 − − µs tHD;STA START condition hold time 4.0 − − µs tLOW SCL LOW time 4.7 − − µs tHIGH SCL HIGH time 4.0 − − µs tr SCL and SDA rise time − − 1.0 µs tf SCL and SDA fall time − − 0.3 µs tSU;DAT data set-up time 250 − − ns tHD;DAT data hold time 0 − − ns tVD;DAT SCL LOW to data out valid − − 3.4 µs tSU;STO STOP condition set-up time 4.0 − − µs Notes 1. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and VIH with an input voltage swing of VSS to VDD. 2. A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to use it”. This brochure may be ordered using the code 9398 393 40011. 1997 Mar 28 16 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector handbook, full pagewidth t SU;STA BIT 6 (A6) BIT 7 MSB (A7) START CONDITION (S) PROTOCOL t LOW t HIGH PCF8573 BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / f SCL SCL t tr BUF tf SDA t HD;STA t SU;DAT t HD;DAT t VD;DAT MBD820 Fig.12 I2C-bus timing diagram; rise and fall times refer to VIL and VIH. 1997 Mar 28 17 t SU;STO Philips Semiconductors Product specification Clock/calendar with Power Fail Detector 14 APPLICATION INFORMATION Fig.13 Application example of the PCF8573 clock/calendar with battery backup. Fig.14 Application example of the PCF8573 with common VSS1 and VSS2 supply. 1997 Mar 28 18 PCF8573 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 15 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 2.2 inches 0.19 0.020 0.15 0.055 0.045 0.021 0.015 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT38-1 050G09 MO-001AE 1997 Mar 28 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-10-02 95-01-19 19 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c HE y v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.41 0.40 0.30 0.29 0.050 0.42 0.39 0.055 0.043 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 inches 0.10 Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT162-1 075E03 MS-013AA 1997 Mar 28 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-24 20 o 8 0o Philips Semiconductors Product specification Clock/calendar with Power Fail Detector Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. 16 SOLDERING 16.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 16.3.2 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 16.2 16.2.1 • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 16.3 16.3.1 16.3.3 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1997 Mar 28 WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. 16.2.2 PCF8573 21 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 17 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Mar 28 22 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector NOTES 1997 Mar 28 23 PCF8573 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 417067/1200/03/pp24 Date of release: 1997 Mar 28 Document order number: 9397 750 01674