PHILIPS PHKD3NQ10T

Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
FEATURES
SYMBOL
• Dual device
• Low on-state resistance
• Fast switching
• Low profile surface mount
package
QUICK REFERENCE DATA
d1
d2
VDS = 100 V
ID = 3 A
g1
RDS(ON) ≤ 90 mΩ (VGS = 10 V)
g2
s1
GENERAL DESCRIPTION
PHKD3NQ10T
s2
PINNING
Dual N-channel enhancement
mode field-effect transistor in a
plastic envelope using ’trench’
technology.
Applications:• Motor and relay drivers
• d.c. to d.c. converters
The PHKD3NQ10T is supplied in
the SOT96-1 (SO8) surface
mounting package.
PIN
SOT96-1
DESCRIPTION
1
source 1
2
gate 1
3
source 2
4
gate 2
5,6
drain 2
7,8
drain 1
pin 1 index
8
7
6
5
1
2
3
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
VDS
VDGR
Continuous drain-source voltage
Drain-gate voltage
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C;
RGS = 20 kΩ
VGS
ID
Gate-source voltage
Drain current per MOSFET
MIN.
MAX.
UNIT
-
100
100
V
V
-
± 20
3
2.4
2.2
1.7
12
V
A
A
A
A
A
- 65
2
1.3
150
W
W
˚C
Ta = 25 ˚C, t ≤ 10 s
Ta = 70 ˚C, t ≤ 10 s
Drain current per MOSFET (both
Ta = 25 ˚C, t ≤ 10 s
MOSFETs conducting)
Ta = 70 ˚C, t ≤ 10 s
Drain current (pulse peak value per Ta = 25 ˚C
MOSFET)
Total power dissipation
Ta = 25 ˚C, t ≤ 10 s
Ta = 70 ˚C, t ≤ 10 s
Storage & operating temperature
ID
IDM
Ptot
Tstg, Tj
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
Rth j-a
Surface mounted on FR4 board, t ≤ 10
sec; either or both MOSFETs conducting
Surface mounted on FR4 board; either or
both MOSFETs conducting
Rth j-a
Thermal resistance junction
to ambient
Thermal resistance junction
to ambient
August 1999
1
TYP.
MAX.
UNIT
-
62.5
K/W
150
-
K/W
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
ELECTRICAL CHARACTERISTICS
Tj= 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
CONDITIONS
MIN.
VGS = 0 V; ID = 250 µA;
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
RDS(ON)
IGSS
IDSS
Drain-source on-state
VGS = 10 V; ID = 1.5 A
resistance
Gate source leakage current VGS = ±20 V; VDS = 0 V
Zero gate voltage drain
VDS = 100 V; VGS = 0 V;
current
Tj = 150˚C
Tj = 150˚C
100
89
2
1.1
-
TYP. MAX. UNIT
3
70
10
0.05
-
4
6
90
216
100
10
100
V
V
V
V
V
mΩ
mΩ
nA
µA
µA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 3 A; VDD = 80 V; VGS = 10 V
-
21
2.5
8
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 50 V; RD = 15 Ω;
VGS = 10 V; RG = 5.6 Ω
Resistive load
-
6
12
20
10
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
-
2.5
5
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
-
633
103
61
-
pF
pF
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
IS
Ta = 25 ˚C, t ≤ 10 s
-
-
2
A
ISM
VSD
Continuous source diode
current
Pulsed source diode current
Diode forward voltage
IF = 2 A; VGS = 0 V
-
0.8
12
1.2
A
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 2 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
55
135
-
ns
nC
August 1999
MIN.
2
TYP. MAX. UNIT
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Normalised Power Derating, PD (%)
Transient thermal impedance, Zth j-a (K/W)
100
100
D = 0.5
90
80
0.2
10
0.1
70
0.05
60
0.02
1
50
single pulse
40
30
P
D
D = tp/T
tp
0.1
20
T
10
0.01
1E-06
0
0
25
50
75
100
Ambient temperature, Ta (C)
125
150
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Ta)
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
Drain Current, ID (A)
6
Normalised Current Derating, ID (%)
100
VGS = 10V
90
8V
5
80
5.4 V
Tj = 25 C
6V
70
5.2 V
5V
4
60
4.8 V
3
50
40
4.6 V
2
30
20
4.4 V
1
10
0
0
25
50
75
100
Ambient temperature, Ta (C)
125
0
150
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Ta); VGS ≥ 10 V
100
0.2
0.4
0.2
4.6V
4.8V
2
5V
0.16
100 us
0.14
1 ms
0.12
1
5.2 V
5.4 V
0.1
10 ms
D.C.
1.8
Drain-Source On Resistance, RDS(on) (Ohms)
0.18
tp = 10 us
10
1.6
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
6V
0.08
100 ms
8V
0.06
0.1
VGS = 10V
0.04
0.02
0.01
Tj = 25 C
0
0.1
1
10
100
Drain-Source Voltage, VDS (V)
1000
0
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
August 1999
1
2
3
4
Drain Current, ID (A)
5
6
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
3
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Drain current, ID (A)
4.5
6
VDS > ID X RDS(ON)
Threshold Voltage, VGS(TO) (V)
4
5
maximum
3.5
typical
3
4
2.5
3
minimum
2
150 C
1.5
2
Tj = 25 C
1
1
0.5
0
0
0
1
2
3
4
5
6
-60
-40
-20
Gate-source voltage, VGS (V)
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
Drain current, ID (A)
1.0E-01
VDS > ID X RDS(ON)
1.0E-02
Tj = 25 C
minimum
1.0E-03
150 C
typical
1.0E-04
maximum
1.0E-05
1.0E-06
0
1
2
3
4
Drain current, ID (A)
5
0
6
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
0.5
1
1.5
2
2.5
3
3.5
Gate-source voltage, VGS (V)
4
4.5
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
10000
Capacitances, Ciss, Coss, Crss (pF)
Ciss
1000
Coss
100
Crss
10
-60
-40
-20
0
20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
0.1
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
August 1999
1
10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
4
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Source-Drain Diode Current, IF (A)
6
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VGS = 0 V
ID = 3A
5
Tj = 25 C
4
VDD = 20 V
150 C
3
VDD = 80 V
Tj = 25 C
2
1
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Gate charge, QG (nC)
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
August 1999
0.1
5
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
A1
A2
mm
inches
UNIT
A3
bp
c
D (1)
E (2)
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
e
HE
4.0
3.8
1.27
6.2
5.8
0.16
0.15
0.050
L
Lp
Q
1.05
1.0
0.4
0.7
0.6
0.244
0.039 0.028
0.041
0.228
0.016 0.024
v
w
y
Z (1)
0.25
0.25
0.1
0.7
0.3
0.01
0.01
0.004
0.028
0.012
θ
o
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03S
MS-012AA
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
Fig.15. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
7
Rev 1.000