INTEGRATED CIRCUITS 74F50109 Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics Product specification IC15 Data Handbook 1990 Sep 14 Philips Semiconductors Product specification Synchronizing dual J–K positive edge-triggered flip-flop with metastable immune characteristics FEATURE 74F50109 PIN CONFIGURATION • Metastable immune characteristics • Output skew guaranteed less than 1.5ns • High source current (IOH = 15mA) ideal for clock driver 1 16 VCC J0 2 15 RD1 K0 3 14 RD0 applications • Pinout compatible with 74F109 • See 74F5074 for synchronizing dual D-type flip-flop • See 74F50728 for synchronizing cascaded D-type flip-flop • See 74F50729 for synchronizing dual D-type flip-flop with 13 K1 SD0 5 12 CP1 Q0 6 11 SD1 Q0 7 10 Q1 GND 8 edge-triggered set and reset J1 CP0 4 9 Q1 SF00598 TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT( TOTAL) 74F50109 150MHz 22mA LOGIC SYMBOL 2 14 ORDERING INFORMATION ORDER CODE COMMERCIAL RANGE VCC = 5V ±10%, DESCRIPTION PKG DWG # Tamb = 0°C to +70°C 4 CP0 J0 5 SD0 1 RD0 12 CP1 16–pin plastic DIP N74F50109N SOT38-4 11 SD1 16–pin plastic SO N74F50109D SOT109-1 15 RD1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 6 74F (U.L.) HIGH/ LOW LOAD VALUE HIGH/LOW J inputs 1.0/0.417 20µA/250µA K0, K1 K inputs 1.0/0.417 20µA/250µA Clock inputs (active rising edge) 1.0/0.033 20µA/20µA Set inputs (active low) 1.0/0.033 Reset inputs (active low) 1.0/0.033 SD0, SD1 RD0, RD1 K0 K1 Q0 Q0 Q1 Q1 VCC = Pin 16 GND = Pin 8 J0, J1 CP0, CP1 J1 3 13 7 10 9 SF00599 IEC/IEEE SYMBOL 2 1J 4 3 20µA/20µA 1 5 20µA/20µA 14 Q0, Q1, Q0, Q1 Data outputs 750/33 15mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. 6 C1 1K S 2J 12 13 15 11 7 R 10 C2 2K 9 R S SF00600 September 14, 1990 2 853-1388 00422 Philips Semiconductors Product specification Synchronizing dual J–K positive edge-triggered flip-flop with metastable immune characteristics device–under–test can be often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build a waveform.0 An experiment was run by continuously operating the devices in the region where metastability will occur. LOGIC DIAGRAM Q 7, 9 6, 10 74F50109 Q When the device–under–test is a 74F74 (which was not designed with metastable immune characteristics) the waveform will appear as in Fig. 2. K J CP SD RD Fig. 2 shows clearly that the Q output can vary in time with respect to the Q trigger point. This also implies that the Q or Q output waveshapes may be distorted. This can be verified on an analog scope with a charge plate CRT. Perhaps of even greater interest are the dots running along the 3.5V volt line in the upper right hand quadrant. These show that the Q output did not change state even though the Q output glitched to at least 1.5 volts, the trigger point of the scope. 3, 13 2, 14 4, 12 5, 11 1, 15 VCC = Pin 16 GND = Pin 8 When the device–under–test is a metastable immune part, such as the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q output will appear as in Fig. 3. The 74F5074 Q output will not vary with respect to the Q trigger point even when the a part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flop the only outward manifestation of the event will be an increased clock–to–Q/Q propagation delay. This propagation delay is, of course, a function of the metastability characteristics of the part defined by τ and T0. SF00601 DESCRIPTION The 74F50109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. The metastability characteristics of the 74F5074 and related part types represent state–of–the–art TTL technology. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. After determining the T0 and t of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74F50729 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74F50109 10 nanoseconds after the clock edge. He simply plugs his number into the equation below: The J and K are edge–triggered inputs which control the state changes of the flip–flops as described in the function table. The J and K inputs must be stable just one setup time prior to the low–to–high transition of the clock for guaranteed propagation delays. The JK design allows operation as a D flip–flop by tying J and K inputs together. The 74F50109 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50109 are: τ ≅ 135ps and τ ≅ 9.8 X 106 sec where τ represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state. MTBF = e(t’/t)/ TofCfI In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t’ is the time after the clock pulse that the output is sampled (t’ < h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying fI by fC gives an answer of 1015 Hz2. From Fig. 4 it is clear that the MTBF is greater than 1010 seconds. Using the above formula MTBF is 1.51 X 1010 seconds or about 480 years. METASTABLE IMMUNE CHARACTERISTICS Philips Semiconductors uses the term ’metastable immune’ to describe characteristics of some of the products in its FAST family. Specifically the 74F50XXX family presently consist of 4 products which displays metastable immune characteristics. This term means that the outputs will not glitch or display an output anomaly under any circumstances including setup and hold time violations. SIGNAL GENERATOR Q TRIGGER DIGITAL SCOPE SIGNAL GENERATOR CP Q INPUT SF00586 This claim is easily verified on the 74F5074. By running two independent signal generators (see Fig. 1) at nearly the same frequency (in this case 10MHz clock and 10.02 MHz data) the September 14, 1990 D Figure 1. Test setup 3 Philips Semiconductors Product specification Synchronizing dual J–K positive edge-triggered flip-flop with metastable immune characteristics 74F50109 COMPARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS 4 3 2 1 0 Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive SF00602 Figure 2. 74F74 Q output triggered by Q output, Setup and Hold times violated 3 2 1 0 Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive SF00588 Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated September 14, 1990 4 Philips Semiconductors Product specification Synchronizing dual J–K positive edge-triggered flip-flop with metastable immune characteristics 74F50109 MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’ 106 108 1010 1012 1014 1012 1015 = fCfI 1011 10,000 years 1010 100 years 109 MTBF in seconds 108 one year 107 106 one week 7 8 9 10 t’ in nanoseconds SF00589 NOTE: VCC = 5V, Tamb = 25°C, τ =135ps, To = 9.8 X 108 sec Figure 4. TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERATURES Tamb = 0°C Tamb = 25°C Tamb = 70°C VCC τ T0 τ T0 τ T0 5.5V 125ps 1.0 X 109 sec 138ps 5.4 X 106 sec 160ps 1.7 X 105 sec 5.0V 115ps 1.3 X 1010 sec 135ps 9.8 X 106 sec 167ps 3.9 X 104 sec 4.5V 115ps 3.4 X 1013 sec 132ps 5.1 X 108 sec 175ps 7.3 X 104 sec FUNCTION TABLE INPUTS OUTPUTS SD RD CP J K Q Q MODE L H X X X H L Asynchronous set H L X X X L H Asynchronous reset L L X X X H H Undetermined* H H ↑ X X q q Hold H H ↑ h l q q Toggle H H ↑ h h H L Load ”1” (set) H H ↑ l l L H Load ”0” (reset) H H ↑ l h q q Hold ’no change” September 14, 1990 NOTES: H = High–voltage level h = High–voltage level one setup time prior to low–to–high clock transition L = Low–voltage level l = Low–voltage level one setup time prior to low–to–high clock transition q = Lower case indicate the state of the referenced output prior to the low–to–high clock transition X = Don’t care ↑ = Low–to–high clock transition ↑ = Not low–to–high clock transition * = Both outputs will be high if both SD and RD go low simultaneously OPERATING 5 Philips Semiconductors Product specification Synchronizing dual J–K positive edge-triggered flip-flop with metastable immune characteristics 74F50109 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state 40 mA Tamb Operating free air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 V VIH High–level input voltage 2.0 VIL Low–level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current –1 mA IOL Low–level output current 20 mA Tamb Operating free air temperature range +70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST LIMITS CONDITIONS1 VOH VOL High–level output voltage VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, Low–level output voltage VIH = MIN IOH = MAX IOL = MAX MIN ±10%VCC 2.5 ±5%VCC 2.7 TYP2 UNIT MAX V 3.4 V ±10%VCC 0.30 0.50 V ±5%VCC 0.30 0.50 V -0.73 -1.2 V VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA IIH High–level input current VCC = MAX, VI = 2.7V 20 µA IIL Low–level input current Jn, Kn VCC = MAX, VI = 0.5V -250 µA CPn, SDn, RDn VCC = MAX, VI = 0.5V -20 µA -150 mA IOS Short circuit output current3 VCC = MAX -60 ICC Supply current4 (total) VCC = MAX 22 32 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn. September 14, 1990 6 Philips Semiconductors Product specification Synchronizing dual J–K positive edge-triggered flip-flop with metastable immune characteristics 74F50109 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω VCC = +5.0V CL = 50pF, RL = 500Ω MIN TYP MAX MIN UNIT MAX fmax Maximum clock frequency Waveform 1 130 150 tPLH tPHL Propagation delay CPn to Qn or Qn Waveform 1 2.0 2.0 3.8 3.8 6.0 6.0 2.0 2.0 90 6.5 6.5 ns tPLH tPHL Propagation delay SDn, RDn to Qn or Qn Waveform 2 3.5 3.5 5.5 5.5 8.0 8.0 3.0 3.0 8.5 8.5 ns 1.5 ns tsk(o) Output skew1, 2 Waveform 4 1.5 NOTES: 1. | tPN actual – tPM actual| for any output compared to any other output where N and M are either LH or HL. 2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.,). ns AC SETUP REQUIREMENTS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500Ω MIN tsu (H) tsu(L) Setup time, high or low Jn, Kn to CPn th (H) th (L) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 1 1.5 1.5 2.0 2.0 ns Hold time, high or low Jn, Kn to CPn Waveform 1 1.0 1.0 1.5 1.5 ns tw (H) tw (L) CPn pulse width, high or low Waveform 1 3.0 4.0 3.5 5.0 ns tw (L) SDn or RDn pulse width, low Waveform 2 3.5 4.0 ns trec Recovery time SDn or RDn to CP Waveform 3 3.0 3.5 ns September 14, 1990 7 Philips Semiconductors Product specification Synchronizing dual J–K positive edge-triggered flip-flop with metastable immune characteristics 74F50109 AC WAVEFORMS Jn, Kn VM tsu(L) VM VM VM tsu(H) th(L) tw(L) SDn VM VM th(H) 1/fmax tw(L) RDn CPn VM VM VM VM tw(H) tPHL tPLH tw(L) tPLH tPHL Qn Qn VM VM VM VM VM tPLH tPHL tPLH tPHL VM VM Qn VM VM Qn SF00050 SF00139 Waveform 2. Propagation delay for set and reset to output, set and reset pulse width Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency VM Qn, Qn SDn or RDn tsk(o) VM Qn, Qn trec VM VM CPn SF00590 Waveform 4. Output skew SF00603 Waveform 3. Recovery time for set or reset to output NOTES: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUIT AND WAVEFORM VCC NEGATIVE PULSE VIN tw 90% VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 September 14, 1990 8 Philips Semiconductors Product specification Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics DIP16: plastic dual in-line package; 16 leads (300 mil) 1990 Sep 14 9 74F50109 SOT38-4 Philips Semiconductors Product specification Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics SO16: plastic small outline package; 16 leads; body width 3.9 mm 1990 Sep 14 10 74F50109 SOT109-1 Philips Semiconductors Product specification Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics NOTES 1990 Sep 14 11 74F50109 Philips Semiconductors Product specification Synchronizing dual J-K positiveedge-triggered flip-flop with metastable immune characteristics 74F50109 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. 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