PHILIPS 74F385

Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
FEATURES
PIN CONFIGURATION
• Four independent adders/subtractors
• Two’s complement arithmetic
• Synchronous operation
• Common Clear and Clock
• 74F385 is designed for use with serial multipliers in implementing
CP 1
20 V
CC
F0 2
19 F3
S0 3
18 S3
B0 4
17 B3
A0 5
16 A3
A1 6
15 A2
DESCRIPTION
B1 7
14 B2
The 74F385 contains four independent adder/subtractor elements
with common Clock and Master Reset. Each adder/subtractor
contains a sum flop-flop and a carry flip-flop for synchronous
operations. Flip-flop state changes occur on the rising edge of the
Clock Pulse (CP) input signal. The Select (S) input should be Low
for the Add (A plus B) mode and High for the Subtract (A minus B)
mode. A Low signal on the asynchronous Master Reset (MR) input
clears the sum flip-flop and resets the Carry flip-flop to zero in the
Add mode or presets it to one in the Subtract mode.
S1
8
13 S2
F1 9
12 F2
digital filters and butterfly networks in fast Fourier transforms
GND 10
11 MR
SF00928
TYPE
TYPICAL fMAX
TYPICAL SUPPLY
CURRENT (TOTAL)
140 MHz
55mA
74F385
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
20-pin plastic DIP
N74F385N
20-pin plastic SO
N74F385D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A3
A operand inputs
1.0/1.0
20µA/0.6mA
B0 – B3
B operand inputs
1.0/1.0
20µA/0.6mA
S0 – S3
Function select inputs
1.0/1.0
20µA/0.6mA
CP
Clock pulse input (active rising edge)
1.0/1.0
20µA/0.6mA
MR
Asynchronous Master Reset input (active Low)
1.0/1.0
20µA/0.6mA
F0–F3
Sum or difference outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
50/33
1.0mA/20mA
1989 Sep 20
1
853–0868 97678
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
LOGIC SYMBOL
IEC/IEEE SYMBOL
5
4
6
7
11
15 14 16 17
1
A0 B0 A1 B1 A2 B2 A3 B3
1
CP
11
MR
3
S0
8
S1
13
S2
18
S3
3
5
4
Z1
C2
M3
/P–Q
2D
R
2
P
Q
3CO/ 3BO
4(3CI/ 3BI)
2D
3R
3S
Z4
8
F0 F1 F2 F3
6
9
7
13
2
9
12 19
15
11
14
VCC = Pin 20
GND = Pin 10
SF00929
18
19
16
17
SF00930
FUNCTION TABLE
CARRY
FLIP-FLOP STATE
INPUTS
H
L
X
↑
=
=
=
=
OUTPUTS
MR
S
A
B
Before↑
After↑
L
L
X
X
L
L
L
L
H
X
X
H
H
L
H
L
L
L
L
L
L
H
L
L
L
H
L
H
H
L
L
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
L
L
H
H
L
H
L
H
H
L
H
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
L
L
H
H
L
H
H
L
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
High voltage level
Low voltage level
Don’t care
Low-to-High Clock transition
1989 Sep 20
2
F
OPERATING
MODE
Clear
Add
Subtract
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
LOGIC DIAGRAM
MR 11
A0
B0
S0
SUM
R
5
Q
D
4
2
F0
CP
3
D
CARRY
CP
CP
1
S
Q
R
SUM
R
A1
B1
S1
6
Q
D
7
9
F1
CP
8
D
CARRY
CP
S
Q
R
SUM
R
A2
B2
S2
15
Q
D
14
12
F2
CP
13
D CARRY
CP
S
Q
R
SUM
R
A3 16
B3
S3
Q
D
17
19
F3
CP
18
D
CARRY
CP
S
Q
R
VCC = Pin 20
GND = Pin 10
1989 Sep 20
SF00931
3
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
VCC
Supply voltage
–0.5 to +7.0
V
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5
mA
VOUT
Voltage applied to output in High output state
–0.5 to VCC
V
IOUT
Current applied to output in Low output state
40
mA
Tamb
Operating free-air temperature range
0 to +70
°C
Tstg
Storage temperature
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARMETER
MIN
NOM
MAX
5.0
5.5
UNIT
VCC
Supply voltage
4.5
V
VIH
High-level input voltage
2.0
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
–18
mA
IOH
High-level output current
–1
mA
IOL
Low-level output current
20
mA
Tamb
Operating free-air temperature range
70
°C
V
0
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
TEST
PARAMETER
UNIT
MAX
2.5
VIH = MIN, IOH = MAX
±5%VCC
2.7
VCC = MIN, VIL = MAX,
±10%VCC
0.35
0.50
V
VIH = MIN, IOL = MAX
±5%VCC
0.35
0.50
V
–0.73
–1.2
V
100
µA
VCC = MAX, VI = 2.7V
20
µA
VCC = MAX, VI = 0.5V
–20
µA
–150
mA
VOL
Low-level output voltage
VIK
Input clamp voltage
VCC = MIN, II = IIK
II
Input current at maximum input voltage
VCC = MAX, VI = 7.0V
IIH
High-level input current
IIL
Low-level input current
Short-circuit output
TYP2
±10%VCC
High-level output voltage
IOS
MIN
VCC = MIN, VIL = MAX,
VOH
current3
LIMITS
CONDITIONS1
VCC = MAX
–60
V
3.4
V
ICC
Supply current (total)
VCC = MAX
55
80
mA
Notes:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
1989 Sep 20
4
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MAX
fMAX
Maximum clock frequency
Waveform 1
105
140
tPLH
tPHL
Propagation delay,
Cn to Fn
Waveform 1
3.0
3.5
5.0
5.5
8.0
9.0
2.5
3.5
90
9.0
10.0
MHz
ns
tPLH
Propagation delay, MR to Fn
Waveform 2
4.0
6.5
9.5
4.0
10.5
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MAX
ts (H)
ts (L)
Setup time, High or Low
An, Bn or Sn to CP
Waveform 3
12.0
12.0
12.0
12.0
ns
th (H)
th (L)
Hold time, High or Low
An, Bn or Sn to CP
Waveform 3
0
0
0
0
ns
ts (H)
ts (L)
CP Pulse width
High or Low
Waveform 2
6.0
6.0
6.0
6.0
ns
tw (L)
MR Pulse width
Low
Waveform 2
6.0
6.0
ns
tREC (L)
Recovery time
MR to CP
Waveform 2
8.5
9.5
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performances.
1/fmax
CP
VM
MR
VM
tw(H)
tw(L)
VM
ts(H)
CP
VM
VM
th(H)
VM
ts(L)
Fn
VM
VM
SF00933
Waveform 2. Master Reset Pulse Width,
Master Reset to Output Delay and
Master Reset to Clock Recovery Time
VM
th(L)
VM
SF00934
Waveform 3. Data and Select Setup and Hold Times
1989 Sep 20
tREC
tPHL
VM
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
VM
(L)
CP
tPLH
SF00932
An, Bn, Sn
VM
tW
tPHL
Fn
VM
VM
5
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
TEST CIRCUIT AND WAVEFORM
VCC
NEGATIVE
PULSE
VIN
tw
90%
10%
D.U.T.
RT
CL
RL
AMP (V)
VM
VM
VOUT
PULSE
GENERATOR
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
AMP (V)
90%
POSITIVE
PULSE
VM
VM
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
RL = Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
90%
10%
tw
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00006
1989 Sep 20
6