PHILIPS UAA3202M

INTEGRATED CIRCUITS
DATA SHEET
UAA3202M
Frequency Shift Keying (FSK)
receiver
Preliminary specification
File under Integrated Circuits, IC01
1997 Aug 12
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
FEATURES
GENERAL DESCRIPTION
• Low cost single-chip FSK receiver
The UAA3202M is a fully integrated single-chip receiver,
primarily intended for use in VHF and UHF systems
employing direct Frequency Shift Keying (FSK)
modulation. The UAA3202M incorporates a SAW
stabilized local oscillator, balanced mixer, IF amplifier,
limiter, Received Signal Strength Indicator (RSSI), RSSI
comparator, FSK demodulator, data filter and data slicer.
The device features a power-down mode in order to
minimize the average receiver supply current.
• Superheterodyne architecture with high integration level
• Few external low cost components
• Wide supply voltage range
• Low power consumption
• Wide frequency range, 150 to 450 MHz
• High sensitivity
• IF band determined by application
• High selectivity
• Very low spurious radiation, −60 dBm
(meets FTZ 17TR2100)
• Automotive temperature range
• Power-down mode
• SSOP20 package.
Applications
• Keyless entry systems
• Car alarm systems
• Remote control systems
• Security systems
• Telemetry systems
• Wireless data transmission
• Domestic appliances.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VCC
supply voltage
ICC
supply current for
operating mode on
operating mode off
Psens
sensitivity
Tamb
operating ambient temperature
CONDITIONS
VPWD = 0 V; R2 = 560 Ω
MIN.
TYP.
MAX.
UNIT
3.5
−
6
V
2.0
3.4
4.7
mA
VPWD = VCC
−
3
30
µA
fi = 433.92 MHz;
fmod = 250 Hz square wave;
∆f = ±25 kHz; BER ≤ 3%
−
−
−94
dBm
−40
−
+85
°C
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
UAA3202M
SSOP20
1997 Aug 12
DESCRIPTION
plastic shrink small outline package; 20 leads; body width 5.3 mm
2
VERSION
SOT339-1
1997 Aug 12
3
2
MON MOP
1
3
MIXER
OSC
4
VCC
19 18
VEM MXIN
VCC
1.5 kΩ
1.5 kΩ
IF
AMP
1.4 kΩ
20
handbook, full pagewidth
FA
OSE
5
VEO
6
OSCILLATOR
8
COMP
PHASE
DETECTOR
PHASE
SHIFT
14
DMOD
30 kΩ
Vref
UAA3202M
BUFFER
13
CPC
9
10
CPB CPA
150 kΩ
150 kΩ
BIAS
12
PWD
MHA797
11
DATA
Frequency Shift Keying (FSK) receiver
Fig.1 Block diagram.
VEE
7
Vref
15
RSSI
RSSI
16
LFB
LIMITER
AMPLIFIER
50 kΩ
17
LIN
Philips Semiconductors
Preliminary specification
UAA3202M
BLOCK DIAGRAM
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
PINNING
SYMBOL
PIN
DESCRIPTION
MON
1
negative mixer output
MOP
2
positive mixer output
VCC
3
positive supply voltage
OSC
4
oscillator collector
OSE
5
oscillator emitter
VEO
6
negative supply voltage for oscillator
VEE
7
COMP
handbook, halfpage
MON 1
20 FA
MOP 2
19 VEM
VCC 3
18 MXIN
negative supply voltage
OSC 4
17 LIN
8
RSSI comparator output
OSE 5
CPB
9
comparator input B
VEO 6
CPA
10
comparator input A
VEE 7
DATA
11
data output
PWD
12
power-down control input
CPC
13
comparator input C
DMOD
14
demodulator frequency adjustment
RSSI
15
RSSI current output
LFB
16
limiter feedback
LIN
17
limiter input
MXIN
18
mixer input
VEM
19
negative supply voltage for mixer
FA
20
IF amplifier output
1997 Aug 12
16 LFB
UAA3202M
15 RSSI
14 DMOD
COMP 8
13 CPC
CPB 9
12 PWD
CPA 10
11 DATA
MHA796
Fig.2 Pin configuration.
4
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
FUNCTIONAL DESCRIPTION
Post mixer amplifier
The device is based on the superheterodyne architecture
incorporating a mixer, local oscillator, IF amplifier, limiter,
RSSI, RSSI comparator, FSK demodulator, data filter,
data slicer and power-down circuitry. The device employs
a low IF frequency of typically 1 MHz in order to allow IF
filtering by means of external low cost R, L and C
components. If image rejection is required it can be
achieved by applying a matching external front-end SAW
filter. The device provides a wide IF range of 300 kHz in
order to allow the use of a SAW stabilized oscillator.
The Post Mixer Amplifier (PMA) is a differential input,
single-ended output amplifier. It separates the first and
second IF filters from each other. Amplifier gain is provided
in order to reduce the influence of the limiter noise figure
on the total noise figure.
Limiter
The limiter is a single-ended input multiple stage amplifier
with high total gain. Amplifier stability is achieved by
means of an external DC feedback capacitor, which is also
used to determine the lower limiter cut-off frequency.
An RSSI signal proportional to the limiter input signal is
provided.
The on-chip local oscillator provides the injection signal for
the mixer. Tuning of the on-chip local oscillator is not
necessary. The oscillator frequency is determined by an
external 1-port SAW resonator. The RF input signal is fed
to the mixer and down converted to the IF frequency. After
amplification and filtering the RF signal is applied to a
limiter. The IF filter order and characteristics are
determined by the external low cost R, L and C
components. The limiter amplifier provides a RSSI signal
which can be routed to an on-chip RSSI level comparator
in order to derive a field strength indication for external
use. The limited IF signal is fed to the FSK demodulator.
The demodulator centre frequency is determined by an
external capacitor. No alignment is necessary for the FSK
demodulator. After filtering the demodulated data signal is
fed to a data slicer and is made available at the data
output. The data filter characteristics are determined by
external capacitors. The data slicer employs an adaptive
slice reference in order to track frequency offsets.
IF filters
IF filtering with high selectivity is realized by means of
external low cost R, L and C components. The first IF filter
is located directly following the mixer output. An external
L/C network assembles a band-pass with low sensitivity in
order to meet the bandwidth of an elliptic low-pass filter
external to the device and is located in front of the limiter.
The filter source impedance is determined by the drive
impedance of the IF amplifier. In order to improve the IF
filter selectivity below the pass-band a high-pass
characteristic is added by means of a DC blocking
capacitor in front of the limiter input and by means of the
limiter DC feedback capacitor.
RSSI
The device is switched from power-down to operating
mode and vice versa by means of a control input.
Extremely low supply current is drawn when the device is
in power-down mode. Measures are taken to allow fast
receiver settling when the device is switched from
power-down to operating mode.
The RSSI signal is a current proportional to the limiter input
level (RF input power). By means of an external resistor
the resulting RSSI voltage level is set in order to fit the
application. The RSSI voltage is available to external
circuits and is fed to the input of the RSSI level
comparator. For RSSI filtering an external capacitor is
connected.
Mixer
The mixer is a single balanced emitter coupled mixer with
internal biasing. Matching of the RF source impedance to
the mixer input requires an external matching network.
RSSI level comparator
The RSSI level comparator compares the RSSI level with
a fixed and independent internal reference voltage. If the
RSSI level exceeds the internal reference voltage a logic
HIGH signal is generated. The level comparator provides
some hysteresis in order to avoid spurious oscillation.
The output of the level comparator is designed as an
open-collector with internal pull-up.
Oscillator
The oscillator consists of an on-chip transistor in common
base configuration. An external tank and SAW resonator
determines the oscillator frequency. Oscillator alignment is
not necessary. Oscillator bias is controlled by an external
resistor.
1997 Aug 12
5
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
The other path is fed to an integration circuit with a large
time constant in order to derive the average value
(DC component) as an adaptive slice reference which is
presented to the negative comparator input. The adaptive
reference enables the received data over a large range of
demodulator frequency offsets to be detected.
The integration circuit consists of a simple R/C low-pass
filter with on-chip resistor. The level comparator output is
designed as an open-collector with internal pull-up.
FSK demodulator
The limited IF signal is converted into baseband data by
means of a quadrature FM demodulator consisting of an
all-pass filter and a mixer stage. No alignment of the
demodulator is necessary. The demodulator centre
frequency is set by a capacitor external to the device.
The demodulator provides a large audio bandwidth in
order to allow high data rate applications.
The demodulator can detect a small IF frequency deviation
even if a relatively large IF frequency offset is
encountered.
Power-down circuitry
The device provides a power-down mode. While in
power-down mode the device disables the majority of the
internal circuits and consumes extremely low current.
Measures are taken to allow fast receiver settling when
normal operation is resumed. Thus circuits with large time
constants are only powered down partly or provide a high
impedance during power-down in order to avoid the
discharge of external capacitors as much as possible.
Power-down mode is entered when the control input is
active HIGH. The control input provides an internal pull-up
resistor of high impedance.
Data filters
After demodulation a two-stage data filtering circuit is
provided in order to suppress unwanted frequency
components. Two R/C low-pass filters with on-chip
resistors are provided which are separated by a buffer
stage.
Data slicer
Data detection is provided by means of a level comparator
with adaptive slice reference. After the first data filter stage
the pre-filtered data is split into two parts. One part passes
the second data filter stage and is fed to the positive
comparator input.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
−0.3
+8.0
V
Tamb
operating ambient temperature
−40
+85
°C
Tstg
storage temperature
−55
+125
°C
Vesd
electrostatic handling
pins 4 and 5
−2000
+1500
V
pins 18 and 19
−1500
+2000
V
all other pins
−2000
+2000
V
note 1
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1997 Aug 12
PARAMETER
thermal resistance from junction to ambient in free air
6
VALUE
UNIT
125
K/W
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DC CHARACTERISTICS
VCC = 3.5 V; Tamb = 25 °C; for application diagram see Fig.11; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCC
supply voltage
ICC
supply current for
3.5
−
6
V
3.4
4.7
mA
note 1
operating mode on
VPWD = 0 V;
R2 = 560 Ω
2.0
operating mode off
VPWD = VCC
−
3
30
µA
VPWD(on)
PWD voltage for operating mode ON
0
−
300
mV
VPWD(off)
PWD voltage for operating mode OFF
VCC − 0.3 −
VCC
V
IPWD(on)
PWD current for operating mode ON
VPWD = 0 V
−30
−10
−3
µA
IPWD(off)
PWD current for operating mode OFF
VPWD = VCC
−
1
3
µA
DC operating point pin 4
3.28
3.34
3.40
V
VMXIN(DC)
DC operating point pin 18
0.68
0.78
0.88
V
VMOP(DC)
DC operating point pin 2
2.78
2.98
3.18
V
VMON(DC)
DC operating point pin 1
2.78
2.98
3.18
V
DC operating point pin 20
2.14
2.27
2.40
V
VLIN(DC)
DC operating point pin 17
3.45
3.49
3.50
V
VLFB(DC)
DC operating point pin 16
2.76
2.81
2.86
V
VRSSI(DC)
DC operating point pin 15
2.21
2.36
2.51
V
1.63
1.83
2.03
V
Oscillator
VOSC(DC)
Mixer
Post mixer amplifier
VFA(DC)
Limiter
Demodulator
VDMOD(DC)
DC operating point pin 14
Data slicer
VCPC(DC)
DC operating point pin 13
note 2
1.43
1.93
2.43
V
VCPA(DC)
DC operating point pin 10
note 2
1.43
1.93
2.43
V
VCPB(DC)
DC operating point pin 9
note 2
1.43
1.93
VOH(DAT)
HIGH-level data output voltage
IDATA = −10 µA
VCC − 0.5 −
VOL(DAT)
LOW-level data output voltage
IDATA = 200 µA
0
−
2.43
V
VCC
V
0.6
V
VCC
V
0.6
V
RSSI comparator
VOH(RSSI)
HIGH-level comparator output voltage
IRSSI = −10 µA
VCC − 0.5 −
VOL(RSSI)
LOW-level comparator output voltage
IRSSI = 200 µA
0
−
Notes
1. The given values are valid for the whole temperature range from Tamb = −40 to +85 °C.
2. Tune RF input frequency until IF = 1 MHz.
1997 Aug 12
7
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
AC CHARACTERISTICS
VCC = 3.5 V; Tamb = 25 °C; for application diagram see Fig.11; fi = 433.92 MHz; ∆f = ±25 kHz; fmod = 250 Hz square
wave, i.e. 500 bits/s; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System performance
Psens
sensitivity
BER ≤ 3%
−
−
−94
dBm
Pi(max)
maximum input power
BER ≤ 3%
−
−
−30
dBm
αrad
spurious radiation
note 1
−
−
−60
dBm
tst
receiver settling time
Pi = Psens + 10 dB; see Fig.5
−
2
5
ms
BIF
IF bandwidth range
Pi = Psens + 3 dB
850
1000
1150
kHz
fD
data frequency
140
−
250
Hz
Gmix
mixer conversion gain
31
33
35
dB
Ro(mix)
mixer output resistance
2.7
3
3.3
kΩ
Mixer
Post mixer amplifier
IP3PMA
interception point (mixer + PMA)
note 2
−38
−35
−
dBm
GPMA
PMA gain
note 2
9
10.4
12
dB
P<1dB
compression (mixer + PMA)
Pi = −45 dBm
0
−
1
dBm
BWPMA
PMA LP cut-off frequency
5
−
−
MHz
RoPMA
PMA output resistance
1.2
1.4
1.6
kΩ
Glim
limiter gain
60
63.5
67
dB
Blim
limiter LP cut-off frequency
2
5
8
MHz
Ri(lim)
limiter input resistance
40
50
60
kΩ
0.8
1
1.2
mV
---------kHz
Limiter
Demodulator
GDMOD
demodulator gain
fc(DMOD)
demodulator centre frequency
800
1000
1200
kHz
∆f
frequency deviation
20
25
70
kHz
Ro(DMOD)
demodulator output resistance
24
30
36
kΩ
BDS
data slicer bandwidth
35
50
−
kHz
Ro(DS)
data slicer output resistance
120
150
180
kΩ
note 2
Data slicer
RSSI comparator
Vo(RSSI)
RSSI output voltage
see Fig.3
−
−
−
−
Vo(COMP)
COMP output voltage
see Fig.4
−
−
−
−
Pth(on)
threshold for switching COMP output
voltage to HIGH
−99.5 −95.5 −91.5 dBm
Phys(W)
hysteresis width of COMP output voltage
1
Notes
1. Measured at the RF input connector of the test board.
2. Measured at test point A in Fig.11.
1997 Aug 12
8
2
4
dBm
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
handbook, full pagewidth
UAA3202M
2.8
Vo(RSSI)
(1)
(V)
2.7
(2)
(3)
2.6
2.5
2.4
−100
−90
−80
−70
−60
−50
Pi (dBm)
MHA811
(1) Tamb = 85 °C.
(2) Tamb = 25 °C.
(3) Tamb = −40 °C.
Fig.3 RSSI output voltage as a function of RF input power.
MHA812
handbook, halfpage
Vo(COMP)
(V)
Phys(W)
3.0
0.6
−97.5
−95.5
Pth(ON)
Pi (dBm)
Fig.4 Comparator output voltage as a function of HF input power.
1997 Aug 12
9
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
INTERNAL CIRCUITRY
Table 1
PIN
Equivalent pin circuits and pin voltages for rough test of printed circuit board; VCC = 3.5 V; no input signal
SYMBOL
DC VOLTAGE
(V)
1
MON
2.98
2
MOP
2.98
EQUIVALENT CIRCUIT
VCC
1.5 kΩ
1.5 kΩ
1
2
VEE
MHA798
VEM
3
VCC
−
4
OSC
3.34
5
OSE
−
4
5
6 kΩ
VEE
6
VEO
0
7
VEE
0
8
COMP
−
MHA799
VCC
1 kΩ
8
VEE
9
CPB
1.93
10
CPA
1.93
MHA800
VCC
9
150 kΩ
150 Ω
10
MHA801
1997 Aug 12
10
VEE
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
PIN
11
SYMBOL
DATA
DC VOLTAGE
(V)
UAA3202M
EQUIVALENT CIRCUIT
−
VCC
1 kΩ
11
VEE
12
PWD
−
MHA802
VCC
300 kΩ
12
13
CPC
MHA803
1.93
VCC
30 kΩ
13
MHA804
14
DMOD
1.83
VEE
VCC
14
VEE
MHA805
1997 Aug 12
11
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
PIN
15
SYMBOL
RSSI
DC VOLTAGE
(V)
UAA3202M
EQUIVALENT CIRCUIT
2.36
VCC
MHA806
15
16
LFB
2.81
VCC
16
MHA807
17
LIN
3.49
VCC
50 kΩ
17
MHA808
1997 Aug 12
12
VEE
VEE
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
PIN
SYMBOL
18
MXIN
19
VEM
DC VOLTAGE
(V)
UAA3202M
EQUIVALENT CIRCUIT
0.78
18
0
15 Ω
MHA809
20
FA
2.27
19
VCC
1.2 kΩ
20
VEE
1997 Aug 12
13
MHA810
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
TEST INFORMATION
Tuning procedure for AC tests
1. Turn on the signal generator (fi = 433.92 MHz; no modulation; RF input level = −60 dBm).
2. Tune C6 (RF stage input) to obtain a peak voltage on test point A (see Fig.11).
3. Turn on modulation (fi = 433.92 MHz; fmod = 250 Hz square wave; ∆f = 25 kHz; RF input level = −60 dBm).
4. Check that data is appearing on the data output (pin 11) and proceed with the AC tests.
AC test conditions
Table 2 Test signals
The reference signal level Pref for the following tests is defined as the minimum input level in dBm to give a
BER ≤ 3 × 10−2 (e.g. 15 bit errors per second for 500 bits/s).
TEST
SIGNAL
FREQUENCY
(MHz)
DATA SIGNAL
MODULATION
FREQUENCY
DEVIATION
1
433.92
2
433.92
250 Hz square wave
FM (FSK)
25 kHz
−
no modulation
−
3
433.82
−
no modulation
−
Table 3 Test results
P1 is the maximum available power from signal generator 1 at the input of the test board; P2 is the maximum available
power from signal generator 2 at the input of the test board.
GENERATOR
TEST
RESULT
1
2
Sensitivity into pin MXIN
(see Fig.6)
modulated test
signal 1; P1 ≤ −94 dBm
−
BER ≤ 3 × 10−2
(e.g. 15 bit errors per second for 500 bits/s)
Maximum input power
(see Fig.6)
modulated test
signal 1; P1 ≥ −30 dBm
(minimum Pmax)
−
BER ≤ 3 × 10−2
(e.g. 15 bit errors per second for 500 bits/s)
Receiver turn-on time; note 1
test signal 1;
P1 = Pref + 10 dB
−
check that the first 10 bits are correct; error
counting is started 10 ms after PWD
switched to operating mode: ON
Intercept point (mixer + PMA)
see note 2 and Fig.7
test signal 3;
P1 = −55 dBm
test signal 2;
P2 = P1
IP3 = P1 + 1⁄2 × IM3 (dB); IP3 ≥ −38 dBm
Spurious radiation see note 3
and Fig.8
−
−
no spurious radiation (25 MHz − 1 GHz)
with level higher than −60 dBm
(maximum Pspur)
1 dB compression point
(mixer + PMA) see note 2
and Fig.9
test signal 3;
P11 = −70 dBm;
P12 = −45 dBm
(minimum P1dB)
−
(Po1 + 70 dB) − [Po2 + 45 dB (minimum
P1 dB)] ≤ 1 dB, where Po1, Po2 is the output
power for test signals with P11 or P12,
respectively
Notes
1. The power-down voltage VPWD alternates between operating mode ON (100 ms) and OFF (100 ms); see Fig.5.
2. Probe of spectrum analyzer connected to test point A.
3. Spectrum analyzer connected to the input of the test board.
1997 Aug 12
14
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
handbook, full pagewidth
UAA3202M
VPWD
MHA834
(V)
3.5
0
0
100
200
300
400
500
t (ms)
Fig.5 Timing diagram for pulsed power-down voltage.
GENERATOR 1
50 Ω
BER TEST
FACILITY (2)
TEST CIRCUIT (1)
MED900
(1) For test circuit see Fig.11.
(2) For BER test facility see Fig.10.
Fig.6 Test configuration A (single generator).
GENERATOR 1
50 Ω
50 Ω
2-SIGNAL
POWER
COMBINER
SPECTRUM
ANALYZER
WITH
PROBE
TEST CIRCUIT (1)
GENERATOR 2
50 Ω
IM3
∆f
∆f
∆f
∆f = 100 kHz
MED901
(1) For test circuit see Fig.11.
Fig.7 Test configuration B (IP3).
1997 Aug 12
15
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
SPECTRUM
ANALYZER
INPUT IMPEDANCE
50 Ω
UAA3202M
TEST CIRCUIT (1)
MED902
(1) For test circuit see Fig.11.
Fig.8 Test configuration C (spurious radiation).
GENERATOR 1
50 Ω
SPECTRUM
ANALYZER
WITH
PROBE
TEST CIRCUIT (1)
MED903
(1) For test circuit see Fig.11.
Fig.9 Test configuration D (1 dB compression point).
TX data
SIGNAL
GENERATOR
MASTER
CLOCK
DEVICE
UNDER TEST
RX data
BIT PATTERN
GENERATOR
PRESET
DELAY
delayed
TX data
DATA
COMPARATOR
INTEGRATE
AND DUMP
to error counter
BER TEST BOARD
MED904
Fig.10 BER test facility.
1997 Aug 12
16
1997 Aug 12
17
C1
C3
L5
C7
1
C2
2
3
VCC
1.5 kΩ
1.5 kΩ
PMA
1.4 kΩ
20
C9
C16
C18
4
SAWR
432.92 MHz
L4
R3
MIXER
VCC
19 18
C10
C11
L3
C24
6
RSSI
16
C12
(1)
7
Vref
15
C23
14
C22
8
COMP
PHASE
DETECTOR
PHASE
SHIFT
R4
Fig.11 Application diagram.
R2
5
C25
VCC
LIMITER
AMPLIFIER
17
OSCILLATOR
50 kΩ
C19
test point
A
30 kΩ
BUFFER
Vref
UAA3202M
13
C17
C14
150 kΩ
150 kΩ
BIAS
12
power-down
9
C13
10
MHA814
11
data
output
Frequency Shift Keying (FSK) receiver
(1) Stray inductance.
VCC
C6
C4
C20
L2
andbook, full pagewidth
L1
C5
C8
Philips Semiconductors
Preliminary specification
UAA3202M
APPLICATION INFORMATION
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
Table 4
UAA3202M
Application component list for Fig.11
COMPONENT
VALUE
TOLERANCE
R2
560 Ω
±2%
TC = 50 ppm/K
R3
220 Ω
±2%
TC = 50 ppm/K
R4
820 kΩ
±2%
TC = 50 ppm/K
C1
4.7 µF
±20%
−
C2
150 pF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C3
100 nF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C4
100 pF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C5
2.7 pF
±10%
TC = 0 ±150 ppm/K; tan δ ≤ 30 × 10−4; f = 1 MHz
C6
3 to 10 pF
−
TC = 0 ±300 ppm/K; tan δ ≤ 20 × 10−4; f = 1 MHz
C7
56 pF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C8
33 pF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C9
100 pF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C10
5.6 pF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 20 × 10−4; f = 1 MHz
C11
100 pF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C12
100 nF
±10%
tan δ ≤ 25 × 10−3; f = 1 kHz
C13
2.2 nF
±10%
tan δ ≤ 25 × 10−3; f = 1 kHz
C14
33 nF
±10%
tan δ ≤ 25 × 10−3; f = 1 kHz
C16
3.9 pF
±10%
TC = 0 ±150 ppm/K; tan δ ≤ 30 × 10−4; f = 1 MHz
C17
10 nF
±10%
tan δ ≤ 25 × 10−3; f = 1 kHz
C18
1.8 pF
±10%
TC = 0 ±150 ppm/K; tan δ ≤ 30 × 10−4; f = 1 MHz
C19
39 pF
±10%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C20
3.3 pF
±10%
TC = 0 ±150 ppm/K; tan δ ≤ 30 × 10−4; f = 1 MHz
C22
18 pF
±5%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C23
47 nF
±10%
tan δ ≤ 25 × 10−3; f = 1 kHz
C24
22 pF
±5%
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
C25
1 nF
±10%
tan δ ≤ 25 × 10−3; f = 1 kHz
L1
10 nH
±10%
Qmin = 50 to 450 MHz; TC = 25 to 125 ppm/K
L2
150 µH
±10%
Qmin = 45 to 800 kHz; Cstray ≤ 1 pF
L3
220 µH
±10%
Qmin = 45 to 800 kHz; Cstray ≤ 1 pF
L4
33 nH
±10%
Qmin = 45 to 450 MHz; TC = 25 to 125 ppm/K
L5
470 µH
±10%
Qmin = 45 to 800 kHz; Cstray ≤ 1 pF
Table 5
DESCRIPTION
Surface Acoustic Wave Resonator (SAWR) data
DESCRIPTION
SPECIFICATION
Type
one-port
Centre frequency
432.92 MHz ±75 kHz
Maximum insertion loss
1.5 dB
Typical loaded Q
1600 (50 Ω load)
Temperature drift
0.032 ppm/K2
Turnover temperature
43 °C
1997 Aug 12
18
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
LAYOUT OF PRINTED-CIRCUIT BOARD FOR AC APPLICATION
handbook, full pagewidth
a. Copper side.
C5
L3
L1
R4
C23
C22
C17
C6
C4
C10
C9
C12
C11
C19
C8
C25
DATA
C20
C7
L2
L5
C13
POWER
DOWN
C14
COMP
UAA3202M
C2
C18 C24 C21
C3
L4
C16
R2
VCC
C1
SAWR
R3
MHA813
b. Component side.
Fig.12 Printed-circuit board layout.
1997 Aug 12
19
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
PACKAGE OUTLINE
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
D
SOT339-1
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
w M
bp
e
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.9
0.5
8
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT339-1
1997 Aug 12
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-09-08
95-02-04
MO-150AE
20
o
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Aug 12
UAA3202M
21
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Aug 12
22
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
NOTES
1997 Aug 12
23
UAA3202M
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© Philips Electronics N.V. 1997
SCA55
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Printed in The Netherlands
547027/1200/01/pp24
Date of release: 1997 Aug 12
Document order number:
9397 750 02306