Dynamic Differential Hall Effect Sensor IC TLE 4923 Bipolar IC Features • • • • • • • • • • • • • Advanced performance Higher sensitivity Symmetrical thresholds High piezo resistivity Reduced power consumption South and north pole pre-induction possible AC coupled Digital output signal Two-wire interface Large temperature range Large airgap Low cut-off frequency Protection against reversed polarity Type ▼ TLE 4923 P-SSO-3-6 Ordering Code Package Q62705-K408 P-SSO-3-6 ▼ New type The differential Hall effect sensor TLE 4923 is compatible to the TLE 4921-3U, except for having a 2-wire interface. The TLE 4923 provides high sensitivity, a superior stability over temperature and symmetrical thresholds in order to achieve a stable duty cycle. TLE 4923 is particularly suitable for rotational speed detection and timing applications of ferromagnetic toothed wheels such as in anti-lock braking systems, transmissions, crankshafts, etc. The integrated circuit (based on Hall effect) provides a digital signal output with frequency proportional to the speed of rotation. Unlike other rotational sensors differential Hall ICs are not influenced by radial vibration within the effective airgap of the sensor and require no external signal processing. Semiconductor Group 1 1998-04-29 TLE 4923 Pin Configuration (top view) Center of sensitive area ± 0.15 1.53 2.67 1 2.5 2 3 VS GND C AEP02039 Figure 1 Pin Definitions and Functions Pin No. Symbol Function 1 VS Supply voltage 2 GND Ground 3 C Capacitor Semiconductor Group 2 1998-04-29 TLE 4923 VS 1 Protection Device Internal Reference and Supply Vreg (3V) Hall-Probes 2 3 GND Figure 2 SchmittTrigger HighpassFilter Amplifier CF AEB01896 Block Diagram Semiconductor Group 3 1998-04-29 TLE 4923 Functional Description The Differential Hall sensor IC detects the motion and position of ferromagnetic and permanent magnet structures by measuring the differential flux density of the magnetic field. To detect ferromagnetic objects the magnetic field must be provided by a back biasing permanent magnet (south or north pole of the magnet attached to the rear unmarked side of the IC package). Using an external capacitor the generated Hall voltage signal is slowly adjusted via an active high pass filter with low frequency cut-off. This causes the output to switch into a biased mode after a time constant is elapsed. The time constant is determined by the external capacitor. Filtering avoids aging and temperature influence from Schmitt-trigger input and eliminates device and magnetic offset. The TLE 4923 can be exploited to detect toothed wheel rotation in a rough environment. Jolts against the toothed wheel and ripple have no influence on the output signal. The on and off state of the IC are indicated by high and low current consumption. Circuit Description (see Figure 2) The TLE 4923 is comprised of a supply voltage reference, a pair of Hall probes spaced at 2.5 mm, differential amplifier, filter for offset compensation, Schmitt-trigger, and a switched current source. The TLE 4923 was designed to have a wide range of application parameter variations. Differential fields up to ± 40 mT can be detected without influence to the switching performance. The pre-induction field can either come from a magnetic south or north pole, whereby the field strength up to 500 mT or more will not influence the switching points1). The improved temperature compensation enables a superior sensitivity and accuracy over the temperature range. Finally, the optimized piezo compensation and the integrated dynamic offset compensation enable easy manufacturing and elimination of magnet offsets. Protection is provided at the input/supply (pin 1) for reverse polarity. 1) Differential bias fields exceeding ± 20 mT, e. g. caused by a misaligned magnet, should be avoided. Semiconductor Group 4 1998-04-29 TLE 4923 Absolute Maximum Ratings Parameter Symbol Limit Values min. Supply voltage Capacitor voltage Junction temperature Junction temperature Junction temperature Junction temperature Storage temperature Thermal resistance VS VC Tj Tj Tj Tj TS Rth JA 1) Unit max. – 18 24 V – 0.3 3 V 150 160 170 190 °C °C °C °C 150 °C 190 K/W – 40 Remarks 5000 h 2500 h 500 h 4h 2) 1) Reverse current drawn by the device < 10 mA Can be reduced significantly by further packaging process, e. g. overmolding. The device is ESD protected up to 2 kV (HL test procedure) 2) Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Range Parameter Symbol Limit Values Unit min. max. 4.5 18 V – 40 190 °C Pre-induction VS Tj B0 – 500 500 mT Differential induction ∆B – 40 40 mT Supply voltage Junction temperature Remarks At Hall probe; independent of magnet orientation Note: Unless otherwise noted, all temperatures refer to junction temperature. In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 5 1998-04-29 TLE 4923 AC/DC Characteristics The device characteristics listed below are guaranteed in the full operating range. Parameter Symbol Limit Values Unit min. typ. max. Supply current IS Supply current difference Supply current ratio 4.1 5.3 10.5 13.6 mA mA 1 1 Ison - Isoff 5.0 6.4 8.3 mA 1 ISON / ISOFF ∆Bm 2 2.4 3 – 0.5 0 0.5 mT ∆B = 2.0 mT, f = 200 Hz, – 40 °C < Tj ≤ 150 °C 1) 2) 2 Center of switching points: (∆BOP + ∆BRP) / 2 ∆Bm – 0.7 0 0.7 mT ∆B = 2.0 mT, f = 200 Hz, 150 °C < Tj < 190 °C 1) 2) 2 Hysteresis ∆Bhy 1 2.2 mT ∆B = 2.0 mT, f = 200 Hz 3) 2 0.5 µs 2 0.5 µs 2 25 10 15 µs µs µs f = 10 kHz, ∆B = 5 mT 2 52 kΩ 25 °C ± 2 °C 1 mV/ mT 25 °C ± 2 °C 1 V ∆B = 0 1 Center of switching points: (∆BOP + ∆BRP) / 2 3.1 8.1 Test Condition Test Circuit tr tf Current fall time 4) tdop Delay time tdrp tdop - tdrp 35 Filter input resistance RC Filter sensitivity to ∆B SC 1.5 Current rise time Filter bias voltage Frequency Resistivity against mechanical stress (piezo)6) Semiconductor Group VC f ∆Bm ∆BHy 1.6 43 8.5 2.0 2.4 1 5) 10000 Hz ∆B = 5 mT 2 – 0.1 – 0.1 0.1 0.1 F=2N 2 6 mT mT 1998-04-29 TLE 4923 AC/DC Characteristics (cont’d) The device characteristics listed below are guaranteed in the full operating range. Parameter Symbol Limit Values Unit Test Condition Test Circuit V VS modulated with VPSRR, fPSRR = 10 kHz, tr,fPSRR = 1 µs, ∆B = 0, min. typ. max. Power Supply Rejection Ratio (PSRR) VPSRR 10 27) only 1 transition may occur 1) For ∆B values larger than ± 10 mT this value may exceed the limits as follows: | ∆Bm | < | 0.05 × ∆B | 2) Leakage currents at pin 3 should be avoided. The bias shift of Bm caused by a leakage current IL can be calculated by: ∆ B m = 3) 4) 5) 6) 7) IL × RC ( T ) --------------------SC ( T ) . See also the typical curves on page 17. Differential pre-induction (e.g. by magnetic misalignment) has to be smaller than 20 mT. For definition see Figure 6. 1 Depends on filter capacitor CF. The cut-off frequency is given as f = ---------------------------------------- . The switching points 2 × π × RC × CF are guaranteed over the whole frequency range, but amplitude modification and phase shift have to be taken into account due to the 1st order highpass filter. For definition see Figure 7. For definition see Figure 5. Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at Tj = 25 °C and the given supply voltage. Semiconductor Group 7 1998-04-29 TLE 4923 RP ΙS V SZ 180 Ω 1 VS VLD 1) ΙC VS 3 C 4.7 nF VC 1) Figure 3 RC = GND 2 ΙC ∆VC ∆Ι C AES01897 Test Circuit 1 1 VS 3 C VS CF 1 µF GND 2 AES01898 RS 180 Ω Figure 4 Test Circuit 2 Semiconductor Group 8 1998-04-29 TLE 4923 18 V V PSRR 8V tr tf AED02488 Figure 5 ∆B ∆ B RP t drp : Delay Time between ∆ B = ∆ B RP and Ι S LOW to HIGH transient ∆ B OP t drp t dop : Delay Time between ∆ B = ∆ B OP and Ι S HIGH to LOW transient t dop ΙS AED02509 Figure 6 Definition of Delay Times (switching points related to initial measurement @∆B = 2 mT; f = 200 Hz) F = 2N r = 0.5 ± 0.05 mm IC 4 x d = 1.5 Figure 7 AEA02508 Setup for Piezo Measurements Semiconductor Group 9 1998-04-29 TLE 4923 Application Notes Two possible applications are shown in Figure 10 and Figure 11 (Toothed and Magnet Wheel). Two-wire application is shown in Figure 12. Gear Tooth Sensing In the case of ferromagnetic toothed wheel applications the IC has to be biased by the south or north pole of a permanent magnet (e.g. SmCo5 (Vacuumschmelze VX170) with the dimensions 8 mm × 5 mm × 3 mm) which should cover both Hall probes. The maximum air gap depends on: – the magnetic field strength (magnet used; pre-induction) and – the tooth wheel that is used (dimensions, material, etc.; resulting differential field). a centered distance of Hall probes b Hall probes to IC surface L IC surface to tooth wheel N S b L a a = 2.5 mm b = 0.3 mm Figure 8 AEA01259 Sensor Spacing Conversion DIN – ASA T m = 25.4 mm/p T = 25.4 mm CP d AEA01260 DIN ASA d diameter (mm) p diameter pitch p z number of teeth PD pitch diameter PD = z/p (inch) m module m = d/z (mm) CP circular pitch T pitch T = π × m (mm) Figure 9 = z/d (inch) CP = 1 inch × π/p Tooth Wheel Dimensions Semiconductor Group 10 1998-04-29 TLE 4923 Gear Wheel Hall Sensor 1 Hall Sensor 2 Signal Processing S (N) Circuitry Permanent Magnet N (S) AEA01261 Figure 10 TLE 4923, with Ferromagnetic Toothed Wheel Magnet Wheel S S N Hall Sensor 2 Hall Sensor 1 Signal Processing AEA01262 Circuitry Figure 11 TLE 4923, with Magnet Wheel Semiconductor Group 11 1998-04-29 TLE 4923 Two-wire-application Line 1 VS 3 VS 1 CS 4.7 nF C GND 2 CF 1 µF VSIGNAL RS Sensor Mainframe typical : R S = 180 Ω AES01899 Figure 12 Application Circuit Semiconductor Group 12 1998-04-29 TLE 4923 N(S) S(N) 1 3 B1 B2 Wheel Profile Missing Tooth Magnetic Field Difference Small Airgap ∆ B = B2-B1 Large Airgap ∆ B RP = 0.75 mT ∆ B HY ∆ B OP = -0.75 mT Output Signal ΙS Operate point : B2-B1< ∆ B OP switches the output ON high current Release point : B2-B1> ∆ BRP switches the output OFF low ∆ B RP = ∆ BOP + ∆ B HY ( The magnetic field is defined as positive if the south pole of the magnet shows towards the rear side of the IC housing. ( AED01900 Figure 13 System Operation Semiconductor Group 13 1998-04-29 TLE 4923 If not otherwise specified, all curves reflect typical values at Tj = 25 °C and VS = 12 V. Supply Current and Supply Current Minimum Switching Field versus Difference versus Supply Voltage Frequency AED02473 12 ΙS mA Ι SON 10 B min 8 T j = 150 C T j = 25 C Ι SON Ι SOFF 0.6 Ι SOFF 4 T j = -40 C 0.4 2 0.2 0 5 15 10 0 20 V 25 VS Supply Current and Supply Current Difference versus Temperature ΙS T j = 190 C 1.0 0.8 6 0 AED02475 1.2 mT 12 mA 100 1000 Hz 10000 f Mean Value of Switching Induction AED02474 Ι SON ∆B m 10 8 6 10 1 AED02476 1.2 mT 1.0 0.8 Ι SON Ι SOFF 0.6 Ι SOFF 0.4 4 ∆B OP ∆B RP 2 f = 200 Hz ∆B m = 0.2 2 typ 0 -40 0 40 80 Semiconductor Group 120 C Tj 0 -40 200 14 0 40 80 120 C Tj 200 1998-04-29 TLE 4923 Delay Time1) versus Temperature Hysteresis versus Temperature AED02477 1.6 mT ∆B HY 1.4 typ 1.2 AED02479 8 µs td 7 t dop t drp 6 ∆B HY = ∆B RP ∆B OP 5 f = 200 Hz 4 1.0 3 0.8 2 0.6 1 0.4 -40 0 40 80 120 0 -50 200 C Tj Delay Time1) versus Differential Field 50 100 150 C 200 Tj Rise and Fall Time versus Temperature AED02478 6.0 µs 5.9 td 0 AED02480 140 ns f = 10 kHz t 120 5.8 tf 100 5.7 tr 5.6 80 5.5 t dop 60 5.4 5.3 40 5.2 t drp 5.1 5.0 1) 0 2 4 6 8 mT ∆B 20 0 -50 12 0 50 100 150 C 200 Tj Switching points related to initial measurement @∆B = 2 mT, f = 200 Hz Semiconductor Group 15 1998-04-29 TLE 4923 Capacitor Voltage versus Temperature Filter Input Resistance versus Temperature AED02481 2.5 VC V RC AED02483 60 kΩ 50 2.0 typ typ 40 1.5 30 1.0 20 0.5 0 -50 10 0 50 100 0 -50 150 C 200 Tj 0 50 100 Delay Time tpon for Power ON versus Temperature Filter Sensitivity versus Temperature AED02482 0 mV/mT S C -2 150 C 200 Tj AED02484 0.8 ms/nF t pon = k C F (nF) k 0.7 max.1) -4 0.6 -6 typ 0.5 -8 VS = 12 V -10 0.4 -12 min.1) 0.3 -14 0.2 -16 0.1 -18 -20 -50 0 50 100 0 -50 150 C 200 Tj 1) Semiconductor Group 16 0 50 100 150 C 200 Tj Calculated values for minimum and maximum filter resistance, C F at room temperature. 1998-04-29 TLE 4923 Threshold Shift versus Filter Leakage AED02485 8 mT ∆B m 7 6 5 4 +190˚C +100˚C +25˚C -40˚C 3 2 1 0 0 20 40 Semiconductor Group 60 80 MΩ 100 RC 17 1998-04-29 TLE 4923 Package Outline 1 max. 1 x 45˚ 1 -0.1 0.25 ±0.05 1.2 ±0.1 12.7 ±1 0.2 1.9 max. 0.2 +0.1 1.67 ±0.05 1 2 3 18 ±0.5 9 -0.5 3.81 1 -1 1.9 max. 0.4 ±0.05 6 ±0.5 0.6 max. 23.8 ±0.5 38 max. 0.87 ±0.05 +0.75 0.65 ±0.1 (0.25) 3.38 ±0.06 3.71 ±0.08 5.16 ±0.08 5.38 ±0.05 0.15 max. P-SSO-3-6 (Plastic Single Small Outline Package) Adhesive Tape 0.25 -0.15 Tape 6.35 ±0.4 4 ±0.3 0.5 ±0.1 12.7 ±0.3 GPO05960 d Branded Side Hall-Probe d : Distance chip to upper side of IC P-SSO-3-6 : 0.3 ±0.08 mm AEA02510 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Semiconductor Group 18 Dimensions in mm 1998-04-29